415 строки
7.8 KiB
ArmAsm
415 строки
7.8 KiB
ArmAsm
/*
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*
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* linux/arch/h8300/kernel/entry.S
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*
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* Yoshinori Sato <ysato@users.sourceforge.jp>
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* David McCullough <davidm@snapgear.com>
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*
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*/
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/*
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* entry.S
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* include exception/interrupt gateway
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* system call entry
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*/
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#include <linux/sys.h>
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#include <asm/unistd.h>
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#include <asm/setup.h>
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#include <asm/segment.h>
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#include <asm/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/thread_info.h>
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#include <asm/errno.h>
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#if defined(CONFIG_CPU_H8300H)
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#define USERRET 8
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INTERRUPTS = 64
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.h8300h
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.macro SHLL2 reg
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shll.l \reg
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shll.l \reg
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.endm
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.macro SHLR2 reg
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shlr.l \reg
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shlr.l \reg
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.endm
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.macro SAVEREGS
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mov.l er0,@-sp
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mov.l er1,@-sp
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mov.l er2,@-sp
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mov.l er3,@-sp
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.endm
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.macro RESTOREREGS
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mov.l @sp+,er3
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mov.l @sp+,er2
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.endm
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.macro SAVEEXR
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.endm
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.macro RESTOREEXR
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.endm
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#endif
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#if defined(CONFIG_CPU_H8S)
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#define USERRET 10
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#define USEREXR 8
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INTERRUPTS = 128
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.h8300s
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.macro SHLL2 reg
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shll.l #2,\reg
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.endm
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.macro SHLR2 reg
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shlr.l #2,\reg
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.endm
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.macro SAVEREGS
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stm.l er0-er3,@-sp
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.endm
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.macro RESTOREREGS
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ldm.l @sp+,er2-er3
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.endm
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.macro SAVEEXR
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mov.w @(USEREXR:16,er0),r1
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mov.w r1,@(LEXR-LER3:16,sp) /* copy EXR */
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.endm
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.macro RESTOREEXR
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mov.w @(LEXR-LER1:16,sp),r1 /* restore EXR */
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mov.b r1l,r1h
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mov.w r1,@(USEREXR:16,er0)
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.endm
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#endif
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/* CPU context save/restore macros. */
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.macro SAVE_ALL
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mov.l er0,@-sp
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stc ccr,r0l /* check kernel mode */
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btst #4,r0l
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bne 5f
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/* user mode */
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mov.l sp,@_sw_usp
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mov.l @sp,er0 /* restore saved er0 */
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orc #0x10,ccr /* switch kernel stack */
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mov.l @_sw_ksp,sp
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sub.l #(LRET-LORIG),sp /* allocate LORIG - LRET */
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SAVEREGS
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mov.l @_sw_usp,er0
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mov.l @(USERRET:16,er0),er1 /* copy the RET addr */
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mov.l er1,@(LRET-LER3:16,sp)
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SAVEEXR
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mov.l @(LORIG-LER3:16,sp),er0
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mov.l er0,@(LER0-LER3:16,sp) /* copy ER0 */
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mov.w e1,r1 /* e1 highbyte = ccr */
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and #0xef,r1h /* mask mode? flag */
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bra 6f
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5:
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/* kernel mode */
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mov.l @sp,er0 /* restore saved er0 */
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subs #2,sp /* set dummy ccr */
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subs #4,sp /* set dummp sp */
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SAVEREGS
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mov.w @(LRET-LER3:16,sp),r1 /* copy old ccr */
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6:
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mov.b r1h,r1l
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mov.b #0,r1h
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mov.w r1,@(LCCR-LER3:16,sp) /* set ccr */
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mov.l @_sw_usp,er2
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mov.l er2,@(LSP-LER3:16,sp) /* set usp */
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mov.l er6,@-sp /* syscall arg #6 */
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mov.l er5,@-sp /* syscall arg #5 */
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mov.l er4,@-sp /* syscall arg #4 */
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.endm /* r1 = ccr */
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.macro RESTORE_ALL
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mov.l @sp+,er4
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mov.l @sp+,er5
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mov.l @sp+,er6
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RESTOREREGS
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mov.w @(LCCR-LER1:16,sp),r0 /* check kernel mode */
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btst #4,r0l
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bne 7f
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orc #0xc0,ccr
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mov.l @(LSP-LER1:16,sp),er0
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mov.l @(LER0-LER1:16,sp),er1 /* restore ER0 */
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mov.l er1,@er0
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RESTOREEXR
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mov.w @(LCCR-LER1:16,sp),r1 /* restore the RET addr */
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mov.b r1l,r1h
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mov.b @(LRET+1-LER1:16,sp),r1l
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mov.w r1,e1
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mov.w @(LRET+2-LER1:16,sp),r1
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mov.l er1,@(USERRET:16,er0)
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mov.l @sp+,er1
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add.l #(LRET-LER1),sp /* remove LORIG - LRET */
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mov.l sp,@_sw_ksp
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andc #0xef,ccr /* switch to user mode */
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mov.l er0,sp
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bra 8f
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7:
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mov.l @sp+,er1
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add.l #10,sp
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8:
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mov.l @sp+,er0
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adds #4,sp /* remove the sw created LVEC */
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rte
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.endm
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.globl _system_call
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.globl ret_from_exception
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.globl ret_from_fork
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.globl ret_from_kernel_thread
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.globl ret_from_interrupt
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.globl _interrupt_redirect_table
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.globl _sw_ksp,_sw_usp
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.globl _resume
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.globl _interrupt_entry
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.globl _trace_break
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.globl _nmi
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#if defined(CONFIG_ROMKERNEL)
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.section .int_redirect,"ax"
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_interrupt_redirect_table:
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#if defined(CONFIG_CPU_H8300H)
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.rept 7
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.long 0
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.endr
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#endif
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#if defined(CONFIG_CPU_H8S)
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.rept 5
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.long 0
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.endr
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jmp @_trace_break
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.long 0
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#endif
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jsr @_interrupt_entry /* NMI */
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jmp @_system_call /* TRAPA #0 (System call) */
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.long 0
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.long 0
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jmp @_trace_break /* TRAPA #3 (breakpoint) */
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.rept INTERRUPTS-12
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jsr @_interrupt_entry
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.endr
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#endif
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#if defined(CONFIG_RAMKERNEL)
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.globl _interrupt_redirect_table
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.section .bss
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_interrupt_redirect_table:
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.space 4
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#endif
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.section .text
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.align 2
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_interrupt_entry:
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SAVE_ALL
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/* r1l is saved ccr */
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mov.l sp,er0
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add.l #LVEC,er0
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btst #4,r1l
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bne 1f
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/* user LVEC */
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mov.l @_sw_usp,er0
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adds #4,er0
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1:
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mov.l @er0,er0 /* LVEC address */
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#if defined(CONFIG_ROMKERNEL)
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sub.l #_interrupt_redirect_table,er0
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#endif
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#if defined(CONFIG_RAMKERNEL)
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mov.l @_interrupt_redirect_table,er1
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sub.l er1,er0
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#endif
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SHLR2 er0
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dec.l #1,er0
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mov.l sp,er1
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subs #4,er1 /* adjust ret_pc */
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#if defined(CONFIG_CPU_H8S)
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orc #7,exr
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#endif
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jsr @do_IRQ
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jmp @ret_from_interrupt
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_system_call:
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subs #4,sp /* dummy LVEC */
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SAVE_ALL
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/* er0: syscall nr */
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andc #0xbf,ccr
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mov.l er0,er4
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/* save top of frame */
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mov.l sp,er0
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jsr @set_esp0
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mov.l sp,er2
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and.w #0xe000,r2
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mov.l @(TI_FLAGS:16,er2),er2
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and.w #_TIF_WORK_SYSCALL_MASK,r2
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beq 1f
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mov.l sp,er0
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jsr @do_syscall_trace_enter
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1:
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cmp.l #__NR_syscalls,er4
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bcc badsys
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SHLL2 er4
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mov.l #_sys_call_table,er0
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add.l er4,er0
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mov.l @er0,er4
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beq ret_from_exception:16
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mov.l @(LER1:16,sp),er0
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mov.l @(LER2:16,sp),er1
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mov.l @(LER3:16,sp),er2
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jsr @er4
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mov.l er0,@(LER0:16,sp) /* save the return value */
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mov.l sp,er2
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and.w #0xe000,r2
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mov.l @(TI_FLAGS:16,er2),er2
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and.w #_TIF_WORK_SYSCALL_MASK,r2
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beq 2f
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mov.l sp,er0
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jsr @do_syscall_trace_leave
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2:
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orc #0xc0,ccr
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bra resume_userspace
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badsys:
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mov.l #-ENOSYS,er0
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mov.l er0,@(LER0:16,sp)
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bra resume_userspace
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#if !defined(CONFIG_PREEMPT)
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#define resume_kernel restore_all
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#endif
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ret_from_exception:
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#if defined(CONFIG_PREEMPT)
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orc #0xc0,ccr
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#endif
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ret_from_interrupt:
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mov.b @(LCCR+1:16,sp),r0l
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btst #4,r0l
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bne resume_kernel:16 /* return from kernel */
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resume_userspace:
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andc #0xbf,ccr
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mov.l sp,er4
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and.w #0xe000,r4 /* er4 <- current thread info */
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mov.l @(TI_FLAGS:16,er4),er1
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and.l #_TIF_WORK_MASK,er1
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beq restore_all:8
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work_pending:
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btst #TIF_NEED_RESCHED,r1l
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bne work_resched:8
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/* work notifysig */
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mov.l sp,er0
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subs #4,er0 /* er0: pt_regs */
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jsr @do_notify_resume
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bra resume_userspace:8
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work_resched:
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mov.l sp,er0
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jsr @set_esp0
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jsr @schedule
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bra resume_userspace:8
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restore_all:
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RESTORE_ALL /* Does RTE */
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#if defined(CONFIG_PREEMPT)
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resume_kernel:
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mov.l @(TI_PRE_COUNT:16,er4),er0
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bne restore_all:8
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need_resched:
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mov.l @(TI_FLAGS:16,er4),er0
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btst #TIF_NEED_RESCHED,r0l
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beq restore_all:8
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mov.b @(LCCR+1:16,sp),r0l /* Interrupt Enabled? */
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bmi restore_all:8
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mov.l sp,er0
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jsr @set_esp0
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jsr @preempt_schedule_irq
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bra need_resched:8
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#endif
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ret_from_fork:
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mov.l er2,er0
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jsr @schedule_tail
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jmp @ret_from_exception
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ret_from_kernel_thread:
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mov.l er2,er0
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jsr @schedule_tail
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mov.l @(LER4:16,sp),er0
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mov.l @(LER5:16,sp),er1
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jsr @er1
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jmp @ret_from_exception
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_resume:
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/*
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* Beware - when entering resume, offset of tss is in d1,
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* prev (the current task) is in a0, next (the new task)
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* is in a1 and d2.b is non-zero if the mm structure is
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* shared between the tasks, so don't change these
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* registers until their contents are no longer needed.
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*/
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/* save sr */
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sub.w r3,r3
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stc ccr,r3l
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mov.w r3,@(THREAD_CCR+2:16,er0)
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/* disable interrupts */
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orc #0xc0,ccr
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mov.l @_sw_usp,er3
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mov.l er3,@(THREAD_USP:16,er0)
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mov.l sp,@(THREAD_KSP:16,er0)
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/* Skip address space switching if they are the same. */
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/* FIXME: what did we hack out of here, this does nothing! */
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mov.l @(THREAD_USP:16,er1),er0
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mov.l er0,@_sw_usp
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mov.l @(THREAD_KSP:16,er1),sp
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/* restore status register */
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mov.w @(THREAD_CCR+2:16,er1),r3
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ldc r3l,ccr
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rts
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_trace_break:
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subs #4,sp
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SAVE_ALL
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sub.l er1,er1
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dec.l #1,er1
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mov.l er1,@(LORIG,sp)
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mov.l sp,er0
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jsr @set_esp0
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mov.l @_sw_usp,er0
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mov.l @er0,er1
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mov.w @(-2:16,er1),r2
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cmp.w #0x5730,r2
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beq 1f
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subs #2,er1
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mov.l er1,@er0
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1:
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and.w #0xff,e1
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mov.l er1,er0
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jsr @trace_trap
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jmp @ret_from_exception
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_nmi:
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subs #4, sp
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mov.l er0, @-sp
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mov.l @_interrupt_redirect_table, er0
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add.l #8*4, er0
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mov.l er0, @(4,sp)
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mov.l @sp+, er0
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jmp @_interrupt_entry
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.section .bss
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_sw_ksp:
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.space 4
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_sw_usp:
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.space 4
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.end
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