243 строки
6.2 KiB
C
243 строки
6.2 KiB
C
/*
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* Device Tree support for Armada 370 and XP platforms.
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/io.h>
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#include <linux/clocksource.h>
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#include <linux/dma-mapping.h>
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#include <linux/mbus.h>
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#include <linux/signal.h>
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#include <linux/slab.h>
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#include <linux/irqchip.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/smp_scu.h>
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#include "armada-370-xp.h"
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#include "common.h"
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#include "coherency.h"
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#include "mvebu-soc-id.h"
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static void __iomem *scu_base;
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/*
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* Enables the SCU when available. Obviously, this is only useful on
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* Cortex-A based SOCs, not on PJ4B based ones.
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*/
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static void __init mvebu_scu_enable(void)
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{
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struct device_node *np =
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of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
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if (np) {
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scu_base = of_iomap(np, 0);
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scu_enable(scu_base);
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of_node_put(np);
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}
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}
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void __iomem *mvebu_get_scu_base(void)
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{
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return scu_base;
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}
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/*
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* Early versions of Armada 375 SoC have a bug where the BootROM
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* leaves an external data abort pending. The kernel is hit by this
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* data abort as soon as it enters userspace, because it unmasks the
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* data aborts at this moment. We register a custom abort handler
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* below to ignore the first data abort to work around this
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* problem.
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*/
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static int armada_375_external_abort_wa(unsigned long addr, unsigned int fsr,
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struct pt_regs *regs)
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{
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static int ignore_first;
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if (!ignore_first && fsr == 0x1406) {
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ignore_first = 1;
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return 0;
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}
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return 1;
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}
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static void __init mvebu_init_irq(void)
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{
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irqchip_init();
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mvebu_scu_enable();
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coherency_init();
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BUG_ON(mvebu_mbus_dt_init(coherency_available()));
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}
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static void __init external_abort_quirk(void)
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{
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u32 dev, rev;
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if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > ARMADA_375_Z1_REV)
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return;
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hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0,
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"imprecise external abort");
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}
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static void __init i2c_quirk(void)
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{
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struct device_node *np;
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u32 dev, rev;
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/*
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* Only revisons more recent than A0 support the offload
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* mechanism. We can exit only if we are sure that we can
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* get the SoC revision and it is more recent than A0.
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*/
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if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > MV78XX0_A0_REV)
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return;
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for_each_compatible_node(np, NULL, "marvell,mv78230-i2c") {
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struct property *new_compat;
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new_compat = kzalloc(sizeof(*new_compat), GFP_KERNEL);
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new_compat->name = kstrdup("compatible", GFP_KERNEL);
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new_compat->length = sizeof("marvell,mv78230-a0-i2c");
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new_compat->value = kstrdup("marvell,mv78230-a0-i2c",
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GFP_KERNEL);
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of_update_property(np, new_compat);
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}
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return;
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}
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#define A375_Z1_THERMAL_FIXUP_OFFSET 0xc
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static void __init thermal_quirk(void)
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{
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struct device_node *np;
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u32 dev, rev;
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int res;
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/*
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* The early SoC Z1 revision needs a quirk to be applied in order
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* for the thermal controller to work properly. This quirk breaks
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* the thermal support if applied on a SoC that doesn't need it,
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* so we enforce the SoC revision to be known.
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*/
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res = mvebu_get_soc_id(&dev, &rev);
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if (res < 0 || (res == 0 && rev > ARMADA_375_Z1_REV))
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return;
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for_each_compatible_node(np, NULL, "marvell,armada375-thermal") {
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struct property *prop;
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__be32 newval, *newprop, *oldprop;
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int len;
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/*
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* The register offset is at a wrong location. This quirk
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* creates a new reg property as a clone of the previous
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* one and corrects the offset.
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*/
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oldprop = (__be32 *)of_get_property(np, "reg", &len);
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if (!oldprop)
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continue;
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/* Create a duplicate of the 'reg' property */
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prop = kzalloc(sizeof(*prop), GFP_KERNEL);
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prop->length = len;
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prop->name = kstrdup("reg", GFP_KERNEL);
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prop->value = kzalloc(len, GFP_KERNEL);
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memcpy(prop->value, oldprop, len);
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/* Fixup the register offset of the second entry */
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oldprop += 2;
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newprop = (__be32 *)prop->value + 2;
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newval = cpu_to_be32(be32_to_cpu(*oldprop) -
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A375_Z1_THERMAL_FIXUP_OFFSET);
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*newprop = newval;
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of_update_property(np, prop);
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/*
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* The thermal controller needs some quirk too, so let's change
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* the compatible string to reflect this and allow the driver
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* the take the necessary action.
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*/
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prop = kzalloc(sizeof(*prop), GFP_KERNEL);
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prop->name = kstrdup("compatible", GFP_KERNEL);
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prop->length = sizeof("marvell,armada375-z1-thermal");
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prop->value = kstrdup("marvell,armada375-z1-thermal",
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GFP_KERNEL);
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of_update_property(np, prop);
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}
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return;
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}
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static void __init mvebu_dt_init(void)
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{
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if (of_machine_is_compatible("plathome,openblocks-ax3-4"))
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i2c_quirk();
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if (of_machine_is_compatible("marvell,a375-db")) {
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external_abort_quirk();
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thermal_quirk();
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}
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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}
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static const char * const armada_370_xp_dt_compat[] = {
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"marvell,armada-370-xp",
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NULL,
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};
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DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)")
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.l2c_aux_val = 0,
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.l2c_aux_mask = ~0,
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.smp = smp_ops(armada_xp_smp_ops),
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.init_machine = mvebu_dt_init,
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.init_irq = mvebu_init_irq,
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.restart = mvebu_restart,
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.dt_compat = armada_370_xp_dt_compat,
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MACHINE_END
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static const char * const armada_375_dt_compat[] = {
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"marvell,armada375",
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NULL,
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};
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DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")
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.l2c_aux_val = 0,
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.l2c_aux_mask = ~0,
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.init_irq = mvebu_init_irq,
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.init_machine = mvebu_dt_init,
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.restart = mvebu_restart,
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.dt_compat = armada_375_dt_compat,
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MACHINE_END
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static const char * const armada_38x_dt_compat[] = {
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"marvell,armada380",
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"marvell,armada385",
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NULL,
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};
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DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")
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.l2c_aux_val = 0,
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.l2c_aux_mask = ~0,
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.init_irq = mvebu_init_irq,
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.restart = mvebu_restart,
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.dt_compat = armada_38x_dt_compat,
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MACHINE_END
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