339 строки
10 KiB
C
339 строки
10 KiB
C
/*
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* Copyright 2010 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#include <drm/drmP.h>
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "nid.h"
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u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev);
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/*
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* DMA
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* Starting with R600, the GPU has an asynchronous
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* DMA engine. The programming model is very similar
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* to the 3D engine (ring buffer, IBs, etc.), but the
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* DMA controller has it's own packet format that is
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* different form the PM4 format used by the 3D engine.
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* It supports copying data, writing embedded data,
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* solid fills, and a number of other things. It also
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* has support for tiling/detiling of buffers.
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* Cayman and newer support two asynchronous DMA engines.
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*/
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/**
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* cayman_dma_ring_ib_execute - Schedule an IB on the DMA engine
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*
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* @rdev: radeon_device pointer
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* @ib: IB object to schedule
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*
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* Schedule an IB in the DMA ring (cayman-SI).
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*/
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void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
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struct radeon_ib *ib)
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{
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struct radeon_ring *ring = &rdev->ring[ib->ring];
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if (rdev->wb.enabled) {
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u32 next_rptr = ring->wptr + 4;
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while ((next_rptr & 7) != 5)
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next_rptr++;
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next_rptr += 3;
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
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radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
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radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
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radeon_ring_write(ring, next_rptr);
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}
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/* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
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* Pad as necessary with NOPs.
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*/
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while ((ring->wptr & 7) != 5)
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
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radeon_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, ib->vm ? ib->vm->id : 0, 0));
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radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
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radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
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}
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/**
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* cayman_dma_stop - stop the async dma engines
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*
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* @rdev: radeon_device pointer
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*
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* Stop the async dma engines (cayman-SI).
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*/
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void cayman_dma_stop(struct radeon_device *rdev)
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{
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u32 rb_cntl;
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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/* dma0 */
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rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
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rb_cntl &= ~DMA_RB_ENABLE;
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WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl);
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/* dma1 */
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rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
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rb_cntl &= ~DMA_RB_ENABLE;
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WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl);
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rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
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rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;
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}
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/**
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* cayman_dma_resume - setup and start the async dma engines
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*
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* @rdev: radeon_device pointer
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*
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* Set up the DMA ring buffers and enable them. (cayman-SI).
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* Returns 0 for success, error for failure.
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*/
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int cayman_dma_resume(struct radeon_device *rdev)
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{
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struct radeon_ring *ring;
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u32 rb_cntl, dma_cntl, ib_cntl;
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u32 rb_bufsz;
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u32 reg_offset, wb_offset;
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int i, r;
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/* Reset dma */
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WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
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RREG32(SRBM_SOFT_RESET);
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udelay(50);
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WREG32(SRBM_SOFT_RESET, 0);
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for (i = 0; i < 2; i++) {
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if (i == 0) {
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ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
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reg_offset = DMA0_REGISTER_OFFSET;
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wb_offset = R600_WB_DMA_RPTR_OFFSET;
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} else {
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ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
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reg_offset = DMA1_REGISTER_OFFSET;
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wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET;
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}
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WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
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WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
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/* Set ring buffer size in dwords */
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rb_bufsz = order_base_2(ring->ring_size / 4);
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rb_cntl = rb_bufsz << 1;
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#ifdef __BIG_ENDIAN
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rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
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#endif
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WREG32(DMA_RB_CNTL + reg_offset, rb_cntl);
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/* Initialize the ring buffer's read and write pointers */
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WREG32(DMA_RB_RPTR + reg_offset, 0);
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WREG32(DMA_RB_WPTR + reg_offset, 0);
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/* set the wb address whether it's enabled or not */
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WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset,
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upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF);
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WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset,
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((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
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if (rdev->wb.enabled)
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rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
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WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8);
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/* enable DMA IBs */
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ib_cntl = DMA_IB_ENABLE | CMD_VMID_FORCE;
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#ifdef __BIG_ENDIAN
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ib_cntl |= DMA_IB_SWAP_ENABLE;
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#endif
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WREG32(DMA_IB_CNTL + reg_offset, ib_cntl);
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dma_cntl = RREG32(DMA_CNTL + reg_offset);
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dma_cntl &= ~CTXEMPTY_INT_ENABLE;
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WREG32(DMA_CNTL + reg_offset, dma_cntl);
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ring->wptr = 0;
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WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2);
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ring->rptr = RREG32(DMA_RB_RPTR + reg_offset) >> 2;
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WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE);
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ring->ready = true;
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r = radeon_ring_test(rdev, ring->idx, ring);
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if (r) {
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ring->ready = false;
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return r;
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}
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}
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
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return 0;
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}
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/**
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* cayman_dma_fini - tear down the async dma engines
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*
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* @rdev: radeon_device pointer
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*
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* Stop the async dma engines and free the rings (cayman-SI).
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*/
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void cayman_dma_fini(struct radeon_device *rdev)
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{
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cayman_dma_stop(rdev);
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radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
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radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
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}
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/**
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* cayman_dma_is_lockup - Check if the DMA engine is locked up
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring structure holding ring information
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*
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* Check if the async DMA engine is locked up.
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* Returns true if the engine appears to be locked up, false if not.
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*/
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bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
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u32 mask;
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if (ring->idx == R600_RING_TYPE_DMA_INDEX)
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mask = RADEON_RESET_DMA;
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else
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mask = RADEON_RESET_DMA1;
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if (!(reset_mask & mask)) {
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radeon_ring_lockup_update(ring);
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return false;
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}
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/* force ring activities */
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radeon_ring_force_activity(rdev, ring);
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return radeon_ring_test_lockup(rdev, ring);
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}
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/**
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* cayman_dma_vm_set_page - update the page tables using the DMA
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*
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* @rdev: radeon_device pointer
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* @ib: indirect buffer to fill with commands
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* @pe: addr of the page entry
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* @addr: dst addr to write into pe
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* @count: number of page entries to update
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* @incr: increase next addr by incr bytes
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* @flags: access flags
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* @r600_flags: hw access flags
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*
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* Update the page tables using the DMA (cayman/TN).
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*/
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void cayman_dma_vm_set_page(struct radeon_device *rdev,
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struct radeon_ib *ib,
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uint64_t pe,
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uint64_t addr, unsigned count,
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uint32_t incr, uint32_t flags)
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{
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uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
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uint64_t value;
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unsigned ndw;
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if ((flags & RADEON_VM_PAGE_SYSTEM) || (count == 1)) {
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while (count) {
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ndw = count * 2;
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if (ndw > 0xFFFFE)
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ndw = 0xFFFFE;
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/* for non-physically contiguous pages (system) */
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ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw);
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ib->ptr[ib->length_dw++] = pe;
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ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
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for (; ndw > 0; ndw -= 2, --count, pe += 8) {
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if (flags & RADEON_VM_PAGE_SYSTEM) {
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value = radeon_vm_map_gart(rdev, addr);
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value &= 0xFFFFFFFFFFFFF000ULL;
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} else if (flags & RADEON_VM_PAGE_VALID) {
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value = addr;
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} else {
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value = 0;
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}
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addr += incr;
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value |= r600_flags;
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ib->ptr[ib->length_dw++] = value;
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ib->ptr[ib->length_dw++] = upper_32_bits(value);
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}
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}
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} else {
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while (count) {
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ndw = count * 2;
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if (ndw > 0xFFFFE)
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ndw = 0xFFFFE;
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if (flags & RADEON_VM_PAGE_VALID)
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value = addr;
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else
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value = 0;
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/* for physically contiguous pages (vram) */
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ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw);
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ib->ptr[ib->length_dw++] = pe; /* dst addr */
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ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
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ib->ptr[ib->length_dw++] = r600_flags; /* mask */
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ib->ptr[ib->length_dw++] = 0;
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ib->ptr[ib->length_dw++] = value; /* value */
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ib->ptr[ib->length_dw++] = upper_32_bits(value);
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ib->ptr[ib->length_dw++] = incr; /* increment size */
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ib->ptr[ib->length_dw++] = 0;
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pe += ndw * 4;
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addr += (ndw / 2) * incr;
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count -= ndw / 2;
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}
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}
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while (ib->length_dw & 0x7)
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ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
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}
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void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
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{
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struct radeon_ring *ring = &rdev->ring[ridx];
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if (vm == NULL)
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return;
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
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radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
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radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
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/* flush hdp cache */
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
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radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
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radeon_ring_write(ring, 1);
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/* bits 0-7 are the VM contexts0-7 */
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
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radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
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radeon_ring_write(ring, 1 << vm->id);
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}
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