448 строки
12 KiB
Plaintext
448 строки
12 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for K2G Industrial Communication Engine EVM
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*
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* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
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*/
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/dts-v1/;
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#include "keystone-k2g.dtsi"
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#include <dt-bindings/net/ti-dp83867.h>
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/ {
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compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone";
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model = "Texas Instruments K2G Industrial Communication EVM";
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memory@800000000 {
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device_type = "memory";
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reg = <0x00000008 0x00000000 0x00000000 0x20000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dsp_common_memory: dsp-common-memory@81f800000 {
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compatible = "shared-dma-pool";
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reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
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reusable;
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status = "okay";
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};
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};
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vmain: fixedregulator-vmain {
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compatible = "regulator-fixed";
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regulator-name = "vmain_fixed";
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regulator-min-microvolt = <24000000>;
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regulator-max-microvolt = <24000000>;
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regulator-always-on;
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};
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v5_0: fixedregulator-v5_0 {
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/* TPS54531 */
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compatible = "regulator-fixed";
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regulator-name = "v5_0_fixed";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&vmain>;
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regulator-always-on;
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};
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vdd_3v3: fixedregulator-vdd_3v3 {
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/* TLV62084 */
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compatible = "regulator-fixed";
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regulator-name = "vdd_3v3_fixed";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&v5_0>;
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regulator-always-on;
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};
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vdd_1v8: fixedregulator-vdd_1v8 {
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/* TLV62084 */
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compatible = "regulator-fixed";
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regulator-name = "vdd_1v8_fixed";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <&v5_0>;
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regulator-always-on;
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};
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vdds_ddr: fixedregulator-vdds_ddr {
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/* TLV62080 */
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compatible = "regulator-fixed";
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regulator-name = "vdds_ddr_fixed";
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regulator-min-microvolt = <1350000>;
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regulator-max-microvolt = <1350000>;
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vin-supply = <&v5_0>;
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regulator-always-on;
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};
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vref_ddr: fixedregulator-vref_ddr {
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/* LP2996A */
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compatible = "regulator-fixed";
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regulator-name = "vref_ddr_fixed";
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regulator-min-microvolt = <675000>;
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regulator-max-microvolt = <675000>;
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vin-supply = <&vdd_3v3>;
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regulator-always-on;
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};
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vtt_ddr: fixedregulator-vtt_ddr {
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/* LP2996A */
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compatible = "regulator-fixed";
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regulator-name = "vtt_ddr_fixed";
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regulator-min-microvolt = <675000>;
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regulator-max-microvolt = <675000>;
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vin-supply = <&vdd_3v3>;
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regulator-always-on;
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};
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vdd_0v9: fixedregulator-vdd_0v9 {
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/* TPS62180 */
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compatible = "regulator-fixed";
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regulator-name = "vdd_0v9_fixed";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <900000>;
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vin-supply = <&v5_0>;
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regulator-always-on;
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};
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vddb: fixedregulator-vddb {
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/* TPS22945 */
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compatible = "regulator-fixed";
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regulator-name = "vddb_fixed";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 53 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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gpio-decoder {
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compatible = "gpio-decoder";
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gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>,
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<&pca9536 2 GPIO_ACTIVE_HIGH>,
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<&pca9536 1 GPIO_ACTIVE_HIGH>,
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<&pca9536 0 GPIO_ACTIVE_HIGH>;
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linux,axis = <0>; /* ABS_X */
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decoder-max-value = <9>;
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};
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leds1 {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&user_leds>;
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led0 {
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label = "status0:red:cpu0";
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gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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linux,default-trigger = "cpu0";
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};
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led1 {
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label = "status0:green:usr";
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gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led2 {
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label = "status0:yellow:usr";
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gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led3 {
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label = "status1:red:mmc0";
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gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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linux,default-trigger = "mmc0";
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};
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led4 {
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label = "status1:green:usr";
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gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led5 {
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label = "status1:yellow:usr";
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gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led6 {
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label = "status2:red:usr";
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gpios = <&gpio0 44 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led7 {
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label = "status2:green:usr";
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gpios = <&gpio0 43 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led8 {
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label = "status2:yellow:usr";
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gpios = <&gpio0 42 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led9 {
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label = "status3:red:usr";
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gpios = <&gpio0 41 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led10 {
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label = "status3:green:usr";
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gpios = <&gpio0 101 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led11 {
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label = "status3:yellow:usr";
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gpios = <&gpio0 102 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led12 {
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label = "status4:green:heartbeat";
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gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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};
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&k2g_pinctrl {
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uart0_pins: pinmux_uart0_pins {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */
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K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
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>;
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};
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qspi_pins: pinmux_qspi_pins {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
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K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
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K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
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K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */
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K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */
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K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */
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K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */
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>;
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};
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mmc1_pins: pinmux_mmc1_pins {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x10FC) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
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K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
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K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
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K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
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K2G_CORE_IOPAD(0x110C) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */
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K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
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K2G_CORE_IOPAD(0x1114) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc1_sdcd.gpio0_69 */
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K2G_CORE_IOPAD(0x1118) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_sdwp.mmc1_sdwp */
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K2G_CORE_IOPAD(0x111C) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_pow.mmc1_pow */
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>;
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};
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i2c0_pins: pinmux_i2c0_pins {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
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K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
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>;
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};
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i2c1_pins: pinmux_i2c1_pins {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */
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K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */
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>;
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};
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user_leds: pinmux_user_leds {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x102c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad11.gpio0_11 */
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K2G_CORE_IOPAD(0x1030) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad12.gpio0_12 */
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K2G_CORE_IOPAD(0x1034) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad13.gpio0_13 */
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K2G_CORE_IOPAD(0x1038) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad14.gpio0_14 */
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K2G_CORE_IOPAD(0x103c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad15.gpio0_15 */
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K2G_CORE_IOPAD(0x1040) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_clk.gpio0_16 */
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K2G_CORE_IOPAD(0x104c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_wen.gpio0_19 */
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K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data9.gpio0_44 */
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K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data10.gpio0_43 */
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K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data11.gpio0_42 */
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K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* dss_data12.gpio0_41 */
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K2G_CORE_IOPAD(0x11b8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* spi2_scsn0.gpio0_101 */
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K2G_CORE_IOPAD(0x11bc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* spi2_scsn1.gpio0_102 */
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>;
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};
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emac_pins: pinmux_emac_pins {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */
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K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */
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K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */
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K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */
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K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */
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K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */
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K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */
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K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */
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K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */
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K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */
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K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */
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K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */
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>;
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};
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mdio_pins: pinmux_mdio_pins {
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pinctrl-single,pins = <
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K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */
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K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */
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>;
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&dsp0 {
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memory-region = <&dsp_common_memory>;
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status = "okay";
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};
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&qspi {
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pinctrl-names = "default";
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pinctrl-0 = <&qspi_pins>;
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cdns,rclk-en;
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status = "okay";
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flash0: m25p80@0 {
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compatible = "s25fl256s1", "jedec,spi-nor";
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reg = <0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <96000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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cdns,read-delay = <5>;
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cdns,tshsl-ns = <500>;
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cdns,tsd2d-ns = <500>;
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cdns,tchsh-ns = <119>;
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cdns,tslch-ns = <119>;
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partition@0 {
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label = "QSPI.u-boot";
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reg = <0x00000000 0x00100000>;
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};
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partition@1 {
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label = "QSPI.u-boot-env";
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reg = <0x00100000 0x00040000>;
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};
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partition@2 {
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label = "QSPI.skern";
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reg = <0x00140000 0x0040000>;
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};
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partition@3 {
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label = "QSPI.pmmc-firmware";
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reg = <0x00180000 0x0040000>;
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};
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partition@4 {
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label = "QSPI.kernel";
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reg = <0x001c0000 0x0800000>;
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};
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partition@5 {
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label = "QSPI.u-boot-spl-os";
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reg = <0x009c0000 0x0040000>;
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};
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partition@6 {
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label = "QSPI.file-system";
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reg = <0x00a00000 0x1600000>;
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};
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};
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};
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&mmc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins>;
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vmmc-supply = <&vdd_3v3>;
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cd-gpios = <&gpio0 69 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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status = "okay";
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eeprom@50 {
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compatible = "atmel,24c256";
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reg = <0x50>;
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};
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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status = "okay";
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clock-frequency = <400000>;
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pca9536: gpio@41 {
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compatible = "ti,pca9536";
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reg = <0x41>;
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gpio-controller;
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#gpio-cells = <2>;
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vcc-supply = <&vdd_3v3>;
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};
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};
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&qmss {
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status = "okay";
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};
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&knav_dmas {
|
|
status = "okay";
|
|
};
|
|
|
|
&netcp {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&emac_pins>;
|
|
status = "okay";
|
|
};
|
|
|
|
&mdio {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mdio_pins>;
|
|
status = "okay";
|
|
ethphy0: ethernet-phy@0 {
|
|
reg = <0>;
|
|
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
|
|
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
|
|
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
|
|
ti,min-output-impedance;
|
|
ti,dp83867-rxctrl-strap-quirk;
|
|
};
|
|
};
|
|
|
|
&gbe0 {
|
|
phy-handle = <ðphy0>;
|
|
phy-mode = "rgmii-id";
|
|
status = "okay";
|
|
};
|