311 строки
6.6 KiB
Plaintext
311 строки
6.6 KiB
Plaintext
/*
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* Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC
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*/
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/include/ "skeleton.dtsi"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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memory {
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reg = <0x00000000 0x04000000>,
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<0x08000000 0x04000000>;
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};
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L2: l2-cache {
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compatible = "arm,l210-cache";
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reg = <0x10210000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <30>;
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cache-unified;
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cache-level = <2>;
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};
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mtu0 {
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/* Nomadik system timer */
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reg = <0x101e2000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <4>;
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};
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mtu1 {
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/* Secondary timer */
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reg = <0x101e3000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <5>;
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};
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gpio0: gpio@101e4000 {
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compatible = "st,nomadik-gpio";
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reg = <0x101e4000 0x80>;
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interrupt-parent = <&vica>;
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interrupts = <6>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-bank = <0>;
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clocks = <&pclk>;
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};
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gpio1: gpio@101e5000 {
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compatible = "st,nomadik-gpio";
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reg = <0x101e5000 0x80>;
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interrupt-parent = <&vica>;
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interrupts = <7>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-bank = <1>;
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clocks = <&pclk>;
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};
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gpio2: gpio@101e6000 {
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compatible = "st,nomadik-gpio";
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reg = <0x101e6000 0x80>;
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interrupt-parent = <&vica>;
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interrupts = <8>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-bank = <2>;
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clocks = <&pclk>;
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};
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gpio3: gpio@101e7000 {
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compatible = "st,nomadik-gpio";
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reg = <0x101e7000 0x80>;
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interrupt-parent = <&vica>;
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interrupts = <9>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-bank = <3>;
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clocks = <&pclk>;
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};
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pinctrl {
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compatible = "stericsson,nmk-pinctrl-stn8815";
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};
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src: src@101e0000 {
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compatible = "stericsson,nomadik-src";
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reg = <0x101e0000 0x1000>;
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clocks {
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/*
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* Dummy clock for primecells
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*/
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pclk: pclk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <2400000>;
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};
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/*
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* The 2.4 MHz TIMCLK reference clock is active at
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* boot time, this is actually the MXTALCLK @19.2 MHz
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* divided by 8. This clock is used by the timers and
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* watchdog. See page 105 ff.
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*/
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timclk: timclk@2.4M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <2400000>;
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};
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/*
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* At boot time, PLL2 is set to generate a set of
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* fixed clocks, one of them is CLK48, the 48 MHz
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* clock, routed to the UART, MMC/SD, I2C, IrDA,
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* USB and SSP blocks.
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*/
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clk48: clk48@48M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <48000000>;
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};
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};
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};
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/* A NAND flash of 128 MiB */
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fsmc: flash@40000000 {
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compatible = "stericsson,fsmc-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x10100000 0x1000>, /* FSMC Register*/
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<0x40000000 0x2000>, /* NAND Base DATA */
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<0x41000000 0x2000>, /* NAND Base ADDR */
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<0x40800000 0x2000>; /* NAND Base CMD */
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reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
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clocks = <&pclk>;
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status = "okay";
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partition@0 {
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label = "X-Loader(NAND)";
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reg = <0x0 0x40000>;
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};
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partition@40000 {
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label = "MemInit(NAND)";
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reg = <0x40000 0x40000>;
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};
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partition@80000 {
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label = "BootLoader(NAND)";
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reg = <0x80000 0x200000>;
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};
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partition@280000 {
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label = "Kernel zImage(NAND)";
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reg = <0x280000 0x300000>;
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};
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partition@580000 {
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label = "Root Filesystem(NAND)";
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reg = <0x580000 0x1600000>;
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};
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partition@1b80000 {
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label = "User Filesystem(NAND)";
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reg = <0x1b80000 0x6480000>;
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};
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};
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external-bus@34000000 {
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compatible = "simple-bus";
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reg = <0x34000000 0x1000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x34000000 0x1000000>;
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ethernet@300 {
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compatible = "smsc,lan91c111";
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reg = <0x300 0x0fd00>;
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};
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};
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/* I2C0 connected to the STw4811 power management chip */
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i2c0 {
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compatible = "i2c-gpio";
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gpios = <&gpio1 31 0>, /* sda */
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<&gpio1 30 0>; /* scl */
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#address-cells = <1>;
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#size-cells = <0>;
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stw4811@2d {
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compatible = "st,stw4811";
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reg = <0x2d>;
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};
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};
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/* I2C1 connected to various sensors */
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i2c1 {
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compatible = "i2c-gpio";
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gpios = <&gpio1 22 0>, /* sda */
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<&gpio1 21 0>; /* scl */
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#address-cells = <1>;
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#size-cells = <0>;
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camera@2d {
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compatible = "st,camera";
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reg = <0x10>;
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};
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stw5095@1a {
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compatible = "st,stw5095";
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reg = <0x1a>;
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};
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lis3lv02dl@1d {
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compatible = "st,lis3lv02dl";
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reg = <0x1d>;
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};
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};
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/* I2C2 connected to the USB portions of the STw4811 only */
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i2c2 {
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compatible = "i2c-gpio";
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gpios = <&gpio2 10 0>, /* sda */
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<&gpio2 9 0>; /* scl */
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#address-cells = <1>;
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#size-cells = <0>;
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stw4811@2d {
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compatible = "st,stw4811-usb";
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reg = <0x2d>;
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};
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};
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amba {
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compatible = "arm,amba-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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vica: intc@0x10140000 {
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compatible = "arm,versatile-vic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x10140000 0x20>;
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};
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vicb: intc@0x10140020 {
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compatible = "arm,versatile-vic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x10140020 0x20>;
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};
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uart0: uart@101fd000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x101fd000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <12>;
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clocks = <&clk48>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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uart1: uart@101fb000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x101fb000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <17>;
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clocks = <&clk48>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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uart2: uart@101f2000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x101f2000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <28>;
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clocks = <&clk48>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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rng: rng@101b0000 {
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compatible = "arm,primecell";
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reg = <0x101b0000 0x1000>;
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clocks = <&clk48>, <&pclk>;
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clock-names = "rng", "apb_pclk";
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};
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rtc: rtc@101e8000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x101e8000 0x1000>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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interrupt-parent = <&vica>;
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interrupts = <10>;
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};
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mmcsd: sdi@101f6000 {
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compatible = "arm,pl18x", "arm,primecell";
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reg = <0x101f6000 0x1000>;
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clocks = <&clk48>, <&pclk>;
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clock-names = "mclk", "apb_pclk";
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interrupt-parent = <&vica>;
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interrupts = <22>;
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max-frequency = <48000000>;
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bus-width = <4>;
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mmc-cap-mmc-highspeed;
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mmc-cap-sd-highspeed;
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cd-gpios = <&gpio3 15 0x1>;
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cd-inverted;
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};
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};
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};
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