378 строки
9.4 KiB
C
378 строки
9.4 KiB
C
/*
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* Chip-specific setup code for the SAMA5D3 family
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*
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* Copyright (C) 2013 Atmel,
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* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/module.h>
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#include <linux/dma-mapping.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/sama5d3.h>
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#include <mach/at91_pmc.h>
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#include <mach/cpu.h>
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#include "soc.h"
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#include "generic.h"
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#include "clock.h"
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#include "sam9_smc.h"
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/* --------------------------------------------------------------------
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* Clocks
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* -------------------------------------------------------------------- */
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/*
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* The peripheral clocks.
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*/
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static struct clk pioA_clk = {
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.name = "pioA_clk",
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.pid = SAMA5D3_ID_PIOA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioB_clk = {
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.name = "pioB_clk",
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.pid = SAMA5D3_ID_PIOB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioC_clk = {
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.name = "pioC_clk",
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.pid = SAMA5D3_ID_PIOC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioD_clk = {
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.name = "pioD_clk",
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.pid = SAMA5D3_ID_PIOD,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioE_clk = {
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.name = "pioE_clk",
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.pid = SAMA5D3_ID_PIOE,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart0_clk = {
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.name = "usart0_clk",
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.pid = SAMA5D3_ID_USART0,
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.type = CLK_TYPE_PERIPHERAL,
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.div = AT91_PMC_PCR_DIV2,
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};
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static struct clk usart1_clk = {
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.name = "usart1_clk",
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.pid = SAMA5D3_ID_USART1,
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.type = CLK_TYPE_PERIPHERAL,
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.div = AT91_PMC_PCR_DIV2,
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};
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static struct clk usart2_clk = {
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.name = "usart2_clk",
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.pid = SAMA5D3_ID_USART2,
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.type = CLK_TYPE_PERIPHERAL,
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.div = AT91_PMC_PCR_DIV2,
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};
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static struct clk usart3_clk = {
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.name = "usart3_clk",
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.pid = SAMA5D3_ID_USART3,
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.type = CLK_TYPE_PERIPHERAL,
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.div = AT91_PMC_PCR_DIV2,
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};
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static struct clk uart0_clk = {
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.name = "uart0_clk",
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.pid = SAMA5D3_ID_UART0,
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.type = CLK_TYPE_PERIPHERAL,
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.div = AT91_PMC_PCR_DIV2,
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};
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static struct clk uart1_clk = {
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.name = "uart1_clk",
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.pid = SAMA5D3_ID_UART1,
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.type = CLK_TYPE_PERIPHERAL,
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.div = AT91_PMC_PCR_DIV2,
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};
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static struct clk twi0_clk = {
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.name = "twi0_clk",
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.pid = SAMA5D3_ID_TWI0,
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.type = CLK_TYPE_PERIPHERAL,
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.div = AT91_PMC_PCR_DIV2,
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};
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static struct clk twi1_clk = {
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.name = "twi1_clk",
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.pid = SAMA5D3_ID_TWI1,
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.type = CLK_TYPE_PERIPHERAL,
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.div = AT91_PMC_PCR_DIV2,
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};
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static struct clk twi2_clk = {
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.name = "twi2_clk",
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.pid = SAMA5D3_ID_TWI2,
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.type = CLK_TYPE_PERIPHERAL,
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.div = AT91_PMC_PCR_DIV2,
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};
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static struct clk mmc0_clk = {
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.name = "mci0_clk",
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.pid = SAMA5D3_ID_HSMCI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc1_clk = {
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.name = "mci1_clk",
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.pid = SAMA5D3_ID_HSMCI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc2_clk = {
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.name = "mci2_clk",
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.pid = SAMA5D3_ID_HSMCI2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi0_clk = {
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.name = "spi0_clk",
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.pid = SAMA5D3_ID_SPI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi1_clk = {
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.name = "spi1_clk",
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.pid = SAMA5D3_ID_SPI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tcb0_clk = {
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.name = "tcb0_clk",
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.pid = SAMA5D3_ID_TC0,
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.type = CLK_TYPE_PERIPHERAL,
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.div = AT91_PMC_PCR_DIV2,
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};
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static struct clk tcb1_clk = {
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.name = "tcb1_clk",
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.pid = SAMA5D3_ID_TC1,
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.type = CLK_TYPE_PERIPHERAL,
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.div = AT91_PMC_PCR_DIV2,
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};
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static struct clk adc_clk = {
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.name = "adc_clk",
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.pid = SAMA5D3_ID_ADC,
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.type = CLK_TYPE_PERIPHERAL,
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.div = AT91_PMC_PCR_DIV2,
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};
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static struct clk adc_op_clk = {
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.name = "adc_op_clk",
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.type = CLK_TYPE_PERIPHERAL,
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.rate_hz = 5000000,
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};
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static struct clk dma0_clk = {
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.name = "dma0_clk",
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.pid = SAMA5D3_ID_DMA0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk dma1_clk = {
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.name = "dma1_clk",
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.pid = SAMA5D3_ID_DMA1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk uhphs_clk = {
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.name = "uhphs",
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.pid = SAMA5D3_ID_UHPHS,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk udphs_clk = {
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.name = "udphs_clk",
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.pid = SAMA5D3_ID_UDPHS,
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.type = CLK_TYPE_PERIPHERAL,
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};
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/* gmac only for sama5d33, sama5d34, sama5d35 */
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static struct clk macb0_clk = {
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.name = "macb0_clk",
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.pid = SAMA5D3_ID_GMAC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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/* emac only for sama5d31, sama5d35 */
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static struct clk macb1_clk = {
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.name = "macb1_clk",
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.pid = SAMA5D3_ID_EMAC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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/* lcd only for sama5d31, sama5d33, sama5d34 */
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static struct clk lcdc_clk = {
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.name = "lcdc_clk",
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.pid = SAMA5D3_ID_LCDC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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/* isi only for sama5d33, sama5d35 */
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static struct clk isi_clk = {
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.name = "isi_clk",
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.pid = SAMA5D3_ID_ISI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk can0_clk = {
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.name = "can0_clk",
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.pid = SAMA5D3_ID_CAN0,
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.type = CLK_TYPE_PERIPHERAL,
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.div = AT91_PMC_PCR_DIV2,
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};
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static struct clk can1_clk = {
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.name = "can1_clk",
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.pid = SAMA5D3_ID_CAN1,
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.type = CLK_TYPE_PERIPHERAL,
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.div = AT91_PMC_PCR_DIV2,
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};
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static struct clk ssc0_clk = {
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.name = "ssc0_clk",
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.pid = SAMA5D3_ID_SSC0,
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.type = CLK_TYPE_PERIPHERAL,
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.div = AT91_PMC_PCR_DIV2,
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};
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static struct clk ssc1_clk = {
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.name = "ssc1_clk",
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.pid = SAMA5D3_ID_SSC1,
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.type = CLK_TYPE_PERIPHERAL,
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.div = AT91_PMC_PCR_DIV2,
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};
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static struct clk sha_clk = {
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.name = "sha_clk",
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.pid = SAMA5D3_ID_SHA,
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.type = CLK_TYPE_PERIPHERAL,
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.div = AT91_PMC_PCR_DIV8,
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};
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static struct clk aes_clk = {
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.name = "aes_clk",
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.pid = SAMA5D3_ID_AES,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tdes_clk = {
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.name = "tdes_clk",
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.pid = SAMA5D3_ID_TDES,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk *periph_clocks[] __initdata = {
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&pioA_clk,
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&pioB_clk,
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&pioC_clk,
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&pioD_clk,
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&pioE_clk,
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&usart0_clk,
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&usart1_clk,
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&usart2_clk,
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&usart3_clk,
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&uart0_clk,
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&uart1_clk,
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&twi0_clk,
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&twi1_clk,
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&twi2_clk,
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&mmc0_clk,
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&mmc1_clk,
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&mmc2_clk,
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&spi0_clk,
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&spi1_clk,
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&tcb0_clk,
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&tcb1_clk,
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&adc_clk,
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&adc_op_clk,
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&dma0_clk,
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&dma1_clk,
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&uhphs_clk,
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&udphs_clk,
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&macb0_clk,
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&macb1_clk,
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&lcdc_clk,
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&isi_clk,
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&can0_clk,
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&can1_clk,
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&ssc0_clk,
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&ssc1_clk,
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&sha_clk,
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&aes_clk,
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&tdes_clk,
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};
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static struct clk pck0 = {
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.name = "pck0",
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.pmc_mask = AT91_PMC_PCK0,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 0,
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};
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static struct clk pck1 = {
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.name = "pck1",
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.pmc_mask = AT91_PMC_PCK1,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 1,
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};
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static struct clk pck2 = {
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.name = "pck2",
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.pmc_mask = AT91_PMC_PCK2,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 2,
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};
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static struct clk_lookup periph_clocks_lookups[] = {
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/* lookup table for DT entries */
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CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
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CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
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CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
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CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
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CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioD_clk),
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CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioE_clk),
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CLKDEV_CON_DEV_ID("usart", "f001c000.serial", &usart0_clk),
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CLKDEV_CON_DEV_ID("usart", "f0020000.serial", &usart1_clk),
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CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart2_clk),
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CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart3_clk),
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CLKDEV_CON_DEV_ID(NULL, "f0014000.i2c", &twi0_clk),
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CLKDEV_CON_DEV_ID(NULL, "f0018000.i2c", &twi1_clk),
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CLKDEV_CON_DEV_ID(NULL, "f801c000.i2c", &twi2_clk),
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CLKDEV_CON_DEV_ID("mci_clk", "f0000000.mmc", &mmc0_clk),
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CLKDEV_CON_DEV_ID("mci_clk", "f8000000.mmc", &mmc1_clk),
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CLKDEV_CON_DEV_ID("mci_clk", "f8004000.mmc", &mmc2_clk),
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CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi0_clk),
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CLKDEV_CON_DEV_ID("spi_clk", "f8008000.spi", &spi1_clk),
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CLKDEV_CON_DEV_ID("t0_clk", "f0010000.timer", &tcb0_clk),
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CLKDEV_CON_DEV_ID("t0_clk", "f8014000.timer", &tcb1_clk),
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CLKDEV_CON_DEV_ID("tsc_clk", "f8018000.tsadcc", &adc_clk),
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CLKDEV_CON_DEV_ID("dma_clk", "ffffe600.dma-controller", &dma0_clk),
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CLKDEV_CON_DEV_ID("dma_clk", "ffffe800.dma-controller", &dma1_clk),
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CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
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CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
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CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
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CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
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CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
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CLKDEV_CON_DEV_ID("hclk", "f0028000.ethernet", &macb0_clk),
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CLKDEV_CON_DEV_ID("pclk", "f0028000.ethernet", &macb0_clk),
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CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb1_clk),
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CLKDEV_CON_DEV_ID("pclk", "f802c000.ethernet", &macb1_clk),
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CLKDEV_CON_DEV_ID("pclk", "f0008000.ssc", &ssc0_clk),
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CLKDEV_CON_DEV_ID("pclk", "f000c000.ssc", &ssc1_clk),
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CLKDEV_CON_DEV_ID("can_clk", "f000c000.can", &can0_clk),
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CLKDEV_CON_DEV_ID("can_clk", "f8010000.can", &can1_clk),
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CLKDEV_CON_DEV_ID("sha_clk", "f8034000.sha", &sha_clk),
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CLKDEV_CON_DEV_ID("aes_clk", "f8038000.aes", &aes_clk),
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CLKDEV_CON_DEV_ID("tdes_clk", "f803c000.tdes", &tdes_clk),
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};
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static void __init sama5d3_register_clocks(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
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clk_register(periph_clocks[i]);
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clkdev_add_table(periph_clocks_lookups,
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ARRAY_SIZE(periph_clocks_lookups));
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clk_register(&pck0);
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clk_register(&pck1);
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clk_register(&pck2);
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}
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/* --------------------------------------------------------------------
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* AT91SAM9x5 processor initialization
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* -------------------------------------------------------------------- */
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static void __init sama5d3_map_io(void)
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{
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at91_init_sram(0, SAMA5D3_SRAM_BASE, SAMA5D3_SRAM_SIZE);
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}
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AT91_SOC_START(sama5d3)
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.map_io = sama5d3_map_io,
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.register_clocks = sama5d3_register_clocks,
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AT91_SOC_END
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