1043 строки
27 KiB
C
1043 строки
27 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2017 Tony Lindgren <tony@atomide.com>
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*
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* Rewritten for Linux IIO framework with some code based on
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* earlier driver found in the Motorola Linux kernel:
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*
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* Copyright (C) 2009-2010 Motorola, Inc.
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/driver.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/kfifo_buf.h>
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#include <linux/mfd/motorola-cpcap.h>
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/* Register CPCAP_REG_ADCC1 bits */
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#define CPCAP_BIT_ADEN_AUTO_CLR BIT(15) /* Currently unused */
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#define CPCAP_BIT_CAL_MODE BIT(14) /* Set with BIT_RAND0 */
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#define CPCAP_BIT_ADC_CLK_SEL1 BIT(13) /* Currently unused */
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#define CPCAP_BIT_ADC_CLK_SEL0 BIT(12) /* Currently unused */
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#define CPCAP_BIT_ATOX BIT(11)
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#define CPCAP_BIT_ATO3 BIT(10)
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#define CPCAP_BIT_ATO2 BIT(9)
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#define CPCAP_BIT_ATO1 BIT(8)
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#define CPCAP_BIT_ATO0 BIT(7)
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#define CPCAP_BIT_ADA2 BIT(6)
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#define CPCAP_BIT_ADA1 BIT(5)
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#define CPCAP_BIT_ADA0 BIT(4)
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#define CPCAP_BIT_AD_SEL1 BIT(3) /* Set for bank1 */
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#define CPCAP_BIT_RAND1 BIT(2) /* Set for channel 16 & 17 */
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#define CPCAP_BIT_RAND0 BIT(1) /* Set with CAL_MODE */
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#define CPCAP_BIT_ADEN BIT(0) /* Currently unused */
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#define CPCAP_REG_ADCC1_DEFAULTS (CPCAP_BIT_ADEN_AUTO_CLR | \
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CPCAP_BIT_ADC_CLK_SEL0 | \
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CPCAP_BIT_RAND1)
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/* Register CPCAP_REG_ADCC2 bits */
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#define CPCAP_BIT_CAL_FACTOR_ENABLE BIT(15) /* Currently unused */
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#define CPCAP_BIT_BATDETB_EN BIT(14) /* Currently unused */
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#define CPCAP_BIT_ADTRIG_ONESHOT BIT(13) /* Set for !TIMING_IMM */
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#define CPCAP_BIT_ASC BIT(12) /* Set for TIMING_IMM */
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#define CPCAP_BIT_ATOX_PS_FACTOR BIT(11)
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#define CPCAP_BIT_ADC_PS_FACTOR1 BIT(10)
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#define CPCAP_BIT_ADC_PS_FACTOR0 BIT(9)
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#define CPCAP_BIT_AD4_SELECT BIT(8) /* Currently unused */
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#define CPCAP_BIT_ADC_BUSY BIT(7) /* Currently unused */
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#define CPCAP_BIT_THERMBIAS_EN BIT(6) /* Bias for AD0_BATTDETB */
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#define CPCAP_BIT_ADTRIG_DIS BIT(5) /* Disable interrupt */
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#define CPCAP_BIT_LIADC BIT(4) /* Currently unused */
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#define CPCAP_BIT_TS_REFEN BIT(3) /* Currently unused */
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#define CPCAP_BIT_TS_M2 BIT(2) /* Currently unused */
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#define CPCAP_BIT_TS_M1 BIT(1) /* Currently unused */
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#define CPCAP_BIT_TS_M0 BIT(0) /* Currently unused */
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#define CPCAP_REG_ADCC2_DEFAULTS (CPCAP_BIT_AD4_SELECT | \
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CPCAP_BIT_ADTRIG_DIS | \
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CPCAP_BIT_LIADC | \
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CPCAP_BIT_TS_M2 | \
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CPCAP_BIT_TS_M1)
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#define CPCAP_MAX_TEMP_LVL 27
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#define CPCAP_FOUR_POINT_TWO_ADC 801
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#define ST_ADC_CAL_CHRGI_HIGH_THRESHOLD 530
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#define ST_ADC_CAL_CHRGI_LOW_THRESHOLD 494
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#define ST_ADC_CAL_BATTI_HIGH_THRESHOLD 530
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#define ST_ADC_CAL_BATTI_LOW_THRESHOLD 494
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#define ST_ADC_CALIBRATE_DIFF_THRESHOLD 3
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#define CPCAP_ADC_MAX_RETRIES 5 /* Calibration */
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/**
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* struct cpcap_adc_ato - timing settings for cpcap adc
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*
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* Unfortunately no cpcap documentation available, please document when
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* using these.
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*/
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struct cpcap_adc_ato {
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unsigned short ato_in;
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unsigned short atox_in;
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unsigned short adc_ps_factor_in;
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unsigned short atox_ps_factor_in;
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unsigned short ato_out;
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unsigned short atox_out;
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unsigned short adc_ps_factor_out;
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unsigned short atox_ps_factor_out;
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};
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/**
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* struct cpcap-adc - cpcap adc device driver data
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* @reg: cpcap regmap
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* @dev: struct device
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* @vendor: cpcap vendor
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* @irq: interrupt
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* @lock: mutex
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* @ato: request timings
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* @wq_data_avail: work queue
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* @done: work done
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*/
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struct cpcap_adc {
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struct regmap *reg;
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struct device *dev;
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u16 vendor;
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int irq;
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struct mutex lock; /* ADC register access lock */
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const struct cpcap_adc_ato *ato;
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wait_queue_head_t wq_data_avail;
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bool done;
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};
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/**
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* enum cpcap_adc_channel - cpcap adc channels
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*/
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enum cpcap_adc_channel {
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/* Bank0 channels */
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CPCAP_ADC_AD0, /* Battery temperature */
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CPCAP_ADC_BATTP, /* Battery voltage */
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CPCAP_ADC_VBUS, /* USB VBUS voltage */
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CPCAP_ADC_AD3, /* Die temperature when charging */
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CPCAP_ADC_BPLUS_AD4, /* Another battery or system voltage */
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CPCAP_ADC_CHG_ISENSE, /* Calibrated charge current */
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CPCAP_ADC_BATTI, /* Calibrated system current */
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CPCAP_ADC_USB_ID, /* USB OTG ID, unused on droid 4? */
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/* Bank1 channels */
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CPCAP_ADC_AD8, /* Seems unused */
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CPCAP_ADC_AD9, /* Seems unused */
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CPCAP_ADC_LICELL, /* Maybe system voltage? Always 3V */
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CPCAP_ADC_HV_BATTP, /* Another battery detection? */
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CPCAP_ADC_TSX1_AD12, /* Seems unused, for touchscreen? */
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CPCAP_ADC_TSX2_AD13, /* Seems unused, for touchscreen? */
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CPCAP_ADC_TSY1_AD14, /* Seems unused, for touchscreen? */
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CPCAP_ADC_TSY2_AD15, /* Seems unused, for touchscreen? */
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/* Remuxed channels using bank0 entries */
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CPCAP_ADC_BATTP_PI16, /* Alternative mux mode for BATTP */
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CPCAP_ADC_BATTI_PI17, /* Alternative mux mode for BATTI */
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CPCAP_ADC_CHANNEL_NUM,
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};
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/**
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* enum cpcap_adc_timing - cpcap adc timing options
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*
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* CPCAP_ADC_TIMING_IMM seems to be immediate with no timings.
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* Please document when using.
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*/
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enum cpcap_adc_timing {
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CPCAP_ADC_TIMING_IMM,
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CPCAP_ADC_TIMING_IN,
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CPCAP_ADC_TIMING_OUT,
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};
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/**
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* struct cpcap_adc_phasing_tbl - cpcap phasing table
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* @offset: offset in the phasing table
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* @multiplier: multiplier in the phasing table
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* @divider: divider in the phasing table
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* @min: minimum value
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* @max: maximum value
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*/
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struct cpcap_adc_phasing_tbl {
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short offset;
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unsigned short multiplier;
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unsigned short divider;
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short min;
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short max;
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};
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/**
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* struct cpcap_adc_conversion_tbl - cpcap conversion table
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* @conv_type: conversion type
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* @align_offset: align offset
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* @conv_offset: conversion offset
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* @cal_offset: calibration offset
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* @multiplier: conversion multiplier
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* @divider: conversion divider
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*/
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struct cpcap_adc_conversion_tbl {
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enum iio_chan_info_enum conv_type;
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int align_offset;
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int conv_offset;
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int cal_offset;
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int multiplier;
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int divider;
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};
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/**
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* struct cpcap_adc_request - cpcap adc request
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* @channel: request channel
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* @phase_tbl: channel phasing table
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* @conv_tbl: channel conversion table
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* @bank_index: channel index within the bank
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* @timing: timing settings
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* @result: result
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*/
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struct cpcap_adc_request {
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int channel;
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const struct cpcap_adc_phasing_tbl *phase_tbl;
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const struct cpcap_adc_conversion_tbl *conv_tbl;
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int bank_index;
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enum cpcap_adc_timing timing;
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int result;
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};
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/* Phasing table for channels. Note that channels 16 & 17 use BATTP and BATTI */
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static const struct cpcap_adc_phasing_tbl bank_phasing[] = {
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/* Bank0 */
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[CPCAP_ADC_AD0] = {0, 0x80, 0x80, 0, 1023},
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[CPCAP_ADC_BATTP] = {0, 0x80, 0x80, 0, 1023},
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[CPCAP_ADC_VBUS] = {0, 0x80, 0x80, 0, 1023},
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[CPCAP_ADC_AD3] = {0, 0x80, 0x80, 0, 1023},
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[CPCAP_ADC_BPLUS_AD4] = {0, 0x80, 0x80, 0, 1023},
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[CPCAP_ADC_CHG_ISENSE] = {0, 0x80, 0x80, -512, 511},
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[CPCAP_ADC_BATTI] = {0, 0x80, 0x80, -512, 511},
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[CPCAP_ADC_USB_ID] = {0, 0x80, 0x80, 0, 1023},
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/* Bank1 */
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[CPCAP_ADC_AD8] = {0, 0x80, 0x80, 0, 1023},
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[CPCAP_ADC_AD9] = {0, 0x80, 0x80, 0, 1023},
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[CPCAP_ADC_LICELL] = {0, 0x80, 0x80, 0, 1023},
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[CPCAP_ADC_HV_BATTP] = {0, 0x80, 0x80, 0, 1023},
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[CPCAP_ADC_TSX1_AD12] = {0, 0x80, 0x80, 0, 1023},
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[CPCAP_ADC_TSX2_AD13] = {0, 0x80, 0x80, 0, 1023},
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[CPCAP_ADC_TSY1_AD14] = {0, 0x80, 0x80, 0, 1023},
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[CPCAP_ADC_TSY2_AD15] = {0, 0x80, 0x80, 0, 1023},
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};
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/*
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* Conversion table for channels. Updated during init based on calibration.
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* Here too channels 16 & 17 use BATTP and BATTI.
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*/
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static struct cpcap_adc_conversion_tbl bank_conversion[] = {
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/* Bank0 */
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[CPCAP_ADC_AD0] = {
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IIO_CHAN_INFO_PROCESSED, 0, 0, 0, 1, 1,
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},
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[CPCAP_ADC_BATTP] = {
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IIO_CHAN_INFO_PROCESSED, 0, 2400, 0, 2300, 1023,
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},
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[CPCAP_ADC_VBUS] = {
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IIO_CHAN_INFO_PROCESSED, 0, 0, 0, 10000, 1023,
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},
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[CPCAP_ADC_AD3] = {
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IIO_CHAN_INFO_PROCESSED, 0, 0, 0, 1, 1,
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},
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[CPCAP_ADC_BPLUS_AD4] = {
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IIO_CHAN_INFO_PROCESSED, 0, 2400, 0, 2300, 1023,
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},
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[CPCAP_ADC_CHG_ISENSE] = {
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IIO_CHAN_INFO_PROCESSED, -512, 2, 0, 5000, 1023,
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},
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[CPCAP_ADC_BATTI] = {
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IIO_CHAN_INFO_PROCESSED, -512, 2, 0, 5000, 1023,
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},
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[CPCAP_ADC_USB_ID] = {
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IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
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},
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/* Bank1 */
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[CPCAP_ADC_AD8] = {
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IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
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},
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[CPCAP_ADC_AD9] = {
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IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
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},
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[CPCAP_ADC_LICELL] = {
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IIO_CHAN_INFO_PROCESSED, 0, 0, 0, 3400, 1023,
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},
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[CPCAP_ADC_HV_BATTP] = {
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IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
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},
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[CPCAP_ADC_TSX1_AD12] = {
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IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
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},
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[CPCAP_ADC_TSX2_AD13] = {
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IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
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},
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[CPCAP_ADC_TSY1_AD14] = {
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IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
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},
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[CPCAP_ADC_TSY2_AD15] = {
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IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
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},
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};
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/*
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* Temperature lookup table of register values to milliCelcius.
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* REVISIT: Check the duplicate 0x3ff entry in a freezer
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*/
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static const int temp_map[CPCAP_MAX_TEMP_LVL][2] = {
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{ 0x03ff, -40000 },
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{ 0x03ff, -35000 },
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{ 0x03ef, -30000 },
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{ 0x03b2, -25000 },
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{ 0x036c, -20000 },
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{ 0x0320, -15000 },
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{ 0x02d0, -10000 },
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{ 0x027f, -5000 },
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{ 0x022f, 0 },
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{ 0x01e4, 5000 },
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{ 0x019f, 10000 },
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{ 0x0161, 15000 },
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{ 0x012b, 20000 },
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{ 0x00fc, 25000 },
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{ 0x00d4, 30000 },
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{ 0x00b2, 35000 },
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{ 0x0095, 40000 },
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{ 0x007d, 45000 },
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{ 0x0069, 50000 },
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{ 0x0059, 55000 },
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{ 0x004b, 60000 },
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{ 0x003f, 65000 },
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{ 0x0036, 70000 },
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{ 0x002e, 75000 },
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{ 0x0027, 80000 },
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{ 0x0022, 85000 },
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{ 0x001d, 90000 },
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};
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#define CPCAP_CHAN(_type, _index, _address, _datasheet_name) { \
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.type = (_type), \
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.address = (_address), \
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.indexed = 1, \
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.channel = (_index), \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
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BIT(IIO_CHAN_INFO_PROCESSED), \
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.scan_index = (_index), \
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.scan_type = { \
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.sign = 'u', \
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.realbits = 10, \
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.storagebits = 16, \
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.endianness = IIO_CPU, \
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}, \
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.datasheet_name = (_datasheet_name), \
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}
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/*
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* The datasheet names are from Motorola mapphone Linux kernel except
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* for the last two which might be uncalibrated charge voltage and
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* current.
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*/
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static const struct iio_chan_spec cpcap_adc_channels[] = {
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/* Bank0 */
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CPCAP_CHAN(IIO_TEMP, 0, CPCAP_REG_ADCD0, "battdetb"),
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CPCAP_CHAN(IIO_VOLTAGE, 1, CPCAP_REG_ADCD1, "battp"),
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CPCAP_CHAN(IIO_VOLTAGE, 2, CPCAP_REG_ADCD2, "vbus"),
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CPCAP_CHAN(IIO_TEMP, 3, CPCAP_REG_ADCD3, "ad3"),
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CPCAP_CHAN(IIO_VOLTAGE, 4, CPCAP_REG_ADCD4, "ad4"),
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CPCAP_CHAN(IIO_CURRENT, 5, CPCAP_REG_ADCD5, "chg_isense"),
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CPCAP_CHAN(IIO_CURRENT, 6, CPCAP_REG_ADCD6, "batti"),
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CPCAP_CHAN(IIO_VOLTAGE, 7, CPCAP_REG_ADCD7, "usb_id"),
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/* Bank1 */
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CPCAP_CHAN(IIO_CURRENT, 8, CPCAP_REG_ADCD0, "ad8"),
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CPCAP_CHAN(IIO_VOLTAGE, 9, CPCAP_REG_ADCD1, "ad9"),
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CPCAP_CHAN(IIO_VOLTAGE, 10, CPCAP_REG_ADCD2, "licell"),
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CPCAP_CHAN(IIO_VOLTAGE, 11, CPCAP_REG_ADCD3, "hv_battp"),
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CPCAP_CHAN(IIO_VOLTAGE, 12, CPCAP_REG_ADCD4, "tsx1_ad12"),
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CPCAP_CHAN(IIO_VOLTAGE, 13, CPCAP_REG_ADCD5, "tsx2_ad13"),
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CPCAP_CHAN(IIO_VOLTAGE, 14, CPCAP_REG_ADCD6, "tsy1_ad14"),
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CPCAP_CHAN(IIO_VOLTAGE, 15, CPCAP_REG_ADCD7, "tsy2_ad15"),
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/* There are two registers with multiplexed functionality */
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CPCAP_CHAN(IIO_VOLTAGE, 16, CPCAP_REG_ADCD0, "chg_vsense"),
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CPCAP_CHAN(IIO_CURRENT, 17, CPCAP_REG_ADCD1, "batti2"),
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};
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static irqreturn_t cpcap_adc_irq_thread(int irq, void *data)
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{
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struct iio_dev *indio_dev = data;
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struct cpcap_adc *ddata = iio_priv(indio_dev);
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int error;
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error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
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CPCAP_BIT_ADTRIG_DIS,
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CPCAP_BIT_ADTRIG_DIS);
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if (error)
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return IRQ_NONE;
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ddata->done = true;
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wake_up_interruptible(&ddata->wq_data_avail);
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return IRQ_HANDLED;
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}
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/* ADC calibration functions */
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static void cpcap_adc_setup_calibrate(struct cpcap_adc *ddata,
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enum cpcap_adc_channel chan)
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{
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unsigned int value = 0;
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unsigned long timeout = jiffies + msecs_to_jiffies(3000);
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int error;
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if ((chan != CPCAP_ADC_CHG_ISENSE) &&
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(chan != CPCAP_ADC_BATTI))
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return;
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value |= CPCAP_BIT_CAL_MODE | CPCAP_BIT_RAND0;
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value |= ((chan << 4) &
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(CPCAP_BIT_ADA2 | CPCAP_BIT_ADA1 | CPCAP_BIT_ADA0));
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error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1,
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CPCAP_BIT_CAL_MODE | CPCAP_BIT_ATOX |
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CPCAP_BIT_ATO3 | CPCAP_BIT_ATO2 |
|
|
CPCAP_BIT_ATO1 | CPCAP_BIT_ATO0 |
|
|
CPCAP_BIT_ADA2 | CPCAP_BIT_ADA1 |
|
|
CPCAP_BIT_ADA0 | CPCAP_BIT_AD_SEL1 |
|
|
CPCAP_BIT_RAND1 | CPCAP_BIT_RAND0,
|
|
value);
|
|
if (error)
|
|
return;
|
|
|
|
error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
|
|
CPCAP_BIT_ATOX_PS_FACTOR |
|
|
CPCAP_BIT_ADC_PS_FACTOR1 |
|
|
CPCAP_BIT_ADC_PS_FACTOR0,
|
|
0);
|
|
if (error)
|
|
return;
|
|
|
|
error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
|
|
CPCAP_BIT_ADTRIG_DIS,
|
|
CPCAP_BIT_ADTRIG_DIS);
|
|
if (error)
|
|
return;
|
|
|
|
error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
|
|
CPCAP_BIT_ASC,
|
|
CPCAP_BIT_ASC);
|
|
if (error)
|
|
return;
|
|
|
|
do {
|
|
schedule_timeout_uninterruptible(1);
|
|
error = regmap_read(ddata->reg, CPCAP_REG_ADCC2, &value);
|
|
if (error)
|
|
return;
|
|
} while ((value & CPCAP_BIT_ASC) && time_before(jiffies, timeout));
|
|
|
|
if (value & CPCAP_BIT_ASC)
|
|
dev_err(ddata->dev,
|
|
"Timeout waiting for calibration to complete\n");
|
|
|
|
error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1,
|
|
CPCAP_BIT_CAL_MODE, 0);
|
|
if (error)
|
|
return;
|
|
}
|
|
|
|
static int cpcap_adc_calibrate_one(struct cpcap_adc *ddata,
|
|
int channel,
|
|
u16 calibration_register,
|
|
int lower_threshold,
|
|
int upper_threshold)
|
|
{
|
|
unsigned int calibration_data[2];
|
|
unsigned short cal_data_diff;
|
|
int i, error;
|
|
|
|
for (i = 0; i < CPCAP_ADC_MAX_RETRIES; i++) {
|
|
calibration_data[0] = 0;
|
|
calibration_data[1] = 0;
|
|
cal_data_diff = 0;
|
|
cpcap_adc_setup_calibrate(ddata, channel);
|
|
error = regmap_read(ddata->reg, calibration_register,
|
|
&calibration_data[0]);
|
|
if (error)
|
|
return error;
|
|
cpcap_adc_setup_calibrate(ddata, channel);
|
|
error = regmap_read(ddata->reg, calibration_register,
|
|
&calibration_data[1]);
|
|
if (error)
|
|
return error;
|
|
|
|
if (calibration_data[0] > calibration_data[1])
|
|
cal_data_diff =
|
|
calibration_data[0] - calibration_data[1];
|
|
else
|
|
cal_data_diff =
|
|
calibration_data[1] - calibration_data[0];
|
|
|
|
if (((calibration_data[1] >= lower_threshold) &&
|
|
(calibration_data[1] <= upper_threshold) &&
|
|
(cal_data_diff <= ST_ADC_CALIBRATE_DIFF_THRESHOLD)) ||
|
|
(ddata->vendor == CPCAP_VENDOR_TI)) {
|
|
bank_conversion[channel].cal_offset =
|
|
((short)calibration_data[1] * -1) + 512;
|
|
dev_dbg(ddata->dev, "ch%i calibration complete: %i\n",
|
|
channel, bank_conversion[channel].cal_offset);
|
|
break;
|
|
}
|
|
usleep_range(5000, 10000);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cpcap_adc_calibrate(struct cpcap_adc *ddata)
|
|
{
|
|
int error;
|
|
|
|
error = cpcap_adc_calibrate_one(ddata, CPCAP_ADC_CHG_ISENSE,
|
|
CPCAP_REG_ADCAL1,
|
|
ST_ADC_CAL_CHRGI_LOW_THRESHOLD,
|
|
ST_ADC_CAL_CHRGI_HIGH_THRESHOLD);
|
|
if (error)
|
|
return error;
|
|
|
|
error = cpcap_adc_calibrate_one(ddata, CPCAP_ADC_BATTI,
|
|
CPCAP_REG_ADCAL2,
|
|
ST_ADC_CAL_BATTI_LOW_THRESHOLD,
|
|
ST_ADC_CAL_BATTI_HIGH_THRESHOLD);
|
|
if (error)
|
|
return error;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* ADC setup, read and scale functions */
|
|
static void cpcap_adc_setup_bank(struct cpcap_adc *ddata,
|
|
struct cpcap_adc_request *req)
|
|
{
|
|
const struct cpcap_adc_ato *ato = ddata->ato;
|
|
unsigned short value1 = 0;
|
|
unsigned short value2 = 0;
|
|
int error;
|
|
|
|
if (!ato)
|
|
return;
|
|
|
|
switch (req->channel) {
|
|
case CPCAP_ADC_AD0:
|
|
value2 |= CPCAP_BIT_THERMBIAS_EN;
|
|
error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
|
|
CPCAP_BIT_THERMBIAS_EN,
|
|
value2);
|
|
if (error)
|
|
return;
|
|
usleep_range(800, 1000);
|
|
break;
|
|
case CPCAP_ADC_AD8 ... CPCAP_ADC_TSY2_AD15:
|
|
value1 |= CPCAP_BIT_AD_SEL1;
|
|
break;
|
|
case CPCAP_ADC_BATTP_PI16 ... CPCAP_ADC_BATTI_PI17:
|
|
value1 |= CPCAP_BIT_RAND1;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
switch (req->timing) {
|
|
case CPCAP_ADC_TIMING_IN:
|
|
value1 |= ato->ato_in;
|
|
value1 |= ato->atox_in;
|
|
value2 |= ato->adc_ps_factor_in;
|
|
value2 |= ato->atox_ps_factor_in;
|
|
break;
|
|
case CPCAP_ADC_TIMING_OUT:
|
|
value1 |= ato->ato_out;
|
|
value1 |= ato->atox_out;
|
|
value2 |= ato->adc_ps_factor_out;
|
|
value2 |= ato->atox_ps_factor_out;
|
|
break;
|
|
|
|
case CPCAP_ADC_TIMING_IMM:
|
|
default:
|
|
break;
|
|
}
|
|
|
|
error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1,
|
|
CPCAP_BIT_CAL_MODE | CPCAP_BIT_ATOX |
|
|
CPCAP_BIT_ATO3 | CPCAP_BIT_ATO2 |
|
|
CPCAP_BIT_ATO1 | CPCAP_BIT_ATO0 |
|
|
CPCAP_BIT_ADA2 | CPCAP_BIT_ADA1 |
|
|
CPCAP_BIT_ADA0 | CPCAP_BIT_AD_SEL1 |
|
|
CPCAP_BIT_RAND1 | CPCAP_BIT_RAND0,
|
|
value1);
|
|
if (error)
|
|
return;
|
|
|
|
error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
|
|
CPCAP_BIT_ATOX_PS_FACTOR |
|
|
CPCAP_BIT_ADC_PS_FACTOR1 |
|
|
CPCAP_BIT_ADC_PS_FACTOR0 |
|
|
CPCAP_BIT_THERMBIAS_EN,
|
|
value2);
|
|
if (error)
|
|
return;
|
|
|
|
if (req->timing == CPCAP_ADC_TIMING_IMM) {
|
|
error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
|
|
CPCAP_BIT_ADTRIG_DIS,
|
|
CPCAP_BIT_ADTRIG_DIS);
|
|
if (error)
|
|
return;
|
|
|
|
error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
|
|
CPCAP_BIT_ASC,
|
|
CPCAP_BIT_ASC);
|
|
if (error)
|
|
return;
|
|
} else {
|
|
error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
|
|
CPCAP_BIT_ADTRIG_ONESHOT,
|
|
CPCAP_BIT_ADTRIG_ONESHOT);
|
|
if (error)
|
|
return;
|
|
|
|
error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
|
|
CPCAP_BIT_ADTRIG_DIS, 0);
|
|
if (error)
|
|
return;
|
|
}
|
|
}
|
|
|
|
static int cpcap_adc_start_bank(struct cpcap_adc *ddata,
|
|
struct cpcap_adc_request *req)
|
|
{
|
|
int i, error;
|
|
|
|
req->timing = CPCAP_ADC_TIMING_IMM;
|
|
ddata->done = false;
|
|
|
|
for (i = 0; i < CPCAP_ADC_MAX_RETRIES; i++) {
|
|
cpcap_adc_setup_bank(ddata, req);
|
|
error = wait_event_interruptible_timeout(ddata->wq_data_avail,
|
|
ddata->done,
|
|
msecs_to_jiffies(50));
|
|
if (error > 0)
|
|
return 0;
|
|
|
|
if (error == 0) {
|
|
error = -ETIMEDOUT;
|
|
continue;
|
|
}
|
|
|
|
if (error < 0)
|
|
return error;
|
|
}
|
|
|
|
return error;
|
|
}
|
|
|
|
static int cpcap_adc_stop_bank(struct cpcap_adc *ddata)
|
|
{
|
|
int error;
|
|
|
|
error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1,
|
|
0xffff,
|
|
CPCAP_REG_ADCC1_DEFAULTS);
|
|
if (error)
|
|
return error;
|
|
|
|
return regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
|
|
0xffff,
|
|
CPCAP_REG_ADCC2_DEFAULTS);
|
|
}
|
|
|
|
static void cpcap_adc_phase(struct cpcap_adc_request *req)
|
|
{
|
|
const struct cpcap_adc_conversion_tbl *conv_tbl = req->conv_tbl;
|
|
const struct cpcap_adc_phasing_tbl *phase_tbl = req->phase_tbl;
|
|
int index = req->channel;
|
|
|
|
/* Remuxed channels 16 and 17 use BATTP and BATTI entries */
|
|
switch (req->channel) {
|
|
case CPCAP_ADC_BATTP:
|
|
case CPCAP_ADC_BATTP_PI16:
|
|
index = req->bank_index;
|
|
req->result -= phase_tbl[index].offset;
|
|
req->result -= CPCAP_FOUR_POINT_TWO_ADC;
|
|
req->result *= phase_tbl[index].multiplier;
|
|
if (phase_tbl[index].divider == 0)
|
|
return;
|
|
req->result /= phase_tbl[index].divider;
|
|
req->result += CPCAP_FOUR_POINT_TWO_ADC;
|
|
break;
|
|
case CPCAP_ADC_BATTI_PI17:
|
|
index = req->bank_index;
|
|
/* fallthrough */
|
|
default:
|
|
req->result += conv_tbl[index].cal_offset;
|
|
req->result += conv_tbl[index].align_offset;
|
|
req->result *= phase_tbl[index].multiplier;
|
|
if (phase_tbl[index].divider == 0)
|
|
return;
|
|
req->result /= phase_tbl[index].divider;
|
|
req->result += phase_tbl[index].offset;
|
|
break;
|
|
}
|
|
|
|
if (req->result < phase_tbl[index].min)
|
|
req->result = phase_tbl[index].min;
|
|
else if (req->result > phase_tbl[index].max)
|
|
req->result = phase_tbl[index].max;
|
|
}
|
|
|
|
/* Looks up temperatures in a table and calculates averages if needed */
|
|
static int cpcap_adc_table_to_millicelcius(unsigned short value)
|
|
{
|
|
int i, result = 0, alpha;
|
|
|
|
if (value <= temp_map[CPCAP_MAX_TEMP_LVL - 1][0])
|
|
return temp_map[CPCAP_MAX_TEMP_LVL - 1][1];
|
|
|
|
if (value >= temp_map[0][0])
|
|
return temp_map[0][1];
|
|
|
|
for (i = 0; i < CPCAP_MAX_TEMP_LVL - 1; i++) {
|
|
if ((value <= temp_map[i][0]) &&
|
|
(value >= temp_map[i + 1][0])) {
|
|
if (value == temp_map[i][0]) {
|
|
result = temp_map[i][1];
|
|
} else if (value == temp_map[i + 1][0]) {
|
|
result = temp_map[i + 1][1];
|
|
} else {
|
|
alpha = ((value - temp_map[i][0]) * 1000) /
|
|
(temp_map[i + 1][0] - temp_map[i][0]);
|
|
|
|
result = temp_map[i][1] +
|
|
((alpha * (temp_map[i + 1][1] -
|
|
temp_map[i][1])) / 1000);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
static void cpcap_adc_convert(struct cpcap_adc_request *req)
|
|
{
|
|
const struct cpcap_adc_conversion_tbl *conv_tbl = req->conv_tbl;
|
|
int index = req->channel;
|
|
|
|
/* Remuxed channels 16 and 17 use BATTP and BATTI entries */
|
|
switch (req->channel) {
|
|
case CPCAP_ADC_BATTP_PI16:
|
|
index = CPCAP_ADC_BATTP;
|
|
break;
|
|
case CPCAP_ADC_BATTI_PI17:
|
|
index = CPCAP_ADC_BATTI;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* No conversion for raw channels */
|
|
if (conv_tbl[index].conv_type == IIO_CHAN_INFO_RAW)
|
|
return;
|
|
|
|
/* Temperatures use a lookup table instead of conversion table */
|
|
if ((req->channel == CPCAP_ADC_AD0) ||
|
|
(req->channel == CPCAP_ADC_AD3)) {
|
|
req->result =
|
|
cpcap_adc_table_to_millicelcius(req->result);
|
|
|
|
return;
|
|
}
|
|
|
|
/* All processed channels use a conversion table */
|
|
req->result *= conv_tbl[index].multiplier;
|
|
if (conv_tbl[index].divider == 0)
|
|
return;
|
|
req->result /= conv_tbl[index].divider;
|
|
req->result += conv_tbl[index].conv_offset;
|
|
}
|
|
|
|
/*
|
|
* REVISIT: Check if timed sampling can use multiple channels at the
|
|
* same time. If not, replace channel_mask with just channel.
|
|
*/
|
|
static int cpcap_adc_read_bank_scaled(struct cpcap_adc *ddata,
|
|
struct cpcap_adc_request *req)
|
|
{
|
|
int calibration_data, error, addr;
|
|
|
|
if (ddata->vendor == CPCAP_VENDOR_TI) {
|
|
error = regmap_read(ddata->reg, CPCAP_REG_ADCAL1,
|
|
&calibration_data);
|
|
if (error)
|
|
return error;
|
|
bank_conversion[CPCAP_ADC_CHG_ISENSE].cal_offset =
|
|
((short)calibration_data * -1) + 512;
|
|
|
|
error = regmap_read(ddata->reg, CPCAP_REG_ADCAL2,
|
|
&calibration_data);
|
|
if (error)
|
|
return error;
|
|
bank_conversion[CPCAP_ADC_BATTI].cal_offset =
|
|
((short)calibration_data * -1) + 512;
|
|
}
|
|
|
|
addr = CPCAP_REG_ADCD0 + req->bank_index * 4;
|
|
|
|
error = regmap_read(ddata->reg, addr, &req->result);
|
|
if (error)
|
|
return error;
|
|
|
|
req->result &= 0x3ff;
|
|
cpcap_adc_phase(req);
|
|
cpcap_adc_convert(req);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cpcap_adc_init_request(struct cpcap_adc_request *req,
|
|
int channel)
|
|
{
|
|
req->channel = channel;
|
|
req->phase_tbl = bank_phasing;
|
|
req->conv_tbl = bank_conversion;
|
|
|
|
switch (channel) {
|
|
case CPCAP_ADC_AD0 ... CPCAP_ADC_USB_ID:
|
|
req->bank_index = channel;
|
|
break;
|
|
case CPCAP_ADC_AD8 ... CPCAP_ADC_TSY2_AD15:
|
|
req->bank_index = channel - 8;
|
|
break;
|
|
case CPCAP_ADC_BATTP_PI16:
|
|
req->bank_index = CPCAP_ADC_BATTP;
|
|
break;
|
|
case CPCAP_ADC_BATTI_PI17:
|
|
req->bank_index = CPCAP_ADC_BATTI;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cpcap_adc_read_st_die_temp(struct cpcap_adc *ddata,
|
|
int addr, int *val)
|
|
{
|
|
int error;
|
|
|
|
error = regmap_read(ddata->reg, addr, val);
|
|
if (error)
|
|
return error;
|
|
|
|
*val -= 282;
|
|
*val *= 114;
|
|
*val += 25000;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cpcap_adc_read(struct iio_dev *indio_dev,
|
|
struct iio_chan_spec const *chan,
|
|
int *val, int *val2, long mask)
|
|
{
|
|
struct cpcap_adc *ddata = iio_priv(indio_dev);
|
|
struct cpcap_adc_request req;
|
|
int error;
|
|
|
|
error = cpcap_adc_init_request(&req, chan->channel);
|
|
if (error)
|
|
return error;
|
|
|
|
switch (mask) {
|
|
case IIO_CHAN_INFO_RAW:
|
|
mutex_lock(&ddata->lock);
|
|
error = cpcap_adc_start_bank(ddata, &req);
|
|
if (error)
|
|
goto err_unlock;
|
|
error = regmap_read(ddata->reg, chan->address, val);
|
|
if (error)
|
|
goto err_unlock;
|
|
error = cpcap_adc_stop_bank(ddata);
|
|
if (error)
|
|
goto err_unlock;
|
|
mutex_unlock(&ddata->lock);
|
|
break;
|
|
case IIO_CHAN_INFO_PROCESSED:
|
|
mutex_lock(&ddata->lock);
|
|
error = cpcap_adc_start_bank(ddata, &req);
|
|
if (error)
|
|
goto err_unlock;
|
|
if ((ddata->vendor == CPCAP_VENDOR_ST) &&
|
|
(chan->channel == CPCAP_ADC_AD3)) {
|
|
error = cpcap_adc_read_st_die_temp(ddata,
|
|
chan->address,
|
|
&req.result);
|
|
if (error)
|
|
goto err_unlock;
|
|
} else {
|
|
error = cpcap_adc_read_bank_scaled(ddata, &req);
|
|
if (error)
|
|
goto err_unlock;
|
|
}
|
|
error = cpcap_adc_stop_bank(ddata);
|
|
if (error)
|
|
goto err_unlock;
|
|
mutex_unlock(&ddata->lock);
|
|
*val = req.result;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return IIO_VAL_INT;
|
|
|
|
err_unlock:
|
|
mutex_unlock(&ddata->lock);
|
|
dev_err(ddata->dev, "error reading ADC: %i\n", error);
|
|
|
|
return error;
|
|
}
|
|
|
|
static const struct iio_info cpcap_adc_info = {
|
|
.read_raw = &cpcap_adc_read,
|
|
};
|
|
|
|
/*
|
|
* Configuration for Motorola mapphone series such as droid 4.
|
|
* Copied from the Motorola mapphone kernel tree.
|
|
*/
|
|
static const struct cpcap_adc_ato mapphone_adc = {
|
|
.ato_in = 0x0480,
|
|
.atox_in = 0,
|
|
.adc_ps_factor_in = 0x0200,
|
|
.atox_ps_factor_in = 0,
|
|
.ato_out = 0,
|
|
.atox_out = 0,
|
|
.adc_ps_factor_out = 0,
|
|
.atox_ps_factor_out = 0,
|
|
};
|
|
|
|
static const struct of_device_id cpcap_adc_id_table[] = {
|
|
{
|
|
.compatible = "motorola,cpcap-adc",
|
|
},
|
|
{
|
|
.compatible = "motorola,mapphone-cpcap-adc",
|
|
.data = &mapphone_adc,
|
|
},
|
|
{ /* sentinel */ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, cpcap_adc_id_table);
|
|
|
|
static int cpcap_adc_probe(struct platform_device *pdev)
|
|
{
|
|
const struct of_device_id *match;
|
|
struct cpcap_adc *ddata;
|
|
struct iio_dev *indio_dev;
|
|
int error;
|
|
|
|
match = of_match_device(of_match_ptr(cpcap_adc_id_table),
|
|
&pdev->dev);
|
|
if (!match)
|
|
return -EINVAL;
|
|
|
|
if (!match->data) {
|
|
dev_err(&pdev->dev, "no configuration data found\n");
|
|
|
|
return -ENODEV;
|
|
}
|
|
|
|
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*ddata));
|
|
if (!indio_dev) {
|
|
dev_err(&pdev->dev, "failed to allocate iio device\n");
|
|
|
|
return -ENOMEM;
|
|
}
|
|
ddata = iio_priv(indio_dev);
|
|
ddata->ato = match->data;
|
|
ddata->dev = &pdev->dev;
|
|
|
|
mutex_init(&ddata->lock);
|
|
init_waitqueue_head(&ddata->wq_data_avail);
|
|
|
|
indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
|
|
indio_dev->dev.parent = &pdev->dev;
|
|
indio_dev->dev.of_node = pdev->dev.of_node;
|
|
indio_dev->channels = cpcap_adc_channels;
|
|
indio_dev->num_channels = ARRAY_SIZE(cpcap_adc_channels);
|
|
indio_dev->name = dev_name(&pdev->dev);
|
|
indio_dev->info = &cpcap_adc_info;
|
|
|
|
ddata->reg = dev_get_regmap(pdev->dev.parent, NULL);
|
|
if (!ddata->reg)
|
|
return -ENODEV;
|
|
|
|
error = cpcap_get_vendor(ddata->dev, ddata->reg, &ddata->vendor);
|
|
if (error)
|
|
return error;
|
|
|
|
platform_set_drvdata(pdev, indio_dev);
|
|
|
|
ddata->irq = platform_get_irq_byname(pdev, "adcdone");
|
|
if (ddata->irq < 0)
|
|
return -ENODEV;
|
|
|
|
error = devm_request_threaded_irq(&pdev->dev, ddata->irq, NULL,
|
|
cpcap_adc_irq_thread,
|
|
IRQF_TRIGGER_NONE,
|
|
"cpcap-adc", indio_dev);
|
|
if (error) {
|
|
dev_err(&pdev->dev, "could not get irq: %i\n",
|
|
error);
|
|
|
|
return error;
|
|
}
|
|
|
|
error = cpcap_adc_calibrate(ddata);
|
|
if (error)
|
|
return error;
|
|
|
|
dev_info(&pdev->dev, "CPCAP ADC device probed\n");
|
|
|
|
return devm_iio_device_register(&pdev->dev, indio_dev);
|
|
}
|
|
|
|
static struct platform_driver cpcap_adc_driver = {
|
|
.driver = {
|
|
.name = "cpcap_adc",
|
|
.of_match_table = of_match_ptr(cpcap_adc_id_table),
|
|
},
|
|
.probe = cpcap_adc_probe,
|
|
};
|
|
|
|
module_platform_driver(cpcap_adc_driver);
|
|
|
|
MODULE_ALIAS("platform:cpcap_adc");
|
|
MODULE_DESCRIPTION("CPCAP ADC driver");
|
|
MODULE_AUTHOR("Tony Lindgren <tony@atomide.com");
|
|
MODULE_LICENSE("GPL v2");
|