WSL2-Linux-Kernel/Documentation/devicetree/bindings/riscv
Krzysztof Kozlowski f46428f066 dt-bindings: riscv: correct e51 and u54-mc CPU bindings
All existing boards with sifive,e51 and sifive,u54-mc use it on top of
sifive,rocket0 compatible:

  arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: cpu@0: compatible: 'oneOf' conditional failed, one must be fixed:
    ['sifive,e51', 'sifive,rocket0', 'riscv'] is too long
    Additional items are not allowed ('riscv' was unexpected)
    Additional items are not allowed ('sifive,rocket0', 'riscv' were unexpected)
    'riscv' was expected

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210920132559.151678-1-krzysztof.kozlowski@canonical.com
Signed-off-by: Rob Herring <robh@kernel.org>
2021-09-20 17:00:32 -05:00
..
canaan.yaml dt-bindings: add Canaan boards compatible strings 2021-02-22 17:51:06 -08:00
cpus.yaml dt-bindings: riscv: correct e51 and u54-mc CPU bindings 2021-09-20 17:00:32 -05:00
microchip.yaml dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC 2021-04-26 08:31:30 -07:00
sifive-l2-cache.yaml dt-bindings: sifive-l2-cache: Fix 'select' matching 2021-08-19 20:55:49 -07:00
sifive.yaml dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched board 2021-01-07 17:37:41 -08:00
starfive.yaml dt-bindings: riscv: add starfive jh7100 bindings 2021-08-04 13:25:28 -07:00