554 строки
17 KiB
C
554 строки
17 KiB
C
/*
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* XHCI HCD glue for Cavium Octeon III SOCs.
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*
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* Copyright (C) 2010-2017 Cavium Networks
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/mutex.h>
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#include <linux/delay.h>
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#include <linux/of_platform.h>
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#include <linux/io.h>
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#include <asm/octeon/octeon.h>
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/* USB Control Register */
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union cvm_usbdrd_uctl_ctl {
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uint64_t u64;
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struct cvm_usbdrd_uctl_ctl_s {
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/* 1 = BIST and set all USB RAMs to 0x0, 0 = BIST */
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__BITFIELD_FIELD(uint64_t clear_bist:1,
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/* 1 = Start BIST and cleared by hardware */
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__BITFIELD_FIELD(uint64_t start_bist:1,
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/* Reference clock select for SuperSpeed and HighSpeed PLLs:
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* 0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock
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* 0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock
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* 0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock &
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* HighSpeed PLL uses PLL_REF_CLK for reference clck
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* 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock &
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* HighSpeed PLL uses PLL_REF_CLK for reference clck
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*/
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__BITFIELD_FIELD(uint64_t ref_clk_sel:2,
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/* 1 = Spread-spectrum clock enable, 0 = SS clock disable */
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__BITFIELD_FIELD(uint64_t ssc_en:1,
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/* Spread-spectrum clock modulation range:
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* 0x0 = -4980 ppm downspread
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* 0x1 = -4492 ppm downspread
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* 0x2 = -4003 ppm downspread
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* 0x3 - 0x7 = Reserved
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*/
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__BITFIELD_FIELD(uint64_t ssc_range:3,
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/* Enable non-standard oscillator frequencies:
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* [55:53] = modules -1
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* [52:47] = 2's complement push amount, 0 = Feature disabled
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*/
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__BITFIELD_FIELD(uint64_t ssc_ref_clk_sel:9,
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/* Reference clock multiplier for non-standard frequencies:
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* 0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
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* 0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
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* 0x32 = 50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
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* Other Values = Reserved
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*/
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__BITFIELD_FIELD(uint64_t mpll_multiplier:7,
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/* Enable reference clock to prescaler for SuperSpeed functionality.
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* Should always be set to "1"
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*/
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__BITFIELD_FIELD(uint64_t ref_ssp_en:1,
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/* Divide the reference clock by 2 before entering the
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* REF_CLK_FSEL divider:
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* If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal
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* If REF_CLK_SEL = 0x2 or 0x3, then:
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* 0x1 = DLMC_REF_CLK* is 125MHz
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* 0x0 = DLMC_REF_CLK* is another supported frequency
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*/
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__BITFIELD_FIELD(uint64_t ref_clk_div2:1,
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/* Select reference clock freqnuency for both PLL blocks:
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* 0x27 = REF_CLK_SEL is 0x0 or 0x1
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* 0x07 = REF_CLK_SEL is 0x2 or 0x3
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*/
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__BITFIELD_FIELD(uint64_t ref_clk_fsel:6,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_31_31:1,
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/* Controller clock enable. */
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__BITFIELD_FIELD(uint64_t h_clk_en:1,
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/* Select bypass input to controller clock divider:
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* 0x0 = Use divided coprocessor clock from H_CLKDIV
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* 0x1 = Use clock from GPIO pins
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*/
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__BITFIELD_FIELD(uint64_t h_clk_byp_sel:1,
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/* Reset controller clock divider. */
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__BITFIELD_FIELD(uint64_t h_clkdiv_rst:1,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_27_27:1,
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/* Clock divider select:
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* 0x0 = divide by 1
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* 0x1 = divide by 2
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* 0x2 = divide by 4
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* 0x3 = divide by 6
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* 0x4 = divide by 8
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* 0x5 = divide by 16
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* 0x6 = divide by 24
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* 0x7 = divide by 32
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*/
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__BITFIELD_FIELD(uint64_t h_clkdiv_sel:3,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_22_23:2,
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/* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */
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__BITFIELD_FIELD(uint64_t usb3_port_perm_attach:1,
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/* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */
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__BITFIELD_FIELD(uint64_t usb2_port_perm_attach:1,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_19_19:1,
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/* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */
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__BITFIELD_FIELD(uint64_t usb3_port_disable:1,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_17_17:1,
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/* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */
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__BITFIELD_FIELD(uint64_t usb2_port_disable:1,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_15_15:1,
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/* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */
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__BITFIELD_FIELD(uint64_t ss_power_en:1,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_13_13:1,
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/* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */
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__BITFIELD_FIELD(uint64_t hs_power_en:1,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_5_11:7,
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/* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */
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__BITFIELD_FIELD(uint64_t csclk_en:1,
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/* Controller mode: 0x0 = Host, 0x1 = Device */
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__BITFIELD_FIELD(uint64_t drd_mode:1,
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/* PHY reset */
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__BITFIELD_FIELD(uint64_t uphy_rst:1,
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/* Software reset UAHC */
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__BITFIELD_FIELD(uint64_t uahc_rst:1,
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/* Software resets UCTL */
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__BITFIELD_FIELD(uint64_t uctl_rst:1,
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;)))))))))))))))))))))))))))))))))
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} s;
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};
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/* UAHC Configuration Register */
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union cvm_usbdrd_uctl_host_cfg {
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uint64_t u64;
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struct cvm_usbdrd_uctl_host_cfg_s {
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_60_63:4,
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/* Indicates minimum value of all received BELT values */
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__BITFIELD_FIELD(uint64_t host_current_belt:12,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_38_47:10,
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/* HS jitter adjustment */
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__BITFIELD_FIELD(uint64_t fla:6,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_29_31:3,
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/* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */
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__BITFIELD_FIELD(uint64_t bme:1,
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/* Overcurrent protection enable: 0x0 = unavailable, 0x1 = available */
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__BITFIELD_FIELD(uint64_t oci_en:1,
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/* Overcurrent sene selection:
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* 0x0 = Overcurrent indication from off-chip is active-low
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* 0x1 = Overcurrent indication from off-chip is active-high
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*/
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__BITFIELD_FIELD(uint64_t oci_active_high_en:1,
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/* Port power control enable: 0x0 = unavailable, 0x1 = available */
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__BITFIELD_FIELD(uint64_t ppc_en:1,
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/* Port power control sense selection:
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* 0x0 = Port power to off-chip is active-low
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* 0x1 = Port power to off-chip is active-high
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*/
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__BITFIELD_FIELD(uint64_t ppc_active_high_en:1,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_0_23:24,
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;)))))))))))
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} s;
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};
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/* UCTL Shim Features Register */
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union cvm_usbdrd_uctl_shim_cfg {
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uint64_t u64;
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struct cvm_usbdrd_uctl_shim_cfg_s {
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/* Out-of-bound UAHC register access: 0 = read, 1 = write */
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__BITFIELD_FIELD(uint64_t xs_ncb_oob_wrn:1,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_60_62:3,
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/* SRCID error log for out-of-bound UAHC register access:
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* [59:58] = chipID
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* [57] = Request source: 0 = core, 1 = NCB-device
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* [56:51] = Core/NCB-device number, [56] always 0 for NCB devices
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* [50:48] = SubID
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*/
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__BITFIELD_FIELD(uint64_t xs_ncb_oob_osrc:12,
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/* Error log for bad UAHC DMA access: 0 = Read log, 1 = Write log */
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__BITFIELD_FIELD(uint64_t xm_bad_dma_wrn:1,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_44_46:3,
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/* Encoded error type for bad UAHC DMA */
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__BITFIELD_FIELD(uint64_t xm_bad_dma_type:4,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_13_39:27,
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/* Select the IOI read command used by DMA accesses */
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__BITFIELD_FIELD(uint64_t dma_read_cmd:1,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_10_11:2,
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/* Select endian format for DMA accesses to the L2c:
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* 0x0 = Little endian
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*` 0x1 = Big endian
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* 0x2 = Reserved
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* 0x3 = Reserved
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*/
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__BITFIELD_FIELD(uint64_t dma_endian_mode:2,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_2_7:6,
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/* Select endian format for IOI CSR access to UAHC:
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* 0x0 = Little endian
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*` 0x1 = Big endian
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* 0x2 = Reserved
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* 0x3 = Reserved
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*/
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__BITFIELD_FIELD(uint64_t csr_endian_mode:2,
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;))))))))))))
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} s;
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};
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#define OCTEON_H_CLKDIV_SEL 8
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#define OCTEON_MIN_H_CLK_RATE 150000000
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#define OCTEON_MAX_H_CLK_RATE 300000000
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static DEFINE_MUTEX(dwc3_octeon_clocks_mutex);
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static uint8_t clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32};
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static int dwc3_octeon_config_power(struct device *dev, u64 base)
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{
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#define UCTL_HOST_CFG 0xe0
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union cvm_usbdrd_uctl_host_cfg uctl_host_cfg;
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union cvmx_gpio_bit_cfgx gpio_bit;
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uint32_t gpio_pwr[3];
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int gpio, len, power_active_low;
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struct device_node *node = dev->of_node;
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int index = (base >> 24) & 1;
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if (of_find_property(node, "power", &len) != NULL) {
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if (len == 12) {
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of_property_read_u32_array(node, "power", gpio_pwr, 3);
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power_active_low = gpio_pwr[2] & 0x01;
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gpio = gpio_pwr[1];
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} else if (len == 8) {
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of_property_read_u32_array(node, "power", gpio_pwr, 2);
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power_active_low = 0;
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gpio = gpio_pwr[1];
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} else {
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dev_err(dev, "dwc3 controller clock init failure.\n");
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return -EINVAL;
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}
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if ((OCTEON_IS_MODEL(OCTEON_CN73XX) ||
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OCTEON_IS_MODEL(OCTEON_CNF75XX))
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&& gpio <= 31) {
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gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
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gpio_bit.s.tx_oe = 1;
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gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x15);
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cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
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} else if (gpio <= 15) {
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gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
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gpio_bit.s.tx_oe = 1;
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gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19);
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cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
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} else {
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gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio));
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gpio_bit.s.tx_oe = 1;
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gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19);
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cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64);
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}
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/* Enable XHCI power control and set if active high or low. */
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uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG);
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uctl_host_cfg.s.ppc_en = 1;
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uctl_host_cfg.s.ppc_active_high_en = !power_active_low;
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cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64);
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} else {
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/* Disable XHCI power control and set if active high. */
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uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG);
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uctl_host_cfg.s.ppc_en = 0;
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uctl_host_cfg.s.ppc_active_high_en = 0;
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cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64);
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dev_warn(dev, "dwc3 controller clock init failure.\n");
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}
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return 0;
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}
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static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
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{
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union cvm_usbdrd_uctl_ctl uctl_ctl;
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int ref_clk_sel = 2;
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u64 div;
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u32 clock_rate;
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int mpll_mul;
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int i;
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u64 h_clk_rate;
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u64 uctl_ctl_reg = base;
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if (dev->of_node) {
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const char *ss_clock_type;
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const char *hs_clock_type;
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i = of_property_read_u32(dev->of_node,
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"refclk-frequency", &clock_rate);
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if (i) {
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pr_err("No UCTL \"refclk-frequency\"\n");
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return -EINVAL;
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}
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i = of_property_read_string(dev->of_node,
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"refclk-type-ss", &ss_clock_type);
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if (i) {
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pr_err("No UCTL \"refclk-type-ss\"\n");
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return -EINVAL;
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}
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i = of_property_read_string(dev->of_node,
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"refclk-type-hs", &hs_clock_type);
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if (i) {
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pr_err("No UCTL \"refclk-type-hs\"\n");
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return -EINVAL;
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}
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if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) {
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if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0)
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ref_clk_sel = 0;
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else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)
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ref_clk_sel = 2;
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else
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pr_err("Invalid HS clock type %s, using pll_ref_clk instead\n",
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hs_clock_type);
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} else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) {
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if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0)
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ref_clk_sel = 1;
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else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)
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ref_clk_sel = 3;
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else {
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pr_err("Invalid HS clock type %s, using pll_ref_clk instead\n",
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hs_clock_type);
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ref_clk_sel = 3;
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}
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} else
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pr_err("Invalid SS clock type %s, using dlmc_ref_clk0 instead\n",
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ss_clock_type);
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if ((ref_clk_sel == 0 || ref_clk_sel == 1) &&
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(clock_rate != 100000000))
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pr_err("Invalid UCTL clock rate of %u, using 100000000 instead\n",
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clock_rate);
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} else {
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pr_err("No USB UCTL device node\n");
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return -EINVAL;
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}
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/*
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* Step 1: Wait for all voltages to be stable...that surely
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* happened before starting the kernel. SKIP
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*/
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/* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */
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/* Step 3: Assert all resets. */
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uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
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uctl_ctl.s.uphy_rst = 1;
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uctl_ctl.s.uahc_rst = 1;
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uctl_ctl.s.uctl_rst = 1;
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cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
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/* Step 4a: Reset the clock dividers. */
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uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
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uctl_ctl.s.h_clkdiv_rst = 1;
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cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
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/* Step 4b: Select controller clock frequency. */
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for (div = 0; div < OCTEON_H_CLKDIV_SEL; div++) {
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h_clk_rate = octeon_get_io_clock_rate() / clk_div[div];
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if (h_clk_rate <= OCTEON_MAX_H_CLK_RATE &&
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h_clk_rate >= OCTEON_MIN_H_CLK_RATE)
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break;
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}
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uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
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uctl_ctl.s.h_clkdiv_sel = div;
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uctl_ctl.s.h_clk_en = 1;
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cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
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uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
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if ((div != uctl_ctl.s.h_clkdiv_sel) || (!uctl_ctl.s.h_clk_en)) {
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dev_err(dev, "dwc3 controller clock init failure.\n");
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return -EINVAL;
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}
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/* Step 4c: Deassert the controller clock divider reset. */
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uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
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uctl_ctl.s.h_clkdiv_rst = 0;
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cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
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/* Step 5a: Reference clock configuration. */
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uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
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uctl_ctl.s.ref_clk_sel = ref_clk_sel;
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uctl_ctl.s.ref_clk_fsel = 0x07;
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uctl_ctl.s.ref_clk_div2 = 0;
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switch (clock_rate) {
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default:
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dev_err(dev, "Invalid ref_clk %u, using 100000000 instead\n",
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clock_rate);
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/* fall through */
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case 100000000:
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mpll_mul = 0x19;
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if (ref_clk_sel < 2)
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uctl_ctl.s.ref_clk_fsel = 0x27;
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break;
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case 50000000:
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mpll_mul = 0x32;
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break;
|
|
case 125000000:
|
|
mpll_mul = 0x28;
|
|
break;
|
|
}
|
|
uctl_ctl.s.mpll_multiplier = mpll_mul;
|
|
|
|
/* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */
|
|
uctl_ctl.s.ssc_en = 1;
|
|
|
|
/* Step 5c: Enable SuperSpeed. */
|
|
uctl_ctl.s.ref_ssp_en = 1;
|
|
|
|
/* Step 5d: Cofngiure PHYs. SKIP */
|
|
|
|
/* Step 6a & 6b: Power up PHYs. */
|
|
uctl_ctl.s.hs_power_en = 1;
|
|
uctl_ctl.s.ss_power_en = 1;
|
|
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
|
|
|
|
/* Step 7: Wait 10 controller-clock cycles to take effect. */
|
|
udelay(10);
|
|
|
|
/* Step 8a: Deassert UCTL reset signal. */
|
|
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
|
|
uctl_ctl.s.uctl_rst = 0;
|
|
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
|
|
|
|
/* Step 8b: Wait 10 controller-clock cycles. */
|
|
udelay(10);
|
|
|
|
/* Steo 8c: Setup power-power control. */
|
|
if (dwc3_octeon_config_power(dev, base)) {
|
|
dev_err(dev, "Error configuring power.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Step 8d: Deassert UAHC reset signal. */
|
|
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
|
|
uctl_ctl.s.uahc_rst = 0;
|
|
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
|
|
|
|
/* Step 8e: Wait 10 controller-clock cycles. */
|
|
udelay(10);
|
|
|
|
/* Step 9: Enable conditional coprocessor clock of UCTL. */
|
|
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
|
|
uctl_ctl.s.csclk_en = 1;
|
|
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
|
|
|
|
/*Step 10: Set for host mode only. */
|
|
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
|
|
uctl_ctl.s.drd_mode = 0;
|
|
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __init dwc3_octeon_set_endian_mode(u64 base)
|
|
{
|
|
#define UCTL_SHIM_CFG 0xe8
|
|
union cvm_usbdrd_uctl_shim_cfg shim_cfg;
|
|
|
|
shim_cfg.u64 = cvmx_read_csr(base + UCTL_SHIM_CFG);
|
|
#ifdef __BIG_ENDIAN
|
|
shim_cfg.s.dma_endian_mode = 1;
|
|
shim_cfg.s.csr_endian_mode = 1;
|
|
#else
|
|
shim_cfg.s.dma_endian_mode = 0;
|
|
shim_cfg.s.csr_endian_mode = 0;
|
|
#endif
|
|
cvmx_write_csr(base + UCTL_SHIM_CFG, shim_cfg.u64);
|
|
}
|
|
|
|
#define CVMX_USBDRDX_UCTL_CTL(index) \
|
|
(CVMX_ADD_IO_SEG(0x0001180068000000ull) + \
|
|
((index & 1) * 0x1000000ull))
|
|
static void __init dwc3_octeon_phy_reset(u64 base)
|
|
{
|
|
union cvm_usbdrd_uctl_ctl uctl_ctl;
|
|
int index = (base >> 24) & 1;
|
|
|
|
uctl_ctl.u64 = cvmx_read_csr(CVMX_USBDRDX_UCTL_CTL(index));
|
|
uctl_ctl.s.uphy_rst = 0;
|
|
cvmx_write_csr(CVMX_USBDRDX_UCTL_CTL(index), uctl_ctl.u64);
|
|
}
|
|
|
|
static int __init dwc3_octeon_device_init(void)
|
|
{
|
|
const char compat_node_name[] = "cavium,octeon-7130-usb-uctl";
|
|
struct platform_device *pdev;
|
|
struct device_node *node;
|
|
struct resource *res;
|
|
void __iomem *base;
|
|
|
|
/*
|
|
* There should only be three universal controllers, "uctl"
|
|
* in the device tree. Two USB and a SATA, which we ignore.
|
|
*/
|
|
node = NULL;
|
|
do {
|
|
node = of_find_node_by_name(node, "uctl");
|
|
if (!node)
|
|
return -ENODEV;
|
|
|
|
if (of_device_is_compatible(node, compat_node_name)) {
|
|
pdev = of_find_device_by_node(node);
|
|
if (!pdev)
|
|
return -ENODEV;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (res == NULL) {
|
|
dev_err(&pdev->dev, "No memory resources\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
/*
|
|
* The code below maps in the registers necessary for
|
|
* setting up the clocks and reseting PHYs. We must
|
|
* release the resources so the dwc3 subsystem doesn't
|
|
* know the difference.
|
|
*/
|
|
base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
mutex_lock(&dwc3_octeon_clocks_mutex);
|
|
dwc3_octeon_clocks_start(&pdev->dev, (u64)base);
|
|
dwc3_octeon_set_endian_mode((u64)base);
|
|
dwc3_octeon_phy_reset((u64)base);
|
|
dev_info(&pdev->dev, "clocks initialized.\n");
|
|
mutex_unlock(&dwc3_octeon_clocks_mutex);
|
|
devm_iounmap(&pdev->dev, base);
|
|
devm_release_mem_region(&pdev->dev, res->start,
|
|
resource_size(res));
|
|
}
|
|
} while (node != NULL);
|
|
|
|
return 0;
|
|
}
|
|
device_initcall(dwc3_octeon_device_init);
|
|
|
|
MODULE_AUTHOR("David Daney <david.daney@cavium.com>");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("USB driver for OCTEON III SoC");
|