1039 строки
24 KiB
C
1039 строки
24 KiB
C
/* irq.c: UltraSparc IRQ handling/init/registry.
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*
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* Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
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* Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
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* Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
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*/
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/linkage.h>
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#include <linux/ptrace.h>
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#include <linux/errno.h>
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#include <linux/kernel_stat.h>
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#include <linux/signal.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/proc_fs.h>
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#include <linux/seq_file.h>
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#include <linux/bootmem.h>
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#include <linux/irq.h>
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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#include <asm/atomic.h>
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#include <asm/system.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/iommu.h>
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#include <asm/upa.h>
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#include <asm/oplib.h>
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#include <asm/prom.h>
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#include <asm/timer.h>
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#include <asm/smp.h>
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#include <asm/starfire.h>
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#include <asm/uaccess.h>
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#include <asm/cache.h>
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#include <asm/cpudata.h>
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#include <asm/auxio.h>
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#include <asm/head.h>
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#include <asm/hypervisor.h>
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#include <asm/cacheflush.h>
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#include "entry.h"
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#define NUM_IVECS (IMAP_INR + 1)
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struct ino_bucket *ivector_table;
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unsigned long ivector_table_pa;
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/* On several sun4u processors, it is illegal to mix bypass and
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* non-bypass accesses. Therefore we access all INO buckets
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* using bypass accesses only.
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*/
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static unsigned long bucket_get_chain_pa(unsigned long bucket_pa)
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{
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unsigned long ret;
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__asm__ __volatile__("ldxa [%1] %2, %0"
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: "=&r" (ret)
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: "r" (bucket_pa +
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offsetof(struct ino_bucket,
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__irq_chain_pa)),
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"i" (ASI_PHYS_USE_EC));
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return ret;
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}
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static void bucket_clear_chain_pa(unsigned long bucket_pa)
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{
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__asm__ __volatile__("stxa %%g0, [%0] %1"
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: /* no outputs */
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: "r" (bucket_pa +
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offsetof(struct ino_bucket,
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__irq_chain_pa)),
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"i" (ASI_PHYS_USE_EC));
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}
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static unsigned int bucket_get_virt_irq(unsigned long bucket_pa)
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{
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unsigned int ret;
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__asm__ __volatile__("lduwa [%1] %2, %0"
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: "=&r" (ret)
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: "r" (bucket_pa +
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offsetof(struct ino_bucket,
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__virt_irq)),
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"i" (ASI_PHYS_USE_EC));
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return ret;
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}
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static void bucket_set_virt_irq(unsigned long bucket_pa,
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unsigned int virt_irq)
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{
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__asm__ __volatile__("stwa %0, [%1] %2"
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: /* no outputs */
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: "r" (virt_irq),
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"r" (bucket_pa +
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offsetof(struct ino_bucket,
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__virt_irq)),
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"i" (ASI_PHYS_USE_EC));
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}
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#define irq_work_pa(__cpu) &(trap_block[(__cpu)].irq_worklist_pa)
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static struct {
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unsigned int dev_handle;
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unsigned int dev_ino;
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unsigned int in_use;
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} virt_irq_table[NR_IRQS];
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static DEFINE_SPINLOCK(virt_irq_alloc_lock);
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unsigned char virt_irq_alloc(unsigned int dev_handle,
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unsigned int dev_ino)
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{
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unsigned long flags;
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unsigned char ent;
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BUILD_BUG_ON(NR_IRQS >= 256);
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spin_lock_irqsave(&virt_irq_alloc_lock, flags);
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for (ent = 1; ent < NR_IRQS; ent++) {
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if (!virt_irq_table[ent].in_use)
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break;
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}
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if (ent >= NR_IRQS) {
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printk(KERN_ERR "IRQ: Out of virtual IRQs.\n");
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ent = 0;
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} else {
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virt_irq_table[ent].dev_handle = dev_handle;
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virt_irq_table[ent].dev_ino = dev_ino;
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virt_irq_table[ent].in_use = 1;
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}
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spin_unlock_irqrestore(&virt_irq_alloc_lock, flags);
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return ent;
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}
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#ifdef CONFIG_PCI_MSI
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void virt_irq_free(unsigned int virt_irq)
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{
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unsigned long flags;
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if (virt_irq >= NR_IRQS)
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return;
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spin_lock_irqsave(&virt_irq_alloc_lock, flags);
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virt_irq_table[virt_irq].in_use = 0;
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spin_unlock_irqrestore(&virt_irq_alloc_lock, flags);
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}
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#endif
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/*
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* /proc/interrupts printing:
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*/
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int show_interrupts(struct seq_file *p, void *v)
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{
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int i = *(loff_t *) v, j;
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struct irqaction * action;
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unsigned long flags;
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if (i == 0) {
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seq_printf(p, " ");
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for_each_online_cpu(j)
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seq_printf(p, "CPU%d ",j);
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seq_putc(p, '\n');
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}
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if (i < NR_IRQS) {
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spin_lock_irqsave(&irq_desc[i].lock, flags);
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action = irq_desc[i].action;
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if (!action)
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goto skip;
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seq_printf(p, "%3d: ",i);
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#ifndef CONFIG_SMP
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seq_printf(p, "%10u ", kstat_irqs(i));
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#else
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
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#endif
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seq_printf(p, " %9s", irq_desc[i].chip->typename);
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seq_printf(p, " %s", action->name);
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for (action=action->next; action; action = action->next)
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seq_printf(p, ", %s", action->name);
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seq_putc(p, '\n');
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skip:
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spin_unlock_irqrestore(&irq_desc[i].lock, flags);
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}
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return 0;
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}
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static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
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{
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unsigned int tid;
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if (this_is_starfire) {
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tid = starfire_translate(imap, cpuid);
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tid <<= IMAP_TID_SHIFT;
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tid &= IMAP_TID_UPA;
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} else {
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if (tlb_type == cheetah || tlb_type == cheetah_plus) {
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unsigned long ver;
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__asm__ ("rdpr %%ver, %0" : "=r" (ver));
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if ((ver >> 32UL) == __JALAPENO_ID ||
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(ver >> 32UL) == __SERRANO_ID) {
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tid = cpuid << IMAP_TID_SHIFT;
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tid &= IMAP_TID_JBUS;
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} else {
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unsigned int a = cpuid & 0x1f;
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unsigned int n = (cpuid >> 5) & 0x1f;
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tid = ((a << IMAP_AID_SHIFT) |
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(n << IMAP_NID_SHIFT));
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tid &= (IMAP_AID_SAFARI |
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IMAP_NID_SAFARI);;
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}
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} else {
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tid = cpuid << IMAP_TID_SHIFT;
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tid &= IMAP_TID_UPA;
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}
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}
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return tid;
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}
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struct irq_handler_data {
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unsigned long iclr;
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unsigned long imap;
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void (*pre_handler)(unsigned int, void *, void *);
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void *arg1;
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void *arg2;
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};
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#ifdef CONFIG_SMP
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static int irq_choose_cpu(unsigned int virt_irq)
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{
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cpumask_t mask = irq_desc[virt_irq].affinity;
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int cpuid;
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if (cpus_equal(mask, CPU_MASK_ALL)) {
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static int irq_rover;
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static DEFINE_SPINLOCK(irq_rover_lock);
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unsigned long flags;
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/* Round-robin distribution... */
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do_round_robin:
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spin_lock_irqsave(&irq_rover_lock, flags);
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while (!cpu_online(irq_rover)) {
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if (++irq_rover >= NR_CPUS)
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irq_rover = 0;
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}
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cpuid = irq_rover;
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do {
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if (++irq_rover >= NR_CPUS)
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irq_rover = 0;
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} while (!cpu_online(irq_rover));
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spin_unlock_irqrestore(&irq_rover_lock, flags);
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} else {
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cpumask_t tmp;
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cpus_and(tmp, cpu_online_map, mask);
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if (cpus_empty(tmp))
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goto do_round_robin;
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cpuid = first_cpu(tmp);
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}
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return cpuid;
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}
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#else
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static int irq_choose_cpu(unsigned int virt_irq)
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{
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return real_hard_smp_processor_id();
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}
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#endif
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static void sun4u_irq_enable(unsigned int virt_irq)
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{
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struct irq_handler_data *data = get_irq_chip_data(virt_irq);
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if (likely(data)) {
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unsigned long cpuid, imap, val;
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unsigned int tid;
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cpuid = irq_choose_cpu(virt_irq);
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imap = data->imap;
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tid = sun4u_compute_tid(imap, cpuid);
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val = upa_readq(imap);
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val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
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IMAP_AID_SAFARI | IMAP_NID_SAFARI);
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val |= tid | IMAP_VALID;
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upa_writeq(val, imap);
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upa_writeq(ICLR_IDLE, data->iclr);
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}
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}
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static void sun4u_set_affinity(unsigned int virt_irq, cpumask_t mask)
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{
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sun4u_irq_enable(virt_irq);
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}
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static void sun4u_irq_disable(unsigned int virt_irq)
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{
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struct irq_handler_data *data = get_irq_chip_data(virt_irq);
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if (likely(data)) {
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unsigned long imap = data->imap;
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unsigned long tmp = upa_readq(imap);
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tmp &= ~IMAP_VALID;
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upa_writeq(tmp, imap);
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}
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}
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static void sun4u_irq_eoi(unsigned int virt_irq)
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{
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struct irq_handler_data *data = get_irq_chip_data(virt_irq);
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struct irq_desc *desc = irq_desc + virt_irq;
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if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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return;
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if (likely(data))
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upa_writeq(ICLR_IDLE, data->iclr);
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}
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static void sun4v_irq_enable(unsigned int virt_irq)
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{
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unsigned int ino = virt_irq_table[virt_irq].dev_ino;
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unsigned long cpuid = irq_choose_cpu(virt_irq);
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int err;
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err = sun4v_intr_settarget(ino, cpuid);
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if (err != HV_EOK)
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printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
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"err(%d)\n", ino, cpuid, err);
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err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
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if (err != HV_EOK)
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printk(KERN_ERR "sun4v_intr_setstate(%x): "
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"err(%d)\n", ino, err);
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err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
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if (err != HV_EOK)
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printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n",
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ino, err);
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}
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static void sun4v_set_affinity(unsigned int virt_irq, cpumask_t mask)
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{
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unsigned int ino = virt_irq_table[virt_irq].dev_ino;
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unsigned long cpuid = irq_choose_cpu(virt_irq);
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int err;
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err = sun4v_intr_settarget(ino, cpuid);
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if (err != HV_EOK)
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printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
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"err(%d)\n", ino, cpuid, err);
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}
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static void sun4v_irq_disable(unsigned int virt_irq)
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{
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unsigned int ino = virt_irq_table[virt_irq].dev_ino;
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int err;
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err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
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if (err != HV_EOK)
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printk(KERN_ERR "sun4v_intr_setenabled(%x): "
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"err(%d)\n", ino, err);
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}
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static void sun4v_irq_eoi(unsigned int virt_irq)
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{
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unsigned int ino = virt_irq_table[virt_irq].dev_ino;
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struct irq_desc *desc = irq_desc + virt_irq;
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int err;
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if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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return;
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err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
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if (err != HV_EOK)
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printk(KERN_ERR "sun4v_intr_setstate(%x): "
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"err(%d)\n", ino, err);
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}
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static void sun4v_virq_enable(unsigned int virt_irq)
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{
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unsigned long cpuid, dev_handle, dev_ino;
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int err;
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cpuid = irq_choose_cpu(virt_irq);
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dev_handle = virt_irq_table[virt_irq].dev_handle;
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dev_ino = virt_irq_table[virt_irq].dev_ino;
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err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
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if (err != HV_EOK)
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printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
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"err(%d)\n",
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dev_handle, dev_ino, cpuid, err);
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err = sun4v_vintr_set_state(dev_handle, dev_ino,
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HV_INTR_STATE_IDLE);
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if (err != HV_EOK)
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printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
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"HV_INTR_STATE_IDLE): err(%d)\n",
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dev_handle, dev_ino, err);
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err = sun4v_vintr_set_valid(dev_handle, dev_ino,
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HV_INTR_ENABLED);
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if (err != HV_EOK)
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printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
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"HV_INTR_ENABLED): err(%d)\n",
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dev_handle, dev_ino, err);
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}
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static void sun4v_virt_set_affinity(unsigned int virt_irq, cpumask_t mask)
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{
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unsigned long cpuid, dev_handle, dev_ino;
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int err;
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cpuid = irq_choose_cpu(virt_irq);
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dev_handle = virt_irq_table[virt_irq].dev_handle;
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dev_ino = virt_irq_table[virt_irq].dev_ino;
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err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
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if (err != HV_EOK)
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printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
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"err(%d)\n",
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dev_handle, dev_ino, cpuid, err);
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}
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static void sun4v_virq_disable(unsigned int virt_irq)
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{
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unsigned long dev_handle, dev_ino;
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int err;
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dev_handle = virt_irq_table[virt_irq].dev_handle;
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dev_ino = virt_irq_table[virt_irq].dev_ino;
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err = sun4v_vintr_set_valid(dev_handle, dev_ino,
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HV_INTR_DISABLED);
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if (err != HV_EOK)
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printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
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"HV_INTR_DISABLED): err(%d)\n",
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dev_handle, dev_ino, err);
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}
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static void sun4v_virq_eoi(unsigned int virt_irq)
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{
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struct irq_desc *desc = irq_desc + virt_irq;
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unsigned long dev_handle, dev_ino;
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int err;
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if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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return;
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dev_handle = virt_irq_table[virt_irq].dev_handle;
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dev_ino = virt_irq_table[virt_irq].dev_ino;
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err = sun4v_vintr_set_state(dev_handle, dev_ino,
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HV_INTR_STATE_IDLE);
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if (err != HV_EOK)
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printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
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"HV_INTR_STATE_IDLE): err(%d)\n",
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dev_handle, dev_ino, err);
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}
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static struct irq_chip sun4u_irq = {
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.typename = "sun4u",
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.enable = sun4u_irq_enable,
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.disable = sun4u_irq_disable,
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.eoi = sun4u_irq_eoi,
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.set_affinity = sun4u_set_affinity,
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};
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static struct irq_chip sun4v_irq = {
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.typename = "sun4v",
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.enable = sun4v_irq_enable,
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.disable = sun4v_irq_disable,
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.eoi = sun4v_irq_eoi,
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.set_affinity = sun4v_set_affinity,
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};
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static struct irq_chip sun4v_virq = {
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.typename = "vsun4v",
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.enable = sun4v_virq_enable,
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.disable = sun4v_virq_disable,
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.eoi = sun4v_virq_eoi,
|
|
.set_affinity = sun4v_virt_set_affinity,
|
|
};
|
|
|
|
static void pre_flow_handler(unsigned int virt_irq,
|
|
struct irq_desc *desc)
|
|
{
|
|
struct irq_handler_data *data = get_irq_chip_data(virt_irq);
|
|
unsigned int ino = virt_irq_table[virt_irq].dev_ino;
|
|
|
|
data->pre_handler(ino, data->arg1, data->arg2);
|
|
|
|
handle_fasteoi_irq(virt_irq, desc);
|
|
}
|
|
|
|
void irq_install_pre_handler(int virt_irq,
|
|
void (*func)(unsigned int, void *, void *),
|
|
void *arg1, void *arg2)
|
|
{
|
|
struct irq_handler_data *data = get_irq_chip_data(virt_irq);
|
|
struct irq_desc *desc = irq_desc + virt_irq;
|
|
|
|
data->pre_handler = func;
|
|
data->arg1 = arg1;
|
|
data->arg2 = arg2;
|
|
|
|
desc->handle_irq = pre_flow_handler;
|
|
}
|
|
|
|
unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
|
|
{
|
|
struct ino_bucket *bucket;
|
|
struct irq_handler_data *data;
|
|
unsigned int virt_irq;
|
|
int ino;
|
|
|
|
BUG_ON(tlb_type == hypervisor);
|
|
|
|
ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
|
|
bucket = &ivector_table[ino];
|
|
virt_irq = bucket_get_virt_irq(__pa(bucket));
|
|
if (!virt_irq) {
|
|
virt_irq = virt_irq_alloc(0, ino);
|
|
bucket_set_virt_irq(__pa(bucket), virt_irq);
|
|
set_irq_chip_and_handler_name(virt_irq,
|
|
&sun4u_irq,
|
|
handle_fasteoi_irq,
|
|
"IVEC");
|
|
}
|
|
|
|
data = get_irq_chip_data(virt_irq);
|
|
if (unlikely(data))
|
|
goto out;
|
|
|
|
data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
|
|
if (unlikely(!data)) {
|
|
prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
|
|
prom_halt();
|
|
}
|
|
set_irq_chip_data(virt_irq, data);
|
|
|
|
data->imap = imap;
|
|
data->iclr = iclr;
|
|
|
|
out:
|
|
return virt_irq;
|
|
}
|
|
|
|
static unsigned int sun4v_build_common(unsigned long sysino,
|
|
struct irq_chip *chip)
|
|
{
|
|
struct ino_bucket *bucket;
|
|
struct irq_handler_data *data;
|
|
unsigned int virt_irq;
|
|
|
|
BUG_ON(tlb_type != hypervisor);
|
|
|
|
bucket = &ivector_table[sysino];
|
|
virt_irq = bucket_get_virt_irq(__pa(bucket));
|
|
if (!virt_irq) {
|
|
virt_irq = virt_irq_alloc(0, sysino);
|
|
bucket_set_virt_irq(__pa(bucket), virt_irq);
|
|
set_irq_chip_and_handler_name(virt_irq, chip,
|
|
handle_fasteoi_irq,
|
|
"IVEC");
|
|
}
|
|
|
|
data = get_irq_chip_data(virt_irq);
|
|
if (unlikely(data))
|
|
goto out;
|
|
|
|
data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
|
|
if (unlikely(!data)) {
|
|
prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
|
|
prom_halt();
|
|
}
|
|
set_irq_chip_data(virt_irq, data);
|
|
|
|
/* Catch accidental accesses to these things. IMAP/ICLR handling
|
|
* is done by hypervisor calls on sun4v platforms, not by direct
|
|
* register accesses.
|
|
*/
|
|
data->imap = ~0UL;
|
|
data->iclr = ~0UL;
|
|
|
|
out:
|
|
return virt_irq;
|
|
}
|
|
|
|
unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
|
|
{
|
|
unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino);
|
|
|
|
return sun4v_build_common(sysino, &sun4v_irq);
|
|
}
|
|
|
|
unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino)
|
|
{
|
|
struct irq_handler_data *data;
|
|
unsigned long hv_err, cookie;
|
|
struct ino_bucket *bucket;
|
|
struct irq_desc *desc;
|
|
unsigned int virt_irq;
|
|
|
|
bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC);
|
|
if (unlikely(!bucket))
|
|
return 0;
|
|
__flush_dcache_range((unsigned long) bucket,
|
|
((unsigned long) bucket +
|
|
sizeof(struct ino_bucket)));
|
|
|
|
virt_irq = virt_irq_alloc(devhandle, devino);
|
|
bucket_set_virt_irq(__pa(bucket), virt_irq);
|
|
|
|
set_irq_chip_and_handler_name(virt_irq, &sun4v_virq,
|
|
handle_fasteoi_irq,
|
|
"IVEC");
|
|
|
|
data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
|
|
if (unlikely(!data))
|
|
return 0;
|
|
|
|
/* In order to make the LDC channel startup sequence easier,
|
|
* especially wrt. locking, we do not let request_irq() enable
|
|
* the interrupt.
|
|
*/
|
|
desc = irq_desc + virt_irq;
|
|
desc->status |= IRQ_NOAUTOEN;
|
|
|
|
set_irq_chip_data(virt_irq, data);
|
|
|
|
/* Catch accidental accesses to these things. IMAP/ICLR handling
|
|
* is done by hypervisor calls on sun4v platforms, not by direct
|
|
* register accesses.
|
|
*/
|
|
data->imap = ~0UL;
|
|
data->iclr = ~0UL;
|
|
|
|
cookie = ~__pa(bucket);
|
|
hv_err = sun4v_vintr_set_cookie(devhandle, devino, cookie);
|
|
if (hv_err) {
|
|
prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] "
|
|
"err=%lu\n", devhandle, devino, hv_err);
|
|
prom_halt();
|
|
}
|
|
|
|
return virt_irq;
|
|
}
|
|
|
|
void ack_bad_irq(unsigned int virt_irq)
|
|
{
|
|
unsigned int ino = virt_irq_table[virt_irq].dev_ino;
|
|
|
|
if (!ino)
|
|
ino = 0xdeadbeef;
|
|
|
|
printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n",
|
|
ino, virt_irq);
|
|
}
|
|
|
|
void *hardirq_stack[NR_CPUS];
|
|
void *softirq_stack[NR_CPUS];
|
|
|
|
static __attribute__((always_inline)) void *set_hardirq_stack(void)
|
|
{
|
|
void *orig_sp, *sp = hardirq_stack[smp_processor_id()];
|
|
|
|
__asm__ __volatile__("mov %%sp, %0" : "=r" (orig_sp));
|
|
if (orig_sp < sp ||
|
|
orig_sp > (sp + THREAD_SIZE)) {
|
|
sp += THREAD_SIZE - 192 - STACK_BIAS;
|
|
__asm__ __volatile__("mov %0, %%sp" : : "r" (sp));
|
|
}
|
|
|
|
return orig_sp;
|
|
}
|
|
static __attribute__((always_inline)) void restore_hardirq_stack(void *orig_sp)
|
|
{
|
|
__asm__ __volatile__("mov %0, %%sp" : : "r" (orig_sp));
|
|
}
|
|
|
|
void handler_irq(int irq, struct pt_regs *regs)
|
|
{
|
|
unsigned long pstate, bucket_pa;
|
|
struct pt_regs *old_regs;
|
|
void *orig_sp;
|
|
|
|
clear_softint(1 << irq);
|
|
|
|
old_regs = set_irq_regs(regs);
|
|
irq_enter();
|
|
|
|
/* Grab an atomic snapshot of the pending IVECs. */
|
|
__asm__ __volatile__("rdpr %%pstate, %0\n\t"
|
|
"wrpr %0, %3, %%pstate\n\t"
|
|
"ldx [%2], %1\n\t"
|
|
"stx %%g0, [%2]\n\t"
|
|
"wrpr %0, 0x0, %%pstate\n\t"
|
|
: "=&r" (pstate), "=&r" (bucket_pa)
|
|
: "r" (irq_work_pa(smp_processor_id())),
|
|
"i" (PSTATE_IE)
|
|
: "memory");
|
|
|
|
orig_sp = set_hardirq_stack();
|
|
|
|
while (bucket_pa) {
|
|
struct irq_desc *desc;
|
|
unsigned long next_pa;
|
|
unsigned int virt_irq;
|
|
|
|
next_pa = bucket_get_chain_pa(bucket_pa);
|
|
virt_irq = bucket_get_virt_irq(bucket_pa);
|
|
bucket_clear_chain_pa(bucket_pa);
|
|
|
|
desc = irq_desc + virt_irq;
|
|
|
|
desc->handle_irq(virt_irq, desc);
|
|
|
|
bucket_pa = next_pa;
|
|
}
|
|
|
|
restore_hardirq_stack(orig_sp);
|
|
|
|
irq_exit();
|
|
set_irq_regs(old_regs);
|
|
}
|
|
|
|
void do_softirq(void)
|
|
{
|
|
unsigned long flags;
|
|
|
|
if (in_interrupt())
|
|
return;
|
|
|
|
local_irq_save(flags);
|
|
|
|
if (local_softirq_pending()) {
|
|
void *orig_sp, *sp = softirq_stack[smp_processor_id()];
|
|
|
|
sp += THREAD_SIZE - 192 - STACK_BIAS;
|
|
|
|
__asm__ __volatile__("mov %%sp, %0\n\t"
|
|
"mov %1, %%sp"
|
|
: "=&r" (orig_sp)
|
|
: "r" (sp));
|
|
__do_softirq();
|
|
__asm__ __volatile__("mov %0, %%sp"
|
|
: : "r" (orig_sp));
|
|
}
|
|
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
void fixup_irqs(void)
|
|
{
|
|
unsigned int irq;
|
|
|
|
for (irq = 0; irq < NR_IRQS; irq++) {
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&irq_desc[irq].lock, flags);
|
|
if (irq_desc[irq].action &&
|
|
!(irq_desc[irq].status & IRQ_PER_CPU)) {
|
|
if (irq_desc[irq].chip->set_affinity)
|
|
irq_desc[irq].chip->set_affinity(irq,
|
|
irq_desc[irq].affinity);
|
|
}
|
|
spin_unlock_irqrestore(&irq_desc[irq].lock, flags);
|
|
}
|
|
|
|
tick_ops->disable_irq();
|
|
}
|
|
#endif
|
|
|
|
struct sun5_timer {
|
|
u64 count0;
|
|
u64 limit0;
|
|
u64 count1;
|
|
u64 limit1;
|
|
};
|
|
|
|
static struct sun5_timer *prom_timers;
|
|
static u64 prom_limit0, prom_limit1;
|
|
|
|
static void map_prom_timers(void)
|
|
{
|
|
struct device_node *dp;
|
|
const unsigned int *addr;
|
|
|
|
/* PROM timer node hangs out in the top level of device siblings... */
|
|
dp = of_find_node_by_path("/");
|
|
dp = dp->child;
|
|
while (dp) {
|
|
if (!strcmp(dp->name, "counter-timer"))
|
|
break;
|
|
dp = dp->sibling;
|
|
}
|
|
|
|
/* Assume if node is not present, PROM uses different tick mechanism
|
|
* which we should not care about.
|
|
*/
|
|
if (!dp) {
|
|
prom_timers = (struct sun5_timer *) 0;
|
|
return;
|
|
}
|
|
|
|
/* If PROM is really using this, it must be mapped by him. */
|
|
addr = of_get_property(dp, "address", NULL);
|
|
if (!addr) {
|
|
prom_printf("PROM does not have timer mapped, trying to continue.\n");
|
|
prom_timers = (struct sun5_timer *) 0;
|
|
return;
|
|
}
|
|
prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
|
|
}
|
|
|
|
static void kill_prom_timer(void)
|
|
{
|
|
if (!prom_timers)
|
|
return;
|
|
|
|
/* Save them away for later. */
|
|
prom_limit0 = prom_timers->limit0;
|
|
prom_limit1 = prom_timers->limit1;
|
|
|
|
/* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
|
|
* We turn both off here just to be paranoid.
|
|
*/
|
|
prom_timers->limit0 = 0;
|
|
prom_timers->limit1 = 0;
|
|
|
|
/* Wheee, eat the interrupt packet too... */
|
|
__asm__ __volatile__(
|
|
" mov 0x40, %%g2\n"
|
|
" ldxa [%%g0] %0, %%g1\n"
|
|
" ldxa [%%g2] %1, %%g1\n"
|
|
" stxa %%g0, [%%g0] %0\n"
|
|
" membar #Sync\n"
|
|
: /* no outputs */
|
|
: "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
|
|
: "g1", "g2");
|
|
}
|
|
|
|
void notrace init_irqwork_curcpu(void)
|
|
{
|
|
int cpu = hard_smp_processor_id();
|
|
|
|
trap_block[cpu].irq_worklist_pa = 0UL;
|
|
}
|
|
|
|
/* Please be very careful with register_one_mondo() and
|
|
* sun4v_register_mondo_queues().
|
|
*
|
|
* On SMP this gets invoked from the CPU trampoline before
|
|
* the cpu has fully taken over the trap table from OBP,
|
|
* and it's kernel stack + %g6 thread register state is
|
|
* not fully cooked yet.
|
|
*
|
|
* Therefore you cannot make any OBP calls, not even prom_printf,
|
|
* from these two routines.
|
|
*/
|
|
static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask)
|
|
{
|
|
unsigned long num_entries = (qmask + 1) / 64;
|
|
unsigned long status;
|
|
|
|
status = sun4v_cpu_qconf(type, paddr, num_entries);
|
|
if (status != HV_EOK) {
|
|
prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
|
|
"err %lu\n", type, paddr, num_entries, status);
|
|
prom_halt();
|
|
}
|
|
}
|
|
|
|
void __cpuinit notrace sun4v_register_mondo_queues(int this_cpu)
|
|
{
|
|
struct trap_per_cpu *tb = &trap_block[this_cpu];
|
|
|
|
register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO,
|
|
tb->cpu_mondo_qmask);
|
|
register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO,
|
|
tb->dev_mondo_qmask);
|
|
register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR,
|
|
tb->resum_qmask);
|
|
register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR,
|
|
tb->nonresum_qmask);
|
|
}
|
|
|
|
static void __init alloc_one_mondo(unsigned long *pa_ptr, unsigned long qmask)
|
|
{
|
|
unsigned long size = PAGE_ALIGN(qmask + 1);
|
|
void *p = __alloc_bootmem(size, size, 0);
|
|
if (!p) {
|
|
prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
|
|
prom_halt();
|
|
}
|
|
|
|
*pa_ptr = __pa(p);
|
|
}
|
|
|
|
static void __init alloc_one_kbuf(unsigned long *pa_ptr, unsigned long qmask)
|
|
{
|
|
unsigned long size = PAGE_ALIGN(qmask + 1);
|
|
void *p = __alloc_bootmem(size, size, 0);
|
|
|
|
if (!p) {
|
|
prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
|
|
prom_halt();
|
|
}
|
|
|
|
*pa_ptr = __pa(p);
|
|
}
|
|
|
|
static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb)
|
|
{
|
|
#ifdef CONFIG_SMP
|
|
void *page;
|
|
|
|
BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
|
|
|
|
page = alloc_bootmem_pages(PAGE_SIZE);
|
|
if (!page) {
|
|
prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
|
|
prom_halt();
|
|
}
|
|
|
|
tb->cpu_mondo_block_pa = __pa(page);
|
|
tb->cpu_list_pa = __pa(page + 64);
|
|
#endif
|
|
}
|
|
|
|
/* Allocate mondo and error queues for all possible cpus. */
|
|
static void __init sun4v_init_mondo_queues(void)
|
|
{
|
|
int cpu;
|
|
|
|
for_each_possible_cpu(cpu) {
|
|
struct trap_per_cpu *tb = &trap_block[cpu];
|
|
|
|
alloc_one_mondo(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask);
|
|
alloc_one_mondo(&tb->dev_mondo_pa, tb->dev_mondo_qmask);
|
|
alloc_one_mondo(&tb->resum_mondo_pa, tb->resum_qmask);
|
|
alloc_one_kbuf(&tb->resum_kernel_buf_pa, tb->resum_qmask);
|
|
alloc_one_mondo(&tb->nonresum_mondo_pa, tb->nonresum_qmask);
|
|
alloc_one_kbuf(&tb->nonresum_kernel_buf_pa,
|
|
tb->nonresum_qmask);
|
|
}
|
|
}
|
|
|
|
static void __init init_send_mondo_info(void)
|
|
{
|
|
int cpu;
|
|
|
|
for_each_possible_cpu(cpu) {
|
|
struct trap_per_cpu *tb = &trap_block[cpu];
|
|
|
|
init_cpu_send_mondo_info(tb);
|
|
}
|
|
}
|
|
|
|
static struct irqaction timer_irq_action = {
|
|
.name = "timer",
|
|
};
|
|
|
|
/* Only invoked on boot processor. */
|
|
void __init init_IRQ(void)
|
|
{
|
|
unsigned long size;
|
|
|
|
map_prom_timers();
|
|
kill_prom_timer();
|
|
|
|
size = sizeof(struct ino_bucket) * NUM_IVECS;
|
|
ivector_table = alloc_bootmem(size);
|
|
if (!ivector_table) {
|
|
prom_printf("Fatal error, cannot allocate ivector_table\n");
|
|
prom_halt();
|
|
}
|
|
__flush_dcache_range((unsigned long) ivector_table,
|
|
((unsigned long) ivector_table) + size);
|
|
|
|
ivector_table_pa = __pa(ivector_table);
|
|
|
|
if (tlb_type == hypervisor)
|
|
sun4v_init_mondo_queues();
|
|
|
|
init_send_mondo_info();
|
|
|
|
if (tlb_type == hypervisor) {
|
|
/* Load up the boot cpu's entries. */
|
|
sun4v_register_mondo_queues(hard_smp_processor_id());
|
|
}
|
|
|
|
/* We need to clear any IRQ's pending in the soft interrupt
|
|
* registers, a spurious one could be left around from the
|
|
* PROM timer which we just disabled.
|
|
*/
|
|
clear_softint(get_softint());
|
|
|
|
/* Now that ivector table is initialized, it is safe
|
|
* to receive IRQ vector traps. We will normally take
|
|
* one or two right now, in case some device PROM used
|
|
* to boot us wants to speak to us. We just ignore them.
|
|
*/
|
|
__asm__ __volatile__("rdpr %%pstate, %%g1\n\t"
|
|
"or %%g1, %0, %%g1\n\t"
|
|
"wrpr %%g1, 0x0, %%pstate"
|
|
: /* No outputs */
|
|
: "i" (PSTATE_IE)
|
|
: "g1");
|
|
|
|
irq_desc[0].action = &timer_irq_action;
|
|
}
|