709 строки
20 KiB
C
709 строки
20 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* pata_via.c - VIA PATA for new ATA layer
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* (C) 2005-2006 Red Hat Inc
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*
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* Documentation
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* Most chipset documentation available under NDA only
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*
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* VIA version guide
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* VIA VT82C561 - early design, uses ata_generic currently
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* VIA VT82C576 - MWDMA, 33Mhz
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* VIA VT82C586 - MWDMA, 33Mhz
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* VIA VT82C586a - Added UDMA to 33Mhz
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* VIA VT82C586b - UDMA33
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* VIA VT82C596a - Nonfunctional UDMA66
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* VIA VT82C596b - Working UDMA66
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* VIA VT82C686 - Nonfunctional UDMA66
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* VIA VT82C686a - Working UDMA66
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* VIA VT82C686b - Updated to UDMA100
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* VIA VT8231 - UDMA100
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* VIA VT8233 - UDMA100
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* VIA VT8233a - UDMA133
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* VIA VT8233c - UDMA100
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* VIA VT8235 - UDMA133
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* VIA VT8237 - UDMA133
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* VIA VT8237A - UDMA133
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* VIA VT8237S - UDMA133
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* VIA VT8251 - UDMA133
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*
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* Most registers remain compatible across chips. Others start reserved
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* and acquire sensible semantics if set to 1 (eg cable detect). A few
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* exceptions exist, notably around the FIFO settings.
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*
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* One additional quirk of the VIA design is that like ALi they use few
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* PCI IDs for a lot of chips.
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*
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* Based heavily on:
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*
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* Version 3.38
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*
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* VIA IDE driver for Linux. Supported southbridges:
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*
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* vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
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* vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
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* vt8235, vt8237
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*
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* Copyright (c) 2000-2002 Vojtech Pavlik
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*
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* Based on the work of:
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* Michel Aubry
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* Jeff Garzik
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* Andre Hedrick
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/gfp.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#include <linux/dmi.h>
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#define DRV_NAME "pata_via"
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#define DRV_VERSION "0.3.4"
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enum {
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VIA_BAD_PREQ = 0x01, /* Crashes if PREQ# till DDACK# set */
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VIA_BAD_CLK66 = 0x02, /* 66 MHz clock doesn't work correctly */
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VIA_SET_FIFO = 0x04, /* Needs to have FIFO split set */
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VIA_NO_UNMASK = 0x08, /* Doesn't work with IRQ unmasking on */
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VIA_BAD_ID = 0x10, /* Has wrong vendor ID (0x1107) */
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VIA_BAD_AST = 0x20, /* Don't touch Address Setup Timing */
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VIA_NO_ENABLES = 0x40, /* Has no enablebits */
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VIA_SATA_PATA = 0x80, /* SATA/PATA combined configuration */
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};
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enum {
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VIA_IDFLAG_SINGLE = (1 << 0), /* single channel controller) */
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};
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/*
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* VIA SouthBridge chips.
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*/
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static const struct via_isa_bridge {
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const char *name;
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u16 id;
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u8 rev_min;
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u8 rev_max;
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u8 udma_mask;
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u8 flags;
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} via_isa_bridges[] = {
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{ "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
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{ "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
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{ "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
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{ "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
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{ "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
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{ "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
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{ "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_NO_ENABLES },
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{ "vt6415", PCI_DEVICE_ID_VIA_6415, 0x00, 0xff, ATA_UDMA6, VIA_BAD_AST | VIA_NO_ENABLES },
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{ "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
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{ "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
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{ "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
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{ "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
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{ "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, },
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{ "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, },
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{ "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, },
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{ "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, },
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{ "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, },
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{ "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
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{ "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, },
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{ "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
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{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
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{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ },
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{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
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{ "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
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{ "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO },
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{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK },
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{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
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{ "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
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{ NULL }
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};
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static const struct dmi_system_id no_atapi_dma_dmi_table[] = {
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{
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.ident = "AVERATEC 3200",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "AVERATEC"),
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DMI_MATCH(DMI_BOARD_NAME, "3200"),
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},
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},
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{ }
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};
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struct via_port {
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u8 cached_device;
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};
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/*
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* Cable special cases
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*/
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static const struct dmi_system_id cable_dmi_table[] = {
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{
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.ident = "Acer Ferrari 3400",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
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DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
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},
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},
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{ }
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};
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static int via_cable_override(struct pci_dev *pdev)
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{
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/* Systems by DMI */
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if (dmi_check_system(cable_dmi_table))
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return 1;
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/* Arima W730-K8/Targa Visionary 811/... */
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if (pdev->subsystem_vendor == 0x161F && pdev->subsystem_device == 0x2032)
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return 1;
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return 0;
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}
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/**
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* via_cable_detect - cable detection
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* @ap: ATA port
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*
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* Perform cable detection. Actually for the VIA case the BIOS
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* already did this for us. We read the values provided by the
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* BIOS. If you are using an 8235 in a non-PC configuration you
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* may need to update this code.
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*
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* Hotplug also impacts on this.
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*/
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static int via_cable_detect(struct ata_port *ap) {
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const struct via_isa_bridge *config = ap->host->private_data;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u32 ata66;
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if (via_cable_override(pdev))
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return ATA_CBL_PATA40_SHORT;
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if ((config->flags & VIA_SATA_PATA) && ap->port_no == 0)
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return ATA_CBL_SATA;
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/* Early chips are 40 wire */
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if (config->udma_mask < ATA_UDMA4)
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return ATA_CBL_PATA40;
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/* UDMA 66 chips have only drive side logic */
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else if (config->udma_mask < ATA_UDMA5)
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return ATA_CBL_PATA_UNK;
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/* UDMA 100 or later */
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pci_read_config_dword(pdev, 0x50, &ata66);
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/* Check both the drive cable reporting bits, we might not have
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two drives */
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if (ata66 & (0x10100000 >> (16 * ap->port_no)))
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return ATA_CBL_PATA80;
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/* Check with ACPI so we can spot BIOS reported SATA bridges */
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if (ata_acpi_init_gtm(ap) &&
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ata_acpi_cbl_80wire(ap, ata_acpi_init_gtm(ap)))
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return ATA_CBL_PATA80;
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return ATA_CBL_PATA40;
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}
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static int via_pre_reset(struct ata_link *link, unsigned long deadline)
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{
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struct ata_port *ap = link->ap;
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const struct via_isa_bridge *config = ap->host->private_data;
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if (!(config->flags & VIA_NO_ENABLES)) {
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static const struct pci_bits via_enable_bits[] = {
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{ 0x40, 1, 0x02, 0x02 },
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{ 0x40, 1, 0x01, 0x01 }
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};
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no]))
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return -ENOENT;
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}
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return ata_sff_prereset(link, deadline);
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}
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/**
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* via_do_set_mode - set transfer mode data
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* @ap: ATA interface
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* @adev: ATA device
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* @mode: ATA mode being programmed
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* @set_ast: Set to program address setup
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* @udma_type: UDMA mode/format of registers
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*
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* Program the VIA registers for DMA and PIO modes. Uses the ata timing
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* support in order to compute modes.
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*
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* FIXME: Hotplug will require we serialize multiple mode changes
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* on the two channels.
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*/
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static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev,
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int mode, int set_ast, int udma_type)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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struct ata_device *peer = ata_dev_pair(adev);
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struct ata_timing t, p;
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const int via_clock = 33333; /* Bus clock in kHz */
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const int T = 1000000000 / via_clock;
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int UT = T;
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int ut;
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int offset = 3 - (2*ap->port_no) - adev->devno;
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switch (udma_type) {
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case ATA_UDMA4:
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UT = T / 2; break;
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case ATA_UDMA5:
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UT = T / 3; break;
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case ATA_UDMA6:
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UT = T / 4; break;
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}
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/* Calculate the timing values we require */
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ata_timing_compute(adev, mode, &t, T, UT);
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/* We share 8bit timing so we must merge the constraints */
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if (peer) {
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if (peer->pio_mode) {
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ata_timing_compute(peer, peer->pio_mode, &p, T, UT);
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ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT);
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}
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}
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/* Address setup is programmable but breaks on UDMA133 setups */
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if (set_ast) {
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u8 setup; /* 2 bits per drive */
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int shift = 2 * offset;
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pci_read_config_byte(pdev, 0x4C, &setup);
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setup &= ~(3 << shift);
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setup |= (clamp_val(t.setup, 1, 4) - 1) << shift;
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pci_write_config_byte(pdev, 0x4C, setup);
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}
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/* Load the PIO mode bits */
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pci_write_config_byte(pdev, 0x4F - ap->port_no,
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((clamp_val(t.act8b, 1, 16) - 1) << 4) | (clamp_val(t.rec8b, 1, 16) - 1));
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pci_write_config_byte(pdev, 0x48 + offset,
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((clamp_val(t.active, 1, 16) - 1) << 4) | (clamp_val(t.recover, 1, 16) - 1));
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/* Load the UDMA bits according to type */
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switch (udma_type) {
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case ATA_UDMA2:
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default:
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ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 5) - 2)) : 0x03;
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break;
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case ATA_UDMA4:
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ut = t.udma ? (0xe8 | (clamp_val(t.udma, 2, 9) - 2)) : 0x0f;
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break;
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case ATA_UDMA5:
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ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07;
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break;
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case ATA_UDMA6:
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ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07;
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break;
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}
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/* Set UDMA unless device is not UDMA capable */
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if (udma_type) {
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u8 udma_etc;
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pci_read_config_byte(pdev, 0x50 + offset, &udma_etc);
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/* clear transfer mode bit */
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udma_etc &= ~0x20;
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if (t.udma) {
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/* preserve 80-wire cable detection bit */
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udma_etc &= 0x10;
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udma_etc |= ut;
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}
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pci_write_config_byte(pdev, 0x50 + offset, udma_etc);
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}
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}
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static void via_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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const struct via_isa_bridge *config = ap->host->private_data;
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int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
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via_do_set_mode(ap, adev, adev->pio_mode, set_ast, config->udma_mask);
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}
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static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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const struct via_isa_bridge *config = ap->host->private_data;
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int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
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via_do_set_mode(ap, adev, adev->dma_mode, set_ast, config->udma_mask);
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}
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/**
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* via_mode_filter - filter buggy device/mode pairs
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* @dev: ATA device
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* @mask: Mode bitmask
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*
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* We need to apply some minimal filtering for old controllers and at least
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* one breed of Transcend SSD. Return the updated mask.
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*/
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static unsigned int via_mode_filter(struct ata_device *dev, unsigned int mask)
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{
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struct ata_host *host = dev->link->ap->host;
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const struct via_isa_bridge *config = host->private_data;
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unsigned char model_num[ATA_ID_PROD_LEN + 1];
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if (config->id == PCI_DEVICE_ID_VIA_82C586_0) {
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ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
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if (strcmp(model_num, "TS64GSSD25-M") == 0) {
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ata_dev_warn(dev,
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"disabling UDMA mode due to reported lockups with this device\n");
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mask &= ~ ATA_MASK_UDMA;
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}
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}
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if (dev->class == ATA_DEV_ATAPI &&
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dmi_check_system(no_atapi_dma_dmi_table)) {
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ata_dev_warn(dev, "controller locks up on ATAPI DMA, forcing PIO\n");
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mask &= ATA_MASK_PIO;
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}
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return mask;
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}
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/**
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* via_tf_load - send taskfile registers to host controller
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* @ap: Port to which output is sent
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* @tf: ATA taskfile register set
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*
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* Outputs ATA taskfile to standard ATA host controller.
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*
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* Note: This is to fix the internal bug of via chipsets, which
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* will reset the device register after changing the IEN bit on
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* ctl register
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*/
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static void via_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
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{
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struct ata_ioports *ioaddr = &ap->ioaddr;
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struct via_port *vp = ap->private_data;
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unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
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int newctl = 0;
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if (tf->ctl != ap->last_ctl) {
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iowrite8(tf->ctl, ioaddr->ctl_addr);
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ap->last_ctl = tf->ctl;
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ata_wait_idle(ap);
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newctl = 1;
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}
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if (tf->flags & ATA_TFLAG_DEVICE) {
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iowrite8(tf->device, ioaddr->device_addr);
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vp->cached_device = tf->device;
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} else if (newctl)
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iowrite8(vp->cached_device, ioaddr->device_addr);
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if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
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WARN_ON_ONCE(!ioaddr->ctl_addr);
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iowrite8(tf->hob_feature, ioaddr->feature_addr);
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iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
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iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
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iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
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iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
|
|
}
|
|
|
|
if (is_addr) {
|
|
iowrite8(tf->feature, ioaddr->feature_addr);
|
|
iowrite8(tf->nsect, ioaddr->nsect_addr);
|
|
iowrite8(tf->lbal, ioaddr->lbal_addr);
|
|
iowrite8(tf->lbam, ioaddr->lbam_addr);
|
|
iowrite8(tf->lbah, ioaddr->lbah_addr);
|
|
}
|
|
|
|
ata_wait_idle(ap);
|
|
}
|
|
|
|
static int via_port_start(struct ata_port *ap)
|
|
{
|
|
struct via_port *vp;
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
|
|
|
int ret = ata_bmdma_port_start(ap);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
vp = devm_kzalloc(&pdev->dev, sizeof(struct via_port), GFP_KERNEL);
|
|
if (vp == NULL)
|
|
return -ENOMEM;
|
|
ap->private_data = vp;
|
|
return 0;
|
|
}
|
|
|
|
static const struct scsi_host_template via_sht = {
|
|
ATA_BMDMA_SHT(DRV_NAME),
|
|
};
|
|
|
|
static struct ata_port_operations via_port_ops = {
|
|
.inherits = &ata_bmdma_port_ops,
|
|
.cable_detect = via_cable_detect,
|
|
.set_piomode = via_set_piomode,
|
|
.set_dmamode = via_set_dmamode,
|
|
.prereset = via_pre_reset,
|
|
.sff_tf_load = via_tf_load,
|
|
.port_start = via_port_start,
|
|
.mode_filter = via_mode_filter,
|
|
};
|
|
|
|
static struct ata_port_operations via_port_ops_noirq = {
|
|
.inherits = &via_port_ops,
|
|
.sff_data_xfer = ata_sff_data_xfer32,
|
|
};
|
|
|
|
/**
|
|
* via_config_fifo - set up the FIFO
|
|
* @pdev: PCI device
|
|
* @flags: configuration flags
|
|
*
|
|
* Set the FIFO properties for this device if necessary. Used both on
|
|
* set up and on and the resume path
|
|
*/
|
|
|
|
static void via_config_fifo(struct pci_dev *pdev, unsigned int flags)
|
|
{
|
|
u8 enable;
|
|
|
|
/* 0x40 low bits indicate enabled channels */
|
|
pci_read_config_byte(pdev, 0x40 , &enable);
|
|
enable &= 3;
|
|
|
|
if (flags & VIA_SET_FIFO) {
|
|
static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20};
|
|
u8 fifo;
|
|
|
|
pci_read_config_byte(pdev, 0x43, &fifo);
|
|
|
|
/* Clear PREQ# until DDACK# for errata */
|
|
if (flags & VIA_BAD_PREQ)
|
|
fifo &= 0x7F;
|
|
else
|
|
fifo &= 0x9f;
|
|
/* Turn on FIFO for enabled channels */
|
|
fifo |= fifo_setting[enable];
|
|
pci_write_config_byte(pdev, 0x43, fifo);
|
|
}
|
|
}
|
|
|
|
static void via_fixup(struct pci_dev *pdev, const struct via_isa_bridge *config)
|
|
{
|
|
u32 timing;
|
|
|
|
/* Initialise the FIFO for the enabled channels. */
|
|
via_config_fifo(pdev, config->flags);
|
|
|
|
if (config->udma_mask == ATA_UDMA4) {
|
|
/* The 66 MHz devices require we enable the clock */
|
|
pci_read_config_dword(pdev, 0x50, &timing);
|
|
timing |= 0x80008;
|
|
pci_write_config_dword(pdev, 0x50, timing);
|
|
}
|
|
if (config->flags & VIA_BAD_CLK66) {
|
|
/* Disable the 66MHz clock on problem devices */
|
|
pci_read_config_dword(pdev, 0x50, &timing);
|
|
timing &= ~0x80008;
|
|
pci_write_config_dword(pdev, 0x50, timing);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* via_init_one - discovery callback
|
|
* @pdev: PCI device
|
|
* @id: PCI table info
|
|
*
|
|
* A VIA IDE interface has been discovered. Figure out what revision
|
|
* and perform configuration work before handing it to the ATA layer
|
|
*/
|
|
|
|
static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
|
|
{
|
|
/* Early VIA without UDMA support */
|
|
static const struct ata_port_info via_mwdma_info = {
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
.port_ops = &via_port_ops
|
|
};
|
|
/* Ditto with IRQ masking required */
|
|
static const struct ata_port_info via_mwdma_info_borked = {
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
.port_ops = &via_port_ops_noirq,
|
|
};
|
|
/* VIA UDMA 33 devices (and borked 66) */
|
|
static const struct ata_port_info via_udma33_info = {
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
.udma_mask = ATA_UDMA2,
|
|
.port_ops = &via_port_ops
|
|
};
|
|
/* VIA UDMA 66 devices */
|
|
static const struct ata_port_info via_udma66_info = {
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
.udma_mask = ATA_UDMA4,
|
|
.port_ops = &via_port_ops
|
|
};
|
|
/* VIA UDMA 100 devices */
|
|
static const struct ata_port_info via_udma100_info = {
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
.udma_mask = ATA_UDMA5,
|
|
.port_ops = &via_port_ops
|
|
};
|
|
/* UDMA133 with bad AST (All current 133) */
|
|
static const struct ata_port_info via_udma133_info = {
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
.udma_mask = ATA_UDMA6, /* FIXME: should check north bridge */
|
|
.port_ops = &via_port_ops
|
|
};
|
|
const struct ata_port_info *ppi[] = { NULL, NULL };
|
|
struct pci_dev *isa;
|
|
const struct via_isa_bridge *config;
|
|
u8 enable;
|
|
unsigned long flags = id->driver_data;
|
|
int rc;
|
|
|
|
ata_print_version_once(&pdev->dev, DRV_VERSION);
|
|
|
|
rc = pcim_enable_device(pdev);
|
|
if (rc)
|
|
return rc;
|
|
|
|
if (flags & VIA_IDFLAG_SINGLE)
|
|
ppi[1] = &ata_dummy_port_info;
|
|
|
|
/* To find out how the IDE will behave and what features we
|
|
actually have to look at the bridge not the IDE controller */
|
|
for (config = via_isa_bridges; config->id != PCI_DEVICE_ID_VIA_ANON;
|
|
config++)
|
|
if ((isa = pci_get_device(PCI_VENDOR_ID_VIA +
|
|
!!(config->flags & VIA_BAD_ID),
|
|
config->id, NULL))) {
|
|
u8 rev = isa->revision;
|
|
pci_dev_put(isa);
|
|
|
|
if ((id->device == 0x0415 || id->device == 0x3164) &&
|
|
(config->id != id->device))
|
|
continue;
|
|
|
|
if (rev >= config->rev_min && rev <= config->rev_max)
|
|
break;
|
|
}
|
|
|
|
if (!(config->flags & VIA_NO_ENABLES)) {
|
|
/* 0x40 low bits indicate enabled channels */
|
|
pci_read_config_byte(pdev, 0x40 , &enable);
|
|
enable &= 3;
|
|
if (enable == 0)
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* Clock set up */
|
|
switch (config->udma_mask) {
|
|
case 0x00:
|
|
if (config->flags & VIA_NO_UNMASK)
|
|
ppi[0] = &via_mwdma_info_borked;
|
|
else
|
|
ppi[0] = &via_mwdma_info;
|
|
break;
|
|
case ATA_UDMA2:
|
|
ppi[0] = &via_udma33_info;
|
|
break;
|
|
case ATA_UDMA4:
|
|
ppi[0] = &via_udma66_info;
|
|
break;
|
|
case ATA_UDMA5:
|
|
ppi[0] = &via_udma100_info;
|
|
break;
|
|
case ATA_UDMA6:
|
|
ppi[0] = &via_udma133_info;
|
|
break;
|
|
default:
|
|
WARN_ON(1);
|
|
return -ENODEV;
|
|
}
|
|
|
|
via_fixup(pdev, config);
|
|
|
|
/* We have established the device type, now fire it up */
|
|
return ata_pci_bmdma_init_one(pdev, ppi, &via_sht, (void *)config, 0);
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
/**
|
|
* via_reinit_one - reinit after resume
|
|
* @pdev: PCI device
|
|
*
|
|
* Called when the VIA PATA device is resumed. We must then
|
|
* reconfigure the fifo and other setup we may have altered. In
|
|
* addition the kernel needs to have the resume methods on PCI
|
|
* quirk supported.
|
|
*/
|
|
|
|
static int via_reinit_one(struct pci_dev *pdev)
|
|
{
|
|
struct ata_host *host = pci_get_drvdata(pdev);
|
|
int rc;
|
|
|
|
rc = ata_pci_device_do_resume(pdev);
|
|
if (rc)
|
|
return rc;
|
|
|
|
via_fixup(pdev, host->private_data);
|
|
|
|
ata_host_resume(host);
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static const struct pci_device_id via[] = {
|
|
{ PCI_VDEVICE(VIA, 0x0415), },
|
|
{ PCI_VDEVICE(VIA, 0x0571), },
|
|
{ PCI_VDEVICE(VIA, 0x0581), },
|
|
{ PCI_VDEVICE(VIA, 0x1571), },
|
|
{ PCI_VDEVICE(VIA, 0x3164), },
|
|
{ PCI_VDEVICE(VIA, 0x5324), },
|
|
{ PCI_VDEVICE(VIA, 0xC409), VIA_IDFLAG_SINGLE },
|
|
{ PCI_VDEVICE(VIA, 0x9001), VIA_IDFLAG_SINGLE },
|
|
|
|
{ },
|
|
};
|
|
|
|
static struct pci_driver via_pci_driver = {
|
|
.name = DRV_NAME,
|
|
.id_table = via,
|
|
.probe = via_init_one,
|
|
.remove = ata_pci_remove_one,
|
|
#ifdef CONFIG_PM_SLEEP
|
|
.suspend = ata_pci_device_suspend,
|
|
.resume = via_reinit_one,
|
|
#endif
|
|
};
|
|
|
|
module_pci_driver(via_pci_driver);
|
|
|
|
MODULE_AUTHOR("Alan Cox");
|
|
MODULE_DESCRIPTION("low-level driver for VIA PATA");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DEVICE_TABLE(pci, via);
|
|
MODULE_VERSION(DRV_VERSION);
|