824 строки
24 KiB
C
824 строки
24 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Cadence SPI controller driver (host and target mode)
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*
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* Copyright (C) 2008 - 2014 Xilinx, Inc.
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*
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* based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/spi/spi.h>
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/* Name of this driver */
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#define CDNS_SPI_NAME "cdns-spi"
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/* Register offset definitions */
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#define CDNS_SPI_CR 0x00 /* Configuration Register, RW */
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#define CDNS_SPI_ISR 0x04 /* Interrupt Status Register, RO */
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#define CDNS_SPI_IER 0x08 /* Interrupt Enable Register, WO */
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#define CDNS_SPI_IDR 0x0c /* Interrupt Disable Register, WO */
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#define CDNS_SPI_IMR 0x10 /* Interrupt Enabled Mask Register, RO */
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#define CDNS_SPI_ER 0x14 /* Enable/Disable Register, RW */
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#define CDNS_SPI_DR 0x18 /* Delay Register, RW */
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#define CDNS_SPI_TXD 0x1C /* Data Transmit Register, WO */
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#define CDNS_SPI_RXD 0x20 /* Data Receive Register, RO */
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#define CDNS_SPI_SICR 0x24 /* Slave Idle Count Register, RW */
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#define CDNS_SPI_THLD 0x28 /* Transmit FIFO Watermark Register,RW */
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#define SPI_AUTOSUSPEND_TIMEOUT 3000
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/*
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* SPI Configuration Register bit Masks
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*
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* This register contains various control bits that affect the operation
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* of the SPI controller
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*/
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#define CDNS_SPI_CR_MANSTRT 0x00010000 /* Manual TX Start */
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#define CDNS_SPI_CR_CPHA 0x00000004 /* Clock Phase Control */
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#define CDNS_SPI_CR_CPOL 0x00000002 /* Clock Polarity Control */
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#define CDNS_SPI_CR_SSCTRL 0x00003C00 /* Slave Select Mask */
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#define CDNS_SPI_CR_PERI_SEL 0x00000200 /* Peripheral Select Decode */
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#define CDNS_SPI_CR_BAUD_DIV 0x00000038 /* Baud Rate Divisor Mask */
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#define CDNS_SPI_CR_MSTREN 0x00000001 /* Master Enable Mask */
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#define CDNS_SPI_CR_MANSTRTEN 0x00008000 /* Manual TX Enable Mask */
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#define CDNS_SPI_CR_SSFORCE 0x00004000 /* Manual SS Enable Mask */
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#define CDNS_SPI_CR_BAUD_DIV_4 0x00000008 /* Default Baud Div Mask */
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#define CDNS_SPI_CR_DEFAULT (CDNS_SPI_CR_MSTREN | \
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CDNS_SPI_CR_SSCTRL | \
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CDNS_SPI_CR_SSFORCE | \
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CDNS_SPI_CR_BAUD_DIV_4)
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/*
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* SPI Configuration Register - Baud rate and target select
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*
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* These are the values used in the calculation of baud rate divisor and
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* setting the target select.
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*/
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#define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
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#define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */
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#define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */
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#define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */
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#define CDNS_SPI_SS0 0x1 /* Slave Select zero */
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#define CDNS_SPI_NOSS 0xF /* No Slave select */
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/*
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* SPI Interrupt Registers bit Masks
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*
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* All the four interrupt registers (Status/Mask/Enable/Disable) have the same
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* bit definitions.
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*/
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#define CDNS_SPI_IXR_TXOW 0x00000004 /* SPI TX FIFO Overwater */
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#define CDNS_SPI_IXR_MODF 0x00000002 /* SPI Mode Fault */
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#define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
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#define CDNS_SPI_IXR_DEFAULT (CDNS_SPI_IXR_TXOW | \
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CDNS_SPI_IXR_MODF)
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#define CDNS_SPI_IXR_TXFULL 0x00000008 /* SPI TX Full */
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#define CDNS_SPI_IXR_ALL 0x0000007F /* SPI all interrupts */
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/*
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* SPI Enable Register bit Masks
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*
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* This register is used to enable or disable the SPI controller
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*/
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#define CDNS_SPI_ER_ENABLE 0x00000001 /* SPI Enable Bit Mask */
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#define CDNS_SPI_ER_DISABLE 0x0 /* SPI Disable Bit Mask */
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/* Default number of chip select lines */
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#define CDNS_SPI_DEFAULT_NUM_CS 4
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/**
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* struct cdns_spi - This definition defines spi driver instance
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* @regs: Virtual address of the SPI controller registers
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* @ref_clk: Pointer to the peripheral clock
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* @pclk: Pointer to the APB clock
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* @clk_rate: Reference clock frequency, taken from @ref_clk
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* @speed_hz: Current SPI bus clock speed in Hz
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* @txbuf: Pointer to the TX buffer
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* @rxbuf: Pointer to the RX buffer
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* @tx_bytes: Number of bytes left to transfer
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* @rx_bytes: Number of bytes requested
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* @dev_busy: Device busy flag
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* @is_decoded_cs: Flag for decoder property set or not
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* @tx_fifo_depth: Depth of the TX FIFO
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*/
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struct cdns_spi {
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void __iomem *regs;
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struct clk *ref_clk;
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struct clk *pclk;
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unsigned int clk_rate;
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u32 speed_hz;
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const u8 *txbuf;
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u8 *rxbuf;
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int tx_bytes;
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int rx_bytes;
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u8 dev_busy;
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u32 is_decoded_cs;
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unsigned int tx_fifo_depth;
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};
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/* Macros for the SPI controller read/write */
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static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
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{
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return readl_relaxed(xspi->regs + offset);
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}
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static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
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{
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writel_relaxed(val, xspi->regs + offset);
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}
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/**
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* cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
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* @xspi: Pointer to the cdns_spi structure
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* @is_target: Flag to indicate target or host mode
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* * On reset the SPI controller is configured to target or host mode.
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* In host mode baud rate divisor is set to 4, threshold value for TX FIFO
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* not full interrupt is set to 1 and size of the word to be transferred as 8 bit.
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*
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* This function initializes the SPI controller to disable and clear all the
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* interrupts, enable manual target select and manual start, deselect all the
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* chip select lines, and enable the SPI controller.
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*/
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static void cdns_spi_init_hw(struct cdns_spi *xspi, bool is_target)
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{
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u32 ctrl_reg = 0;
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if (!is_target)
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ctrl_reg |= CDNS_SPI_CR_DEFAULT;
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if (xspi->is_decoded_cs)
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ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
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cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
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cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL);
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/* Clear the RX FIFO */
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while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY)
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cdns_spi_read(xspi, CDNS_SPI_RXD);
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cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL);
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cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
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cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
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}
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/**
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* cdns_spi_chipselect - Select or deselect the chip select line
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* @spi: Pointer to the spi_device structure
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* @is_high: Select(0) or deselect (1) the chip select line
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*/
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static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
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{
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struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
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u32 ctrl_reg;
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ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
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if (is_high) {
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/* Deselect the target */
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ctrl_reg |= CDNS_SPI_CR_SSCTRL;
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} else {
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/* Select the target */
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ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
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if (!(xspi->is_decoded_cs))
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ctrl_reg |= ((~(CDNS_SPI_SS0 << spi_get_chipselect(spi, 0))) <<
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CDNS_SPI_SS_SHIFT) &
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CDNS_SPI_CR_SSCTRL;
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else
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ctrl_reg |= (spi_get_chipselect(spi, 0) << CDNS_SPI_SS_SHIFT) &
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CDNS_SPI_CR_SSCTRL;
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}
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cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
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}
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/**
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* cdns_spi_config_clock_mode - Sets clock polarity and phase
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* @spi: Pointer to the spi_device structure
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*
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* Sets the requested clock polarity and phase.
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*/
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static void cdns_spi_config_clock_mode(struct spi_device *spi)
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{
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struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
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u32 ctrl_reg, new_ctrl_reg;
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new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
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ctrl_reg = new_ctrl_reg;
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/* Set the SPI clock phase and clock polarity */
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new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL);
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if (spi->mode & SPI_CPHA)
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new_ctrl_reg |= CDNS_SPI_CR_CPHA;
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if (spi->mode & SPI_CPOL)
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new_ctrl_reg |= CDNS_SPI_CR_CPOL;
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if (new_ctrl_reg != ctrl_reg) {
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/*
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* Just writing the CR register does not seem to apply the clock
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* setting changes. This is problematic when changing the clock
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* polarity as it will cause the SPI target to see spurious clock
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* transitions. To workaround the issue toggle the ER register.
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*/
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cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
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cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg);
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cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
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}
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}
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/**
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* cdns_spi_config_clock_freq - Sets clock frequency
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* @spi: Pointer to the spi_device structure
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* @transfer: Pointer to the spi_transfer structure which provides
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* information about next transfer setup parameters
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*
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* Sets the requested clock frequency.
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* Note: If the requested frequency is not an exact match with what can be
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* obtained using the prescalar value the driver sets the clock frequency which
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* is lower than the requested frequency (maximum lower) for the transfer. If
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* the requested frequency is higher or lower than that is supported by the SPI
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* controller the driver will set the highest or lowest frequency supported by
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* controller.
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*/
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static void cdns_spi_config_clock_freq(struct spi_device *spi,
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struct spi_transfer *transfer)
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{
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struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
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u32 ctrl_reg, baud_rate_val;
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unsigned long frequency;
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frequency = xspi->clk_rate;
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ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
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/* Set the clock frequency */
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if (xspi->speed_hz != transfer->speed_hz) {
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/* first valid value is 1 */
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baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
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while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
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(frequency / (2 << baud_rate_val)) > transfer->speed_hz)
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baud_rate_val++;
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ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;
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ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
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xspi->speed_hz = frequency / (2 << baud_rate_val);
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}
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cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
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}
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/**
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* cdns_spi_setup_transfer - Configure SPI controller for specified transfer
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* @spi: Pointer to the spi_device structure
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* @transfer: Pointer to the spi_transfer structure which provides
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* information about next transfer setup parameters
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*
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* Sets the operational mode of SPI controller for the next SPI transfer and
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* sets the requested clock frequency.
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*
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* Return: Always 0
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*/
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static int cdns_spi_setup_transfer(struct spi_device *spi,
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struct spi_transfer *transfer)
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{
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struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
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cdns_spi_config_clock_freq(spi, transfer);
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dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
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__func__, spi->mode, spi->bits_per_word,
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xspi->speed_hz);
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return 0;
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}
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/**
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* cdns_spi_process_fifo - Fills the TX FIFO, and drain the RX FIFO
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* @xspi: Pointer to the cdns_spi structure
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* @ntx: Number of bytes to pack into the TX FIFO
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* @nrx: Number of bytes to drain from the RX FIFO
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*/
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static void cdns_spi_process_fifo(struct cdns_spi *xspi, int ntx, int nrx)
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{
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ntx = clamp(ntx, 0, xspi->tx_bytes);
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nrx = clamp(nrx, 0, xspi->rx_bytes);
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xspi->tx_bytes -= ntx;
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xspi->rx_bytes -= nrx;
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while (ntx || nrx) {
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if (ntx) {
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if (xspi->txbuf)
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cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
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else
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cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
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ntx--;
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}
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if (nrx) {
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u8 data = cdns_spi_read(xspi, CDNS_SPI_RXD);
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if (xspi->rxbuf)
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*xspi->rxbuf++ = data;
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nrx--;
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}
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}
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}
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/**
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* cdns_spi_irq - Interrupt service routine of the SPI controller
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* @irq: IRQ number
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* @dev_id: Pointer to the xspi structure
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*
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* This function handles TX empty and Mode Fault interrupts only.
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* On TX empty interrupt this function reads the received data from RX FIFO and
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* fills the TX FIFO if there is any data remaining to be transferred.
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* On Mode Fault interrupt this function indicates that transfer is completed,
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* the SPI subsystem will identify the error as the remaining bytes to be
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* transferred is non-zero.
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*
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* Return: IRQ_HANDLED when handled; IRQ_NONE otherwise.
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*/
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static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
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{
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struct spi_controller *ctlr = dev_id;
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struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
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irqreturn_t status;
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u32 intr_status;
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status = IRQ_NONE;
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intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
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cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
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if (intr_status & CDNS_SPI_IXR_MODF) {
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/* Indicate that transfer is completed, the SPI subsystem will
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* identify the error as the remaining bytes to be
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* transferred is non-zero
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*/
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cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT);
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spi_finalize_current_transfer(ctlr);
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status = IRQ_HANDLED;
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} else if (intr_status & CDNS_SPI_IXR_TXOW) {
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int threshold = cdns_spi_read(xspi, CDNS_SPI_THLD);
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int trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
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if (threshold > 1)
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trans_cnt -= threshold;
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/* Set threshold to one if number of pending are
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* less than half fifo
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*/
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if (xspi->tx_bytes < xspi->tx_fifo_depth >> 1)
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cdns_spi_write(xspi, CDNS_SPI_THLD, 1);
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if (xspi->tx_bytes) {
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cdns_spi_process_fifo(xspi, trans_cnt, trans_cnt);
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} else {
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/* Fixed delay due to controller limitation with
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* RX_NEMPTY incorrect status
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* Xilinx AR:65885 contains more details
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*/
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udelay(10);
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cdns_spi_process_fifo(xspi, 0, trans_cnt);
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cdns_spi_write(xspi, CDNS_SPI_IDR,
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CDNS_SPI_IXR_DEFAULT);
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spi_finalize_current_transfer(ctlr);
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}
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status = IRQ_HANDLED;
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}
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return status;
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}
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static int cdns_prepare_message(struct spi_controller *ctlr,
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struct spi_message *msg)
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{
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if (!spi_controller_is_target(ctlr))
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cdns_spi_config_clock_mode(msg->spi);
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return 0;
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}
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/**
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* cdns_transfer_one - Initiates the SPI transfer
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* @ctlr: Pointer to spi_controller structure
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* @spi: Pointer to the spi_device structure
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* @transfer: Pointer to the spi_transfer structure which provides
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* information about next transfer parameters
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*
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* This function in host mode fills the TX FIFO, starts the SPI transfer and
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* returns a positive transfer count so that core will wait for completion.
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* This function in target mode fills the TX FIFO and wait for transfer trigger.
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*
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* Return: Number of bytes transferred in the last transfer
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*/
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static int cdns_transfer_one(struct spi_controller *ctlr,
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struct spi_device *spi,
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struct spi_transfer *transfer)
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{
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struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
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xspi->txbuf = transfer->tx_buf;
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xspi->rxbuf = transfer->rx_buf;
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xspi->tx_bytes = transfer->len;
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xspi->rx_bytes = transfer->len;
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if (!spi_controller_is_target(ctlr)) {
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cdns_spi_setup_transfer(spi, transfer);
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} else {
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/* Set TX empty threshold to half of FIFO depth
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* only if TX bytes are more than FIFO depth.
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*/
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if (xspi->tx_bytes > xspi->tx_fifo_depth)
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cdns_spi_write(xspi, CDNS_SPI_THLD, xspi->tx_fifo_depth >> 1);
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}
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/* When xspi in busy condition, bytes may send failed,
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* then spi control didn't work thoroughly, add one byte delay
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*/
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if (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_TXFULL)
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udelay(10);
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cdns_spi_process_fifo(xspi, xspi->tx_fifo_depth, 0);
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spi_transfer_delay_exec(transfer);
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|
|
cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT);
|
|
return transfer->len;
|
|
}
|
|
|
|
/**
|
|
* cdns_prepare_transfer_hardware - Prepares hardware for transfer.
|
|
* @ctlr: Pointer to the spi_controller structure which provides
|
|
* information about the controller.
|
|
*
|
|
* This function enables SPI host controller.
|
|
*
|
|
* Return: 0 always
|
|
*/
|
|
static int cdns_prepare_transfer_hardware(struct spi_controller *ctlr)
|
|
{
|
|
struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
|
|
|
|
cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
|
|
* @ctlr: Pointer to the spi_controller structure which provides
|
|
* information about the controller.
|
|
*
|
|
* This function disables the SPI host controller when no target selected.
|
|
* This function flush out if any pending data in FIFO.
|
|
*
|
|
* Return: 0 always
|
|
*/
|
|
static int cdns_unprepare_transfer_hardware(struct spi_controller *ctlr)
|
|
{
|
|
struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
|
|
u32 ctrl_reg;
|
|
unsigned int cnt = xspi->tx_fifo_depth;
|
|
|
|
if (spi_controller_is_target(ctlr)) {
|
|
while (cnt--)
|
|
cdns_spi_read(xspi, CDNS_SPI_RXD);
|
|
}
|
|
|
|
/* Disable the SPI if target is deselected */
|
|
ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
|
|
ctrl_reg = (ctrl_reg & CDNS_SPI_CR_SSCTRL) >> CDNS_SPI_SS_SHIFT;
|
|
if (ctrl_reg == CDNS_SPI_NOSS || spi_controller_is_target(ctlr))
|
|
cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
|
|
|
|
/* Reset to default */
|
|
cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* cdns_spi_detect_fifo_depth - Detect the FIFO depth of the hardware
|
|
* @xspi: Pointer to the cdns_spi structure
|
|
*
|
|
* The depth of the TX FIFO is a synthesis configuration parameter of the SPI
|
|
* IP. The FIFO threshold register is sized so that its maximum value can be the
|
|
* FIFO size - 1. This is used to detect the size of the FIFO.
|
|
*/
|
|
static void cdns_spi_detect_fifo_depth(struct cdns_spi *xspi)
|
|
{
|
|
/* The MSBs will get truncated giving us the size of the FIFO */
|
|
cdns_spi_write(xspi, CDNS_SPI_THLD, 0xffff);
|
|
xspi->tx_fifo_depth = cdns_spi_read(xspi, CDNS_SPI_THLD) + 1;
|
|
|
|
/* Reset to default */
|
|
cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
|
|
}
|
|
|
|
/**
|
|
* cdns_target_abort - Abort target transfer
|
|
* @ctlr: Pointer to the spi_controller structure
|
|
*
|
|
* This function abort target transfer if there any transfer timeout.
|
|
*
|
|
* Return: 0 always
|
|
*/
|
|
static int cdns_target_abort(struct spi_controller *ctlr)
|
|
{
|
|
struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
|
|
u32 intr_status;
|
|
|
|
intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
|
|
cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
|
|
cdns_spi_write(xspi, CDNS_SPI_IDR, (CDNS_SPI_IXR_MODF | CDNS_SPI_IXR_RXNEMTY));
|
|
spi_finalize_current_transfer(ctlr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* cdns_spi_probe - Probe method for the SPI driver
|
|
* @pdev: Pointer to the platform_device structure
|
|
*
|
|
* This function initializes the driver data structures and the hardware.
|
|
*
|
|
* Return: 0 on success and error value on error
|
|
*/
|
|
static int cdns_spi_probe(struct platform_device *pdev)
|
|
{
|
|
int ret = 0, irq;
|
|
struct spi_controller *ctlr;
|
|
struct cdns_spi *xspi;
|
|
u32 num_cs;
|
|
bool target;
|
|
|
|
target = of_property_read_bool(pdev->dev.of_node, "spi-slave");
|
|
if (target)
|
|
ctlr = spi_alloc_target(&pdev->dev, sizeof(*xspi));
|
|
else
|
|
ctlr = spi_alloc_host(&pdev->dev, sizeof(*xspi));
|
|
|
|
if (!ctlr)
|
|
return -ENOMEM;
|
|
|
|
xspi = spi_controller_get_devdata(ctlr);
|
|
ctlr->dev.of_node = pdev->dev.of_node;
|
|
platform_set_drvdata(pdev, ctlr);
|
|
|
|
xspi->regs = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(xspi->regs)) {
|
|
ret = PTR_ERR(xspi->regs);
|
|
goto remove_ctlr;
|
|
}
|
|
|
|
xspi->pclk = devm_clk_get(&pdev->dev, "pclk");
|
|
if (IS_ERR(xspi->pclk)) {
|
|
dev_err(&pdev->dev, "pclk clock not found.\n");
|
|
ret = PTR_ERR(xspi->pclk);
|
|
goto remove_ctlr;
|
|
}
|
|
|
|
ret = clk_prepare_enable(xspi->pclk);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Unable to enable APB clock.\n");
|
|
goto remove_ctlr;
|
|
}
|
|
|
|
if (!spi_controller_is_target(ctlr)) {
|
|
xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
|
|
if (IS_ERR(xspi->ref_clk)) {
|
|
dev_err(&pdev->dev, "ref_clk clock not found.\n");
|
|
ret = PTR_ERR(xspi->ref_clk);
|
|
goto clk_dis_apb;
|
|
}
|
|
|
|
ret = clk_prepare_enable(xspi->ref_clk);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Unable to enable device clock.\n");
|
|
goto clk_dis_apb;
|
|
}
|
|
|
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
|
|
pm_runtime_get_noresume(&pdev->dev);
|
|
pm_runtime_set_active(&pdev->dev);
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
|
|
if (ret < 0)
|
|
ctlr->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
|
|
else
|
|
ctlr->num_chipselect = num_cs;
|
|
|
|
ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
|
|
&xspi->is_decoded_cs);
|
|
if (ret < 0)
|
|
xspi->is_decoded_cs = 0;
|
|
}
|
|
|
|
cdns_spi_detect_fifo_depth(xspi);
|
|
|
|
/* SPI controller initializations */
|
|
cdns_spi_init_hw(xspi, spi_controller_is_target(ctlr));
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
ret = irq;
|
|
goto clk_dis_all;
|
|
}
|
|
|
|
ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
|
|
0, pdev->name, ctlr);
|
|
if (ret != 0) {
|
|
ret = -ENXIO;
|
|
dev_err(&pdev->dev, "request_irq failed\n");
|
|
goto clk_dis_all;
|
|
}
|
|
|
|
ctlr->use_gpio_descriptors = true;
|
|
ctlr->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
|
|
ctlr->prepare_message = cdns_prepare_message;
|
|
ctlr->transfer_one = cdns_transfer_one;
|
|
ctlr->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
|
|
ctlr->mode_bits = SPI_CPOL | SPI_CPHA;
|
|
ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
|
|
|
|
if (!spi_controller_is_target(ctlr)) {
|
|
ctlr->mode_bits |= SPI_CS_HIGH;
|
|
ctlr->set_cs = cdns_spi_chipselect;
|
|
ctlr->auto_runtime_pm = true;
|
|
xspi->clk_rate = clk_get_rate(xspi->ref_clk);
|
|
/* Set to default valid value */
|
|
ctlr->max_speed_hz = xspi->clk_rate / 4;
|
|
xspi->speed_hz = ctlr->max_speed_hz;
|
|
pm_runtime_mark_last_busy(&pdev->dev);
|
|
pm_runtime_put_autosuspend(&pdev->dev);
|
|
} else {
|
|
ctlr->mode_bits |= SPI_NO_CS;
|
|
ctlr->target_abort = cdns_target_abort;
|
|
}
|
|
ret = spi_register_controller(ctlr);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "spi_register_controller failed\n");
|
|
goto clk_dis_all;
|
|
}
|
|
|
|
return ret;
|
|
|
|
clk_dis_all:
|
|
if (!spi_controller_is_target(ctlr)) {
|
|
pm_runtime_set_suspended(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
clk_disable_unprepare(xspi->ref_clk);
|
|
}
|
|
clk_dis_apb:
|
|
clk_disable_unprepare(xspi->pclk);
|
|
remove_ctlr:
|
|
spi_controller_put(ctlr);
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* cdns_spi_remove - Remove method for the SPI driver
|
|
* @pdev: Pointer to the platform_device structure
|
|
*
|
|
* This function is called if a device is physically removed from the system or
|
|
* if the driver module is being unloaded. It frees all resources allocated to
|
|
* the device.
|
|
*/
|
|
static void cdns_spi_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_controller *ctlr = platform_get_drvdata(pdev);
|
|
struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
|
|
|
|
cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
|
|
|
|
clk_disable_unprepare(xspi->ref_clk);
|
|
clk_disable_unprepare(xspi->pclk);
|
|
pm_runtime_set_suspended(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
spi_unregister_controller(ctlr);
|
|
}
|
|
|
|
/**
|
|
* cdns_spi_suspend - Suspend method for the SPI driver
|
|
* @dev: Address of the platform_device structure
|
|
*
|
|
* This function disables the SPI controller and
|
|
* changes the driver state to "suspend"
|
|
*
|
|
* Return: 0 on success and error value on error
|
|
*/
|
|
static int __maybe_unused cdns_spi_suspend(struct device *dev)
|
|
{
|
|
struct spi_controller *ctlr = dev_get_drvdata(dev);
|
|
|
|
return spi_controller_suspend(ctlr);
|
|
}
|
|
|
|
/**
|
|
* cdns_spi_resume - Resume method for the SPI driver
|
|
* @dev: Address of the platform_device structure
|
|
*
|
|
* This function changes the driver state to "ready"
|
|
*
|
|
* Return: 0 on success and error value on error
|
|
*/
|
|
static int __maybe_unused cdns_spi_resume(struct device *dev)
|
|
{
|
|
struct spi_controller *ctlr = dev_get_drvdata(dev);
|
|
struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
|
|
|
|
cdns_spi_init_hw(xspi, spi_controller_is_target(ctlr));
|
|
return spi_controller_resume(ctlr);
|
|
}
|
|
|
|
/**
|
|
* cdns_spi_runtime_resume - Runtime resume method for the SPI driver
|
|
* @dev: Address of the platform_device structure
|
|
*
|
|
* This function enables the clocks
|
|
*
|
|
* Return: 0 on success and error value on error
|
|
*/
|
|
static int __maybe_unused cdns_spi_runtime_resume(struct device *dev)
|
|
{
|
|
struct spi_controller *ctlr = dev_get_drvdata(dev);
|
|
struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(xspi->pclk);
|
|
if (ret) {
|
|
dev_err(dev, "Cannot enable APB clock.\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_prepare_enable(xspi->ref_clk);
|
|
if (ret) {
|
|
dev_err(dev, "Cannot enable device clock.\n");
|
|
clk_disable_unprepare(xspi->pclk);
|
|
return ret;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver
|
|
* @dev: Address of the platform_device structure
|
|
*
|
|
* This function disables the clocks
|
|
*
|
|
* Return: Always 0
|
|
*/
|
|
static int __maybe_unused cdns_spi_runtime_suspend(struct device *dev)
|
|
{
|
|
struct spi_controller *ctlr = dev_get_drvdata(dev);
|
|
struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
|
|
|
|
clk_disable_unprepare(xspi->ref_clk);
|
|
clk_disable_unprepare(xspi->pclk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops cdns_spi_dev_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(cdns_spi_runtime_suspend,
|
|
cdns_spi_runtime_resume, NULL)
|
|
SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume)
|
|
};
|
|
|
|
static const struct of_device_id cdns_spi_of_match[] = {
|
|
{ .compatible = "xlnx,zynq-spi-r1p6" },
|
|
{ .compatible = "cdns,spi-r1p6" },
|
|
{ /* end of table */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
|
|
|
|
/* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
|
|
static struct platform_driver cdns_spi_driver = {
|
|
.probe = cdns_spi_probe,
|
|
.remove_new = cdns_spi_remove,
|
|
.driver = {
|
|
.name = CDNS_SPI_NAME,
|
|
.of_match_table = cdns_spi_of_match,
|
|
.pm = &cdns_spi_dev_pm_ops,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(cdns_spi_driver);
|
|
|
|
MODULE_AUTHOR("Xilinx, Inc.");
|
|
MODULE_DESCRIPTION("Cadence SPI driver");
|
|
MODULE_LICENSE("GPL");
|