594 строки
14 KiB
C
594 строки
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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// Copyright (C) IBM Corporation 2020
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/fsi.h>
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#include <linux/jiffies.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/spi/spi.h>
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#define FSI_ENGID_SPI 0x23
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#define FSI_MBOX_ROOT_CTRL_8 0x2860
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#define FSI_MBOX_ROOT_CTRL_8_SPI_MUX 0xf0000000
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#define FSI2SPI_DATA0 0x00
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#define FSI2SPI_DATA1 0x04
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#define FSI2SPI_CMD 0x08
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#define FSI2SPI_CMD_WRITE BIT(31)
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#define FSI2SPI_RESET 0x18
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#define FSI2SPI_STATUS 0x1c
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#define FSI2SPI_STATUS_ANY_ERROR BIT(31)
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#define FSI2SPI_IRQ 0x20
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#define SPI_FSI_BASE 0x70000
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#define SPI_FSI_TIMEOUT_MS 1000
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#define SPI_FSI_MAX_RX_SIZE 8
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#define SPI_FSI_MAX_TX_SIZE 40
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#define SPI_FSI_ERROR 0x0
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#define SPI_FSI_COUNTER_CFG 0x1
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#define SPI_FSI_CFG1 0x2
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#define SPI_FSI_CLOCK_CFG 0x3
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#define SPI_FSI_CLOCK_CFG_MM_ENABLE BIT_ULL(32)
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#define SPI_FSI_CLOCK_CFG_ECC_DISABLE (BIT_ULL(35) | BIT_ULL(33))
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#define SPI_FSI_CLOCK_CFG_RESET1 (BIT_ULL(36) | BIT_ULL(38))
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#define SPI_FSI_CLOCK_CFG_RESET2 (BIT_ULL(37) | BIT_ULL(39))
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#define SPI_FSI_CLOCK_CFG_MODE (BIT_ULL(41) | BIT_ULL(42))
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#define SPI_FSI_CLOCK_CFG_SCK_RECV_DEL GENMASK_ULL(51, 44)
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#define SPI_FSI_CLOCK_CFG_SCK_NO_DEL BIT_ULL(51)
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#define SPI_FSI_CLOCK_CFG_SCK_DIV GENMASK_ULL(63, 52)
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#define SPI_FSI_MMAP 0x4
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#define SPI_FSI_DATA_TX 0x5
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#define SPI_FSI_DATA_RX 0x6
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#define SPI_FSI_SEQUENCE 0x7
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#define SPI_FSI_SEQUENCE_STOP 0x00
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#define SPI_FSI_SEQUENCE_SEL_SLAVE(x) (0x10 | ((x) & 0xf))
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#define SPI_FSI_SEQUENCE_SHIFT_OUT(x) (0x30 | ((x) & 0xf))
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#define SPI_FSI_SEQUENCE_SHIFT_IN(x) (0x40 | ((x) & 0xf))
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#define SPI_FSI_SEQUENCE_COPY_DATA_TX 0xc0
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#define SPI_FSI_SEQUENCE_BRANCH(x) (0xe0 | ((x) & 0xf))
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#define SPI_FSI_STATUS 0x8
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#define SPI_FSI_STATUS_ERROR \
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(GENMASK_ULL(31, 21) | GENMASK_ULL(15, 12))
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#define SPI_FSI_STATUS_SEQ_STATE GENMASK_ULL(55, 48)
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#define SPI_FSI_STATUS_SEQ_STATE_IDLE BIT_ULL(48)
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#define SPI_FSI_STATUS_TDR_UNDERRUN BIT_ULL(57)
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#define SPI_FSI_STATUS_TDR_OVERRUN BIT_ULL(58)
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#define SPI_FSI_STATUS_TDR_FULL BIT_ULL(59)
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#define SPI_FSI_STATUS_RDR_UNDERRUN BIT_ULL(61)
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#define SPI_FSI_STATUS_RDR_OVERRUN BIT_ULL(62)
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#define SPI_FSI_STATUS_RDR_FULL BIT_ULL(63)
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#define SPI_FSI_STATUS_ANY_ERROR \
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(SPI_FSI_STATUS_ERROR | \
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SPI_FSI_STATUS_TDR_OVERRUN | SPI_FSI_STATUS_RDR_UNDERRUN | \
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SPI_FSI_STATUS_RDR_OVERRUN)
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#define SPI_FSI_PORT_CTRL 0x9
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struct fsi2spi {
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struct fsi_device *fsi; /* FSI2SPI CFAM engine device */
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struct mutex lock; /* lock access to the device */
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};
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struct fsi_spi {
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struct device *dev; /* SPI controller device */
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struct fsi2spi *bridge; /* FSI2SPI device */
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u32 base;
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};
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struct fsi_spi_sequence {
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int bit;
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u64 data;
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};
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static int fsi_spi_check_mux(struct fsi_device *fsi, struct device *dev)
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{
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int rc;
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u32 root_ctrl_8;
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__be32 root_ctrl_8_be;
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rc = fsi_slave_read(fsi->slave, FSI_MBOX_ROOT_CTRL_8, &root_ctrl_8_be,
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sizeof(root_ctrl_8_be));
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if (rc)
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return rc;
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root_ctrl_8 = be32_to_cpu(root_ctrl_8_be);
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dev_dbg(dev, "Root control register 8: %08x\n", root_ctrl_8);
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if ((root_ctrl_8 & FSI_MBOX_ROOT_CTRL_8_SPI_MUX) ==
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FSI_MBOX_ROOT_CTRL_8_SPI_MUX)
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return 0;
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return -ENOLINK;
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}
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static int fsi_spi_check_status(struct fsi_spi *ctx)
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{
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int rc;
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u32 sts;
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__be32 sts_be;
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rc = fsi_device_read(ctx->bridge->fsi, FSI2SPI_STATUS, &sts_be,
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sizeof(sts_be));
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if (rc)
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return rc;
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sts = be32_to_cpu(sts_be);
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if (sts & FSI2SPI_STATUS_ANY_ERROR) {
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dev_err(ctx->dev, "Error with FSI2SPI interface: %08x.\n", sts);
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return -EIO;
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}
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return 0;
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}
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static int fsi_spi_read_reg(struct fsi_spi *ctx, u32 offset, u64 *value)
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{
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int rc = 0;
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__be32 cmd_be;
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__be32 data_be;
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u32 cmd = offset + ctx->base;
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struct fsi2spi *bridge = ctx->bridge;
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*value = 0ULL;
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if (cmd & FSI2SPI_CMD_WRITE)
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return -EINVAL;
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rc = mutex_lock_interruptible(&bridge->lock);
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if (rc)
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return rc;
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cmd_be = cpu_to_be32(cmd);
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rc = fsi_device_write(bridge->fsi, FSI2SPI_CMD, &cmd_be,
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sizeof(cmd_be));
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if (rc)
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goto unlock;
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rc = fsi_spi_check_status(ctx);
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if (rc)
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goto unlock;
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rc = fsi_device_read(bridge->fsi, FSI2SPI_DATA0, &data_be,
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sizeof(data_be));
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if (rc)
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goto unlock;
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*value |= (u64)be32_to_cpu(data_be) << 32;
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rc = fsi_device_read(bridge->fsi, FSI2SPI_DATA1, &data_be,
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sizeof(data_be));
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if (rc)
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goto unlock;
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*value |= (u64)be32_to_cpu(data_be);
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dev_dbg(ctx->dev, "Read %02x[%016llx].\n", offset, *value);
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unlock:
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mutex_unlock(&bridge->lock);
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return rc;
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}
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static int fsi_spi_write_reg(struct fsi_spi *ctx, u32 offset, u64 value)
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{
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int rc = 0;
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__be32 cmd_be;
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__be32 data_be;
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u32 cmd = offset + ctx->base;
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struct fsi2spi *bridge = ctx->bridge;
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if (cmd & FSI2SPI_CMD_WRITE)
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return -EINVAL;
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rc = mutex_lock_interruptible(&bridge->lock);
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if (rc)
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return rc;
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dev_dbg(ctx->dev, "Write %02x[%016llx].\n", offset, value);
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data_be = cpu_to_be32(upper_32_bits(value));
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rc = fsi_device_write(bridge->fsi, FSI2SPI_DATA0, &data_be,
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sizeof(data_be));
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if (rc)
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goto unlock;
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data_be = cpu_to_be32(lower_32_bits(value));
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rc = fsi_device_write(bridge->fsi, FSI2SPI_DATA1, &data_be,
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sizeof(data_be));
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if (rc)
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goto unlock;
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cmd_be = cpu_to_be32(cmd | FSI2SPI_CMD_WRITE);
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rc = fsi_device_write(bridge->fsi, FSI2SPI_CMD, &cmd_be,
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sizeof(cmd_be));
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if (rc)
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goto unlock;
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rc = fsi_spi_check_status(ctx);
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unlock:
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mutex_unlock(&bridge->lock);
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return rc;
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}
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static int fsi_spi_data_in(u64 in, u8 *rx, int len)
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{
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int i;
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int num_bytes = min(len, 8);
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for (i = 0; i < num_bytes; ++i)
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rx[i] = (u8)(in >> (8 * ((num_bytes - 1) - i)));
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return num_bytes;
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}
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static int fsi_spi_data_out(u64 *out, const u8 *tx, int len)
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{
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int i;
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int num_bytes = min(len, 8);
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u8 *out_bytes = (u8 *)out;
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/* Unused bytes of the tx data should be 0. */
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*out = 0ULL;
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for (i = 0; i < num_bytes; ++i)
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out_bytes[8 - (i + 1)] = tx[i];
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return num_bytes;
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}
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static int fsi_spi_reset(struct fsi_spi *ctx)
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{
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int rc;
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dev_dbg(ctx->dev, "Resetting SPI controller.\n");
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rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
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SPI_FSI_CLOCK_CFG_RESET1);
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if (rc)
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return rc;
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rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
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SPI_FSI_CLOCK_CFG_RESET2);
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if (rc)
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return rc;
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return fsi_spi_write_reg(ctx, SPI_FSI_STATUS, 0ULL);
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}
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static int fsi_spi_status(struct fsi_spi *ctx, u64 *status, const char *dir)
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{
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int rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS, status);
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if (rc)
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return rc;
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if (*status & SPI_FSI_STATUS_ANY_ERROR) {
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dev_err(ctx->dev, "%s error: %016llx\n", dir, *status);
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rc = fsi_spi_reset(ctx);
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if (rc)
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return rc;
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return -EREMOTEIO;
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}
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return 0;
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}
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static void fsi_spi_sequence_add(struct fsi_spi_sequence *seq, u8 val)
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{
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/*
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* Add the next byte of instruction to the 8-byte sequence register.
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* Then decrement the counter so that the next instruction will go in
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* the right place. Return the index of the slot we just filled in the
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* sequence register.
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*/
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seq->data |= (u64)val << seq->bit;
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seq->bit -= 8;
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}
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static void fsi_spi_sequence_init(struct fsi_spi_sequence *seq)
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{
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seq->bit = 56;
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seq->data = 0ULL;
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}
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static int fsi_spi_transfer_data(struct fsi_spi *ctx,
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struct spi_transfer *transfer)
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{
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int loops;
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int rc = 0;
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unsigned long end;
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u64 status = 0ULL;
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if (transfer->tx_buf) {
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int nb;
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int sent = 0;
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u64 out = 0ULL;
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const u8 *tx = transfer->tx_buf;
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while (transfer->len > sent) {
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nb = fsi_spi_data_out(&out, &tx[sent],
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(int)transfer->len - sent);
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rc = fsi_spi_write_reg(ctx, SPI_FSI_DATA_TX, out);
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if (rc)
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return rc;
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loops = 0;
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end = jiffies + msecs_to_jiffies(SPI_FSI_TIMEOUT_MS);
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do {
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if (loops++ && time_after(jiffies, end))
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return -ETIMEDOUT;
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rc = fsi_spi_status(ctx, &status, "TX");
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if (rc)
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return rc;
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} while (status & SPI_FSI_STATUS_TDR_FULL);
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sent += nb;
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}
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} else if (transfer->rx_buf) {
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int recv = 0;
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u64 in = 0ULL;
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u8 *rx = transfer->rx_buf;
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while (transfer->len > recv) {
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loops = 0;
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end = jiffies + msecs_to_jiffies(SPI_FSI_TIMEOUT_MS);
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do {
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if (loops++ && time_after(jiffies, end))
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return -ETIMEDOUT;
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rc = fsi_spi_status(ctx, &status, "RX");
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if (rc)
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return rc;
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} while (!(status & SPI_FSI_STATUS_RDR_FULL));
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rc = fsi_spi_read_reg(ctx, SPI_FSI_DATA_RX, &in);
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if (rc)
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return rc;
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recv += fsi_spi_data_in(in, &rx[recv],
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(int)transfer->len - recv);
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}
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}
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return 0;
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}
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static int fsi_spi_transfer_init(struct fsi_spi *ctx)
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{
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int loops = 0;
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int rc;
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bool reset = false;
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unsigned long end;
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u64 seq_state;
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u64 clock_cfg = 0ULL;
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u64 status = 0ULL;
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u64 wanted_clock_cfg = SPI_FSI_CLOCK_CFG_ECC_DISABLE |
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SPI_FSI_CLOCK_CFG_SCK_NO_DEL |
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FIELD_PREP(SPI_FSI_CLOCK_CFG_SCK_DIV, 19);
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end = jiffies + msecs_to_jiffies(SPI_FSI_TIMEOUT_MS);
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do {
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if (loops++ && time_after(jiffies, end))
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return -ETIMEDOUT;
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rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS, &status);
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if (rc)
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return rc;
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seq_state = status & SPI_FSI_STATUS_SEQ_STATE;
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if (status & (SPI_FSI_STATUS_ANY_ERROR |
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SPI_FSI_STATUS_TDR_FULL |
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SPI_FSI_STATUS_RDR_FULL)) {
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if (reset) {
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dev_err(ctx->dev,
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"Initialization error: %08llx\n",
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status);
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return -EIO;
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}
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rc = fsi_spi_reset(ctx);
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if (rc)
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return rc;
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reset = true;
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continue;
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}
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} while (seq_state && (seq_state != SPI_FSI_STATUS_SEQ_STATE_IDLE));
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rc = fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG, 0ULL);
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if (rc)
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return rc;
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rc = fsi_spi_read_reg(ctx, SPI_FSI_CLOCK_CFG, &clock_cfg);
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if (rc)
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return rc;
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if ((clock_cfg & (SPI_FSI_CLOCK_CFG_MM_ENABLE |
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SPI_FSI_CLOCK_CFG_ECC_DISABLE |
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SPI_FSI_CLOCK_CFG_MODE |
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SPI_FSI_CLOCK_CFG_SCK_RECV_DEL |
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SPI_FSI_CLOCK_CFG_SCK_DIV)) != wanted_clock_cfg)
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rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
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wanted_clock_cfg);
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return rc;
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}
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static int fsi_spi_transfer_one_message(struct spi_controller *ctlr,
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struct spi_message *mesg)
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{
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int rc;
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u8 seq_slave = SPI_FSI_SEQUENCE_SEL_SLAVE(spi_get_chipselect(mesg->spi, 0) + 1);
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unsigned int len;
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struct spi_transfer *transfer;
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struct fsi_spi *ctx = spi_controller_get_devdata(ctlr);
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rc = fsi_spi_check_mux(ctx->bridge->fsi, ctx->dev);
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if (rc)
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goto error;
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list_for_each_entry(transfer, &mesg->transfers, transfer_list) {
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struct fsi_spi_sequence seq;
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struct spi_transfer *next = NULL;
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/* Sequencer must do shift out (tx) first. */
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if (!transfer->tx_buf || transfer->len > SPI_FSI_MAX_TX_SIZE) {
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rc = -EINVAL;
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goto error;
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}
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dev_dbg(ctx->dev, "Start tx of %d bytes.\n", transfer->len);
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rc = fsi_spi_transfer_init(ctx);
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if (rc < 0)
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goto error;
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fsi_spi_sequence_init(&seq);
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fsi_spi_sequence_add(&seq, seq_slave);
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len = transfer->len;
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while (len > 8) {
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fsi_spi_sequence_add(&seq,
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SPI_FSI_SEQUENCE_SHIFT_OUT(8));
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len -= 8;
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}
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fsi_spi_sequence_add(&seq, SPI_FSI_SEQUENCE_SHIFT_OUT(len));
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if (!list_is_last(&transfer->transfer_list,
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&mesg->transfers)) {
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next = list_next_entry(transfer, transfer_list);
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/* Sequencer can only do shift in (rx) after tx. */
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if (next->rx_buf) {
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u8 shift;
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if (next->len > SPI_FSI_MAX_RX_SIZE) {
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rc = -EINVAL;
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goto error;
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}
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dev_dbg(ctx->dev, "Sequence rx of %d bytes.\n",
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next->len);
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shift = SPI_FSI_SEQUENCE_SHIFT_IN(next->len);
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fsi_spi_sequence_add(&seq, shift);
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} else {
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next = NULL;
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}
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}
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fsi_spi_sequence_add(&seq, SPI_FSI_SEQUENCE_SEL_SLAVE(0));
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rc = fsi_spi_write_reg(ctx, SPI_FSI_SEQUENCE, seq.data);
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if (rc)
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goto error;
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rc = fsi_spi_transfer_data(ctx, transfer);
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if (rc)
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goto error;
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if (next) {
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rc = fsi_spi_transfer_data(ctx, next);
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if (rc)
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goto error;
|
|
|
|
transfer = next;
|
|
}
|
|
}
|
|
|
|
error:
|
|
mesg->status = rc;
|
|
spi_finalize_current_message(ctlr);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static size_t fsi_spi_max_transfer_size(struct spi_device *spi)
|
|
{
|
|
return SPI_FSI_MAX_RX_SIZE;
|
|
}
|
|
|
|
static int fsi_spi_probe(struct device *dev)
|
|
{
|
|
int rc;
|
|
struct device_node *np;
|
|
int num_controllers_registered = 0;
|
|
struct fsi2spi *bridge;
|
|
struct fsi_device *fsi = to_fsi_dev(dev);
|
|
|
|
rc = fsi_spi_check_mux(fsi, dev);
|
|
if (rc)
|
|
return -ENODEV;
|
|
|
|
bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
|
|
if (!bridge)
|
|
return -ENOMEM;
|
|
|
|
bridge->fsi = fsi;
|
|
mutex_init(&bridge->lock);
|
|
|
|
for_each_available_child_of_node(dev->of_node, np) {
|
|
u32 base;
|
|
struct fsi_spi *ctx;
|
|
struct spi_controller *ctlr;
|
|
|
|
if (of_property_read_u32(np, "reg", &base))
|
|
continue;
|
|
|
|
ctlr = spi_alloc_host(dev, sizeof(*ctx));
|
|
if (!ctlr) {
|
|
of_node_put(np);
|
|
break;
|
|
}
|
|
|
|
ctlr->dev.of_node = np;
|
|
ctlr->num_chipselect = of_get_available_child_count(np) ?: 1;
|
|
ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX;
|
|
ctlr->max_transfer_size = fsi_spi_max_transfer_size;
|
|
ctlr->transfer_one_message = fsi_spi_transfer_one_message;
|
|
|
|
ctx = spi_controller_get_devdata(ctlr);
|
|
ctx->dev = &ctlr->dev;
|
|
ctx->bridge = bridge;
|
|
ctx->base = base + SPI_FSI_BASE;
|
|
|
|
rc = devm_spi_register_controller(dev, ctlr);
|
|
if (rc)
|
|
spi_controller_put(ctlr);
|
|
else
|
|
num_controllers_registered++;
|
|
}
|
|
|
|
if (!num_controllers_registered)
|
|
return -ENODEV;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct fsi_device_id fsi_spi_ids[] = {
|
|
{ FSI_ENGID_SPI, FSI_VERSION_ANY },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(fsi, fsi_spi_ids);
|
|
|
|
static struct fsi_driver fsi_spi_driver = {
|
|
.id_table = fsi_spi_ids,
|
|
.drv = {
|
|
.name = "spi-fsi",
|
|
.bus = &fsi_bus_type,
|
|
.probe = fsi_spi_probe,
|
|
},
|
|
};
|
|
module_fsi_driver(fsi_spi_driver);
|
|
|
|
MODULE_AUTHOR("Eddie James <eajames@linux.ibm.com>");
|
|
MODULE_DESCRIPTION("FSI attached SPI controller");
|
|
MODULE_LICENSE("GPL");
|