369 строки
9.5 KiB
C
369 строки
9.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* MPC52xx PSC in SPI mode driver.
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*
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* Maintainer: Dragos Carp
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*
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* Copyright (C) 2006 TOPTICA Photonics AG.
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <linux/workqueue.h>
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#include <linux/completion.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/spi/spi.h>
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#include <linux/slab.h>
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#include <asm/mpc52xx.h>
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#include <asm/mpc52xx_psc.h>
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#define MCLK 20000000 /* PSC port MClk in hz */
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struct mpc52xx_psc_spi {
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/* driver internal data */
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struct mpc52xx_psc __iomem *psc;
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struct mpc52xx_psc_fifo __iomem *fifo;
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int irq;
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u8 bits_per_word;
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struct completion done;
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};
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/* controller state */
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struct mpc52xx_psc_spi_cs {
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int bits_per_word;
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int speed_hz;
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};
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/* set clock freq, clock ramp, bits per work
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* if t is NULL then reset the values to the default values
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*/
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static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
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cs->speed_hz = (t && t->speed_hz)
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? t->speed_hz : spi->max_speed_hz;
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cs->bits_per_word = (t && t->bits_per_word)
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? t->bits_per_word : spi->bits_per_word;
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cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
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return 0;
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}
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static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
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{
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struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
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struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
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struct mpc52xx_psc __iomem *psc = mps->psc;
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u32 sicr;
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u16 ccr;
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sicr = in_be32(&psc->sicr);
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/* Set clock phase and polarity */
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if (spi->mode & SPI_CPHA)
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sicr |= 0x00001000;
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else
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sicr &= ~0x00001000;
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if (spi->mode & SPI_CPOL)
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sicr |= 0x00002000;
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else
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sicr &= ~0x00002000;
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if (spi->mode & SPI_LSB_FIRST)
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sicr |= 0x10000000;
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else
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sicr &= ~0x10000000;
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out_be32(&psc->sicr, sicr);
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/* Set clock frequency and bits per word
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* Because psc->ccr is defined as 16bit register instead of 32bit
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* just set the lower byte of BitClkDiv
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*/
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ccr = in_be16((u16 __iomem *)&psc->ccr);
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ccr &= 0xFF00;
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if (cs->speed_hz)
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ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
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else /* by default SPI Clk 1MHz */
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ccr |= (MCLK / 1000000 - 1) & 0xFF;
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out_be16((u16 __iomem *)&psc->ccr, ccr);
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mps->bits_per_word = cs->bits_per_word;
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}
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#define MPC52xx_PSC_BUFSIZE (MPC52xx_PSC_RFNUM_MASK + 1)
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/* wake up when 80% fifo full */
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#define MPC52xx_PSC_RFALARM (MPC52xx_PSC_BUFSIZE * 20 / 100)
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static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
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struct mpc52xx_psc __iomem *psc = mps->psc;
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struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
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unsigned rb = 0; /* number of bytes receieved */
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unsigned sb = 0; /* number of bytes sent */
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unsigned char *rx_buf = (unsigned char *)t->rx_buf;
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unsigned char *tx_buf = (unsigned char *)t->tx_buf;
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unsigned rfalarm;
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unsigned send_at_once = MPC52xx_PSC_BUFSIZE;
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unsigned recv_at_once;
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int last_block = 0;
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if (!t->tx_buf && !t->rx_buf && t->len)
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return -EINVAL;
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/* enable transmiter/receiver */
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out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
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while (rb < t->len) {
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if (t->len - rb > MPC52xx_PSC_BUFSIZE) {
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rfalarm = MPC52xx_PSC_RFALARM;
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last_block = 0;
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} else {
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send_at_once = t->len - sb;
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rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb);
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last_block = 1;
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}
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dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once);
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for (; send_at_once; sb++, send_at_once--) {
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/* set EOF flag before the last word is sent */
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if (send_at_once == 1 && last_block)
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out_8(&psc->ircr2, 0x01);
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if (tx_buf)
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out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]);
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else
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out_8(&psc->mpc52xx_psc_buffer_8, 0);
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}
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/* enable interrupts and wait for wake up
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* if just one byte is expected the Rx FIFO genererates no
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* FFULL interrupt, so activate the RxRDY interrupt
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*/
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out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
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if (t->len - rb == 1) {
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out_8(&psc->mode, 0);
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} else {
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out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
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out_be16(&fifo->rfalarm, rfalarm);
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}
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out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY);
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wait_for_completion(&mps->done);
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recv_at_once = in_be16(&fifo->rfnum);
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dev_dbg(&spi->dev, "%d bytes received\n", recv_at_once);
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send_at_once = recv_at_once;
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if (rx_buf) {
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for (; recv_at_once; rb++, recv_at_once--)
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rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8);
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} else {
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for (; recv_at_once; rb++, recv_at_once--)
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in_8(&psc->mpc52xx_psc_buffer_8);
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}
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}
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/* disable transmiter/receiver */
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out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
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return 0;
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}
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int mpc52xx_psc_spi_transfer_one_message(struct spi_controller *ctlr,
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struct spi_message *m)
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{
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struct spi_device *spi;
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struct spi_transfer *t = NULL;
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unsigned cs_change;
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int status;
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spi = m->spi;
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cs_change = 1;
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status = 0;
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list_for_each_entry (t, &m->transfers, transfer_list) {
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if (t->bits_per_word || t->speed_hz) {
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status = mpc52xx_psc_spi_transfer_setup(spi, t);
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if (status < 0)
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break;
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}
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if (cs_change)
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mpc52xx_psc_spi_activate_cs(spi);
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cs_change = t->cs_change;
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status = mpc52xx_psc_spi_transfer_rxtx(spi, t);
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if (status)
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break;
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m->actual_length += t->len;
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spi_transfer_delay_exec(t);
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}
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m->status = status;
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mpc52xx_psc_spi_transfer_setup(spi, NULL);
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spi_finalize_current_message(ctlr);
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return 0;
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}
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static int mpc52xx_psc_spi_setup(struct spi_device *spi)
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{
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struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
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if (spi->bits_per_word%8)
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return -EINVAL;
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if (!cs) {
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cs = kzalloc(sizeof(*cs), GFP_KERNEL);
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if (!cs)
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return -ENOMEM;
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spi->controller_state = cs;
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}
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cs->bits_per_word = spi->bits_per_word;
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cs->speed_hz = spi->max_speed_hz;
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return 0;
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}
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static void mpc52xx_psc_spi_cleanup(struct spi_device *spi)
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{
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kfree(spi->controller_state);
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}
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static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
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{
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struct mpc52xx_psc __iomem *psc = mps->psc;
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struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
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u32 mclken_div;
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int ret;
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/* default sysclk is 512MHz */
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mclken_div = 512000000 / MCLK;
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ret = mpc52xx_set_psc_clkdiv(psc_id, mclken_div);
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if (ret)
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return ret;
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/* Reset the PSC into a known state */
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out_8(&psc->command, MPC52xx_PSC_RST_RX);
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out_8(&psc->command, MPC52xx_PSC_RST_TX);
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out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
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/* Disable interrupts, interrupts are based on alarm level */
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out_be16(&psc->mpc52xx_psc_imr, 0);
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out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
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out_8(&fifo->rfcntl, 0);
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out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
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/* Configure 8bit codec mode as a SPI master and use EOF flags */
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/* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
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out_be32(&psc->sicr, 0x0180C800);
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out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */
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/* Set 2ms DTL delay */
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out_8(&psc->ctur, 0x00);
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out_8(&psc->ctlr, 0x84);
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mps->bits_per_word = 8;
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return 0;
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}
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static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id)
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{
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struct mpc52xx_psc_spi *mps = (struct mpc52xx_psc_spi *)dev_id;
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struct mpc52xx_psc __iomem *psc = mps->psc;
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/* disable interrupt and wake up the work queue */
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if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) {
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out_be16(&psc->mpc52xx_psc_imr, 0);
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complete(&mps->done);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static int mpc52xx_psc_spi_of_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mpc52xx_psc_spi *mps;
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struct spi_master *master;
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u32 bus_num;
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int ret;
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master = devm_spi_alloc_master(dev, sizeof(*mps));
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if (master == NULL)
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return -ENOMEM;
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dev_set_drvdata(dev, master);
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mps = spi_master_get_devdata(master);
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/* the spi->mode bits understood by this driver: */
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master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
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ret = device_property_read_u32(dev, "cell-index", &bus_num);
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if (ret || bus_num > 5)
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return dev_err_probe(dev, ret ? : -EINVAL, "Invalid cell-index property\n");
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master->bus_num = bus_num + 1;
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master->num_chipselect = 255;
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master->setup = mpc52xx_psc_spi_setup;
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master->transfer_one_message = mpc52xx_psc_spi_transfer_one_message;
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master->cleanup = mpc52xx_psc_spi_cleanup;
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device_set_node(&master->dev, dev_fwnode(dev));
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mps->psc = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
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if (IS_ERR(mps->psc))
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return dev_err_probe(dev, PTR_ERR(mps->psc), "could not ioremap I/O port range\n");
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/* On the 5200, fifo regs are immediately ajacent to the psc regs */
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mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc);
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mps->irq = platform_get_irq(pdev, 0);
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if (mps->irq < 0)
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return mps->irq;
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ret = devm_request_irq(dev, mps->irq, mpc52xx_psc_spi_isr, 0,
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"mpc52xx-psc-spi", mps);
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if (ret)
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return ret;
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ret = mpc52xx_psc_spi_port_config(master->bus_num, mps);
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if (ret < 0)
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return dev_err_probe(dev, ret, "can't configure PSC! Is it capable of SPI?\n");
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init_completion(&mps->done);
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return devm_spi_register_master(dev, master);
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}
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static const struct of_device_id mpc52xx_psc_spi_of_match[] = {
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{ .compatible = "fsl,mpc5200-psc-spi", },
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{ .compatible = "mpc5200-psc-spi", }, /* old */
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{}
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};
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MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match);
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static struct platform_driver mpc52xx_psc_spi_of_driver = {
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.probe = mpc52xx_psc_spi_of_probe,
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.driver = {
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.name = "mpc52xx-psc-spi",
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.of_match_table = mpc52xx_psc_spi_of_match,
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},
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};
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module_platform_driver(mpc52xx_psc_spi_of_driver);
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MODULE_AUTHOR("Dragos Carp");
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MODULE_DESCRIPTION("MPC52xx PSC SPI Driver");
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MODULE_LICENSE("GPL");
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