570 строки
14 KiB
C
570 строки
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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// Copyright (c) 2018 MediaTek Inc.
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/spi/spi.h>
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#include <linux/of.h>
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#define SPIS_IRQ_EN_REG 0x0
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#define SPIS_IRQ_CLR_REG 0x4
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#define SPIS_IRQ_ST_REG 0x8
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#define SPIS_IRQ_MASK_REG 0xc
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#define SPIS_CFG_REG 0x10
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#define SPIS_RX_DATA_REG 0x14
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#define SPIS_TX_DATA_REG 0x18
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#define SPIS_RX_DST_REG 0x1c
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#define SPIS_TX_SRC_REG 0x20
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#define SPIS_DMA_CFG_REG 0x30
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#define SPIS_SOFT_RST_REG 0x40
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/* SPIS_IRQ_EN_REG */
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#define DMA_DONE_EN BIT(7)
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#define DATA_DONE_EN BIT(2)
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#define RSTA_DONE_EN BIT(1)
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#define CMD_INVALID_EN BIT(0)
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/* SPIS_IRQ_ST_REG */
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#define DMA_DONE_ST BIT(7)
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#define DATA_DONE_ST BIT(2)
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#define RSTA_DONE_ST BIT(1)
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#define CMD_INVALID_ST BIT(0)
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/* SPIS_IRQ_MASK_REG */
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#define DMA_DONE_MASK BIT(7)
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#define DATA_DONE_MASK BIT(2)
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#define RSTA_DONE_MASK BIT(1)
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#define CMD_INVALID_MASK BIT(0)
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/* SPIS_CFG_REG */
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#define SPIS_TX_ENDIAN BIT(7)
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#define SPIS_RX_ENDIAN BIT(6)
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#define SPIS_TXMSBF BIT(5)
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#define SPIS_RXMSBF BIT(4)
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#define SPIS_CPHA BIT(3)
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#define SPIS_CPOL BIT(2)
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#define SPIS_TX_EN BIT(1)
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#define SPIS_RX_EN BIT(0)
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/* SPIS_DMA_CFG_REG */
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#define TX_DMA_TRIG_EN BIT(31)
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#define TX_DMA_EN BIT(30)
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#define RX_DMA_EN BIT(29)
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#define TX_DMA_LEN 0xfffff
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/* SPIS_SOFT_RST_REG */
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#define SPIS_DMA_ADDR_EN BIT(1)
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#define SPIS_SOFT_RST BIT(0)
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struct mtk_spi_slave {
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struct device *dev;
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void __iomem *base;
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struct clk *spi_clk;
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struct completion xfer_done;
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struct spi_transfer *cur_transfer;
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bool slave_aborted;
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const struct mtk_spi_compatible *dev_comp;
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};
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struct mtk_spi_compatible {
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const u32 max_fifo_size;
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bool must_rx;
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};
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static const struct mtk_spi_compatible mt2712_compat = {
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.max_fifo_size = 512,
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};
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static const struct mtk_spi_compatible mt8195_compat = {
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.max_fifo_size = 128,
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.must_rx = true,
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};
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static const struct of_device_id mtk_spi_slave_of_match[] = {
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{ .compatible = "mediatek,mt2712-spi-slave",
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.data = (void *)&mt2712_compat,},
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{ .compatible = "mediatek,mt8195-spi-slave",
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.data = (void *)&mt8195_compat,},
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{}
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};
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MODULE_DEVICE_TABLE(of, mtk_spi_slave_of_match);
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static void mtk_spi_slave_disable_dma(struct mtk_spi_slave *mdata)
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{
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u32 reg_val;
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reg_val = readl(mdata->base + SPIS_DMA_CFG_REG);
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reg_val &= ~RX_DMA_EN;
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reg_val &= ~TX_DMA_EN;
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writel(reg_val, mdata->base + SPIS_DMA_CFG_REG);
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}
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static void mtk_spi_slave_disable_xfer(struct mtk_spi_slave *mdata)
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{
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u32 reg_val;
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reg_val = readl(mdata->base + SPIS_CFG_REG);
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reg_val &= ~SPIS_TX_EN;
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reg_val &= ~SPIS_RX_EN;
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writel(reg_val, mdata->base + SPIS_CFG_REG);
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}
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static int mtk_spi_slave_wait_for_completion(struct mtk_spi_slave *mdata)
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{
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if (wait_for_completion_interruptible(&mdata->xfer_done) ||
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mdata->slave_aborted) {
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dev_err(mdata->dev, "interrupted\n");
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return -EINTR;
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}
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return 0;
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}
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static int mtk_spi_slave_prepare_message(struct spi_controller *ctlr,
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struct spi_message *msg)
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{
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struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
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struct spi_device *spi = msg->spi;
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bool cpha, cpol;
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u32 reg_val;
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cpha = spi->mode & SPI_CPHA ? 1 : 0;
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cpol = spi->mode & SPI_CPOL ? 1 : 0;
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reg_val = readl(mdata->base + SPIS_CFG_REG);
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if (cpha)
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reg_val |= SPIS_CPHA;
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else
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reg_val &= ~SPIS_CPHA;
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if (cpol)
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reg_val |= SPIS_CPOL;
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else
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reg_val &= ~SPIS_CPOL;
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if (spi->mode & SPI_LSB_FIRST)
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reg_val &= ~(SPIS_TXMSBF | SPIS_RXMSBF);
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else
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reg_val |= SPIS_TXMSBF | SPIS_RXMSBF;
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reg_val &= ~SPIS_TX_ENDIAN;
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reg_val &= ~SPIS_RX_ENDIAN;
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writel(reg_val, mdata->base + SPIS_CFG_REG);
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return 0;
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}
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static int mtk_spi_slave_fifo_transfer(struct spi_controller *ctlr,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
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int reg_val, cnt, remainder, ret;
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writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG);
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reg_val = readl(mdata->base + SPIS_CFG_REG);
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if (xfer->rx_buf)
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reg_val |= SPIS_RX_EN;
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if (xfer->tx_buf)
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reg_val |= SPIS_TX_EN;
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writel(reg_val, mdata->base + SPIS_CFG_REG);
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cnt = xfer->len / 4;
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if (xfer->tx_buf)
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iowrite32_rep(mdata->base + SPIS_TX_DATA_REG,
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xfer->tx_buf, cnt);
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remainder = xfer->len % 4;
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if (xfer->tx_buf && remainder > 0) {
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reg_val = 0;
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memcpy(®_val, xfer->tx_buf + cnt * 4, remainder);
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writel(reg_val, mdata->base + SPIS_TX_DATA_REG);
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}
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ret = mtk_spi_slave_wait_for_completion(mdata);
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if (ret) {
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mtk_spi_slave_disable_xfer(mdata);
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writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG);
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}
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return ret;
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}
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static int mtk_spi_slave_dma_transfer(struct spi_controller *ctlr,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
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struct device *dev = mdata->dev;
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int reg_val, ret;
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writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG);
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if (xfer->tx_buf) {
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/* tx_buf is a const void* where we need a void * for
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* the dma mapping
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*/
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void *nonconst_tx = (void *)xfer->tx_buf;
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xfer->tx_dma = dma_map_single(dev, nonconst_tx,
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xfer->len, DMA_TO_DEVICE);
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if (dma_mapping_error(dev, xfer->tx_dma)) {
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ret = -ENOMEM;
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goto disable_transfer;
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}
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}
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if (xfer->rx_buf) {
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xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
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xfer->len, DMA_FROM_DEVICE);
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if (dma_mapping_error(dev, xfer->rx_dma)) {
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ret = -ENOMEM;
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goto unmap_txdma;
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}
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}
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writel(xfer->tx_dma, mdata->base + SPIS_TX_SRC_REG);
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writel(xfer->rx_dma, mdata->base + SPIS_RX_DST_REG);
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writel(SPIS_DMA_ADDR_EN, mdata->base + SPIS_SOFT_RST_REG);
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/* enable config reg tx rx_enable */
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reg_val = readl(mdata->base + SPIS_CFG_REG);
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if (xfer->tx_buf)
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reg_val |= SPIS_TX_EN;
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if (xfer->rx_buf)
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reg_val |= SPIS_RX_EN;
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writel(reg_val, mdata->base + SPIS_CFG_REG);
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/* config dma */
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reg_val = 0;
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reg_val |= (xfer->len - 1) & TX_DMA_LEN;
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writel(reg_val, mdata->base + SPIS_DMA_CFG_REG);
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reg_val = readl(mdata->base + SPIS_DMA_CFG_REG);
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if (xfer->tx_buf)
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reg_val |= TX_DMA_EN;
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if (xfer->rx_buf)
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reg_val |= RX_DMA_EN;
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reg_val |= TX_DMA_TRIG_EN;
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writel(reg_val, mdata->base + SPIS_DMA_CFG_REG);
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ret = mtk_spi_slave_wait_for_completion(mdata);
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if (ret)
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goto unmap_rxdma;
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return 0;
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unmap_rxdma:
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if (xfer->rx_buf)
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dma_unmap_single(dev, xfer->rx_dma,
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xfer->len, DMA_FROM_DEVICE);
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unmap_txdma:
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if (xfer->tx_buf)
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dma_unmap_single(dev, xfer->tx_dma,
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xfer->len, DMA_TO_DEVICE);
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disable_transfer:
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mtk_spi_slave_disable_dma(mdata);
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mtk_spi_slave_disable_xfer(mdata);
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writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG);
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return ret;
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}
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static int mtk_spi_slave_transfer_one(struct spi_controller *ctlr,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
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reinit_completion(&mdata->xfer_done);
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mdata->slave_aborted = false;
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mdata->cur_transfer = xfer;
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if (xfer->len > mdata->dev_comp->max_fifo_size)
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return mtk_spi_slave_dma_transfer(ctlr, spi, xfer);
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else
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return mtk_spi_slave_fifo_transfer(ctlr, spi, xfer);
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}
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static int mtk_spi_slave_setup(struct spi_device *spi)
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{
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struct mtk_spi_slave *mdata = spi_controller_get_devdata(spi->master);
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u32 reg_val;
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reg_val = DMA_DONE_EN | DATA_DONE_EN |
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RSTA_DONE_EN | CMD_INVALID_EN;
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writel(reg_val, mdata->base + SPIS_IRQ_EN_REG);
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reg_val = DMA_DONE_MASK | DATA_DONE_MASK |
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RSTA_DONE_MASK | CMD_INVALID_MASK;
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writel(reg_val, mdata->base + SPIS_IRQ_MASK_REG);
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mtk_spi_slave_disable_dma(mdata);
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mtk_spi_slave_disable_xfer(mdata);
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return 0;
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}
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static int mtk_slave_abort(struct spi_controller *ctlr)
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{
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struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
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mdata->slave_aborted = true;
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complete(&mdata->xfer_done);
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return 0;
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}
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static irqreturn_t mtk_spi_slave_interrupt(int irq, void *dev_id)
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{
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struct spi_controller *ctlr = dev_id;
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struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
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struct spi_transfer *trans = mdata->cur_transfer;
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u32 int_status, reg_val, cnt, remainder;
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int_status = readl(mdata->base + SPIS_IRQ_ST_REG);
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writel(int_status, mdata->base + SPIS_IRQ_CLR_REG);
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if (!trans)
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return IRQ_NONE;
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if ((int_status & DMA_DONE_ST) &&
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((int_status & DATA_DONE_ST) ||
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(int_status & RSTA_DONE_ST))) {
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writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG);
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if (trans->tx_buf)
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dma_unmap_single(mdata->dev, trans->tx_dma,
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trans->len, DMA_TO_DEVICE);
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if (trans->rx_buf)
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dma_unmap_single(mdata->dev, trans->rx_dma,
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trans->len, DMA_FROM_DEVICE);
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mtk_spi_slave_disable_dma(mdata);
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mtk_spi_slave_disable_xfer(mdata);
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}
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if ((!(int_status & DMA_DONE_ST)) &&
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((int_status & DATA_DONE_ST) ||
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(int_status & RSTA_DONE_ST))) {
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cnt = trans->len / 4;
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if (trans->rx_buf)
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ioread32_rep(mdata->base + SPIS_RX_DATA_REG,
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trans->rx_buf, cnt);
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remainder = trans->len % 4;
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if (trans->rx_buf && remainder > 0) {
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reg_val = readl(mdata->base + SPIS_RX_DATA_REG);
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memcpy(trans->rx_buf + (cnt * 4),
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®_val, remainder);
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}
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mtk_spi_slave_disable_xfer(mdata);
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}
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if (int_status & CMD_INVALID_ST) {
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dev_warn(&ctlr->dev, "cmd invalid\n");
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return IRQ_NONE;
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}
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mdata->cur_transfer = NULL;
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complete(&mdata->xfer_done);
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return IRQ_HANDLED;
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}
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static int mtk_spi_slave_probe(struct platform_device *pdev)
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{
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struct spi_controller *ctlr;
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struct mtk_spi_slave *mdata;
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int irq, ret;
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const struct of_device_id *of_id;
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ctlr = spi_alloc_slave(&pdev->dev, sizeof(*mdata));
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if (!ctlr) {
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dev_err(&pdev->dev, "failed to alloc spi slave\n");
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return -ENOMEM;
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}
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ctlr->auto_runtime_pm = true;
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ctlr->dev.of_node = pdev->dev.of_node;
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ctlr->mode_bits = SPI_CPOL | SPI_CPHA;
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ctlr->mode_bits |= SPI_LSB_FIRST;
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ctlr->prepare_message = mtk_spi_slave_prepare_message;
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ctlr->transfer_one = mtk_spi_slave_transfer_one;
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ctlr->setup = mtk_spi_slave_setup;
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ctlr->slave_abort = mtk_slave_abort;
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of_id = of_match_node(mtk_spi_slave_of_match, pdev->dev.of_node);
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if (!of_id) {
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dev_err(&pdev->dev, "failed to probe of_node\n");
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ret = -EINVAL;
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goto err_put_ctlr;
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}
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mdata = spi_controller_get_devdata(ctlr);
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mdata->dev_comp = of_id->data;
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if (mdata->dev_comp->must_rx)
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ctlr->flags = SPI_CONTROLLER_MUST_RX;
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platform_set_drvdata(pdev, ctlr);
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init_completion(&mdata->xfer_done);
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mdata->dev = &pdev->dev;
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mdata->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(mdata->base)) {
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ret = PTR_ERR(mdata->base);
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goto err_put_ctlr;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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ret = irq;
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goto err_put_ctlr;
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}
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ret = devm_request_irq(&pdev->dev, irq, mtk_spi_slave_interrupt,
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IRQF_TRIGGER_NONE, dev_name(&pdev->dev), ctlr);
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if (ret) {
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dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
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goto err_put_ctlr;
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}
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mdata->spi_clk = devm_clk_get(&pdev->dev, "spi");
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if (IS_ERR(mdata->spi_clk)) {
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ret = PTR_ERR(mdata->spi_clk);
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dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
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goto err_put_ctlr;
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}
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ret = clk_prepare_enable(mdata->spi_clk);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
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goto err_put_ctlr;
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}
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pm_runtime_enable(&pdev->dev);
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ret = devm_spi_register_controller(&pdev->dev, ctlr);
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if (ret) {
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dev_err(&pdev->dev,
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"failed to register slave controller(%d)\n", ret);
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clk_disable_unprepare(mdata->spi_clk);
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goto err_disable_runtime_pm;
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}
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clk_disable_unprepare(mdata->spi_clk);
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return 0;
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err_disable_runtime_pm:
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pm_runtime_disable(&pdev->dev);
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err_put_ctlr:
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spi_controller_put(ctlr);
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return ret;
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}
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static void mtk_spi_slave_remove(struct platform_device *pdev)
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{
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pm_runtime_disable(&pdev->dev);
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}
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#ifdef CONFIG_PM_SLEEP
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static int mtk_spi_slave_suspend(struct device *dev)
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{
|
|
struct spi_controller *ctlr = dev_get_drvdata(dev);
|
|
struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
|
|
int ret;
|
|
|
|
ret = spi_controller_suspend(ctlr);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (!pm_runtime_suspended(dev))
|
|
clk_disable_unprepare(mdata->spi_clk);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int mtk_spi_slave_resume(struct device *dev)
|
|
{
|
|
struct spi_controller *ctlr = dev_get_drvdata(dev);
|
|
struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
|
|
int ret;
|
|
|
|
if (!pm_runtime_suspended(dev)) {
|
|
ret = clk_prepare_enable(mdata->spi_clk);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
ret = spi_controller_resume(ctlr);
|
|
if (ret < 0)
|
|
clk_disable_unprepare(mdata->spi_clk);
|
|
|
|
return ret;
|
|
}
|
|
#endif /* CONFIG_PM_SLEEP */
|
|
|
|
#ifdef CONFIG_PM
|
|
static int mtk_spi_slave_runtime_suspend(struct device *dev)
|
|
{
|
|
struct spi_controller *ctlr = dev_get_drvdata(dev);
|
|
struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
|
|
|
|
clk_disable_unprepare(mdata->spi_clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_spi_slave_runtime_resume(struct device *dev)
|
|
{
|
|
struct spi_controller *ctlr = dev_get_drvdata(dev);
|
|
struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(mdata->spi_clk);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_PM */
|
|
|
|
static const struct dev_pm_ops mtk_spi_slave_pm = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_slave_suspend, mtk_spi_slave_resume)
|
|
SET_RUNTIME_PM_OPS(mtk_spi_slave_runtime_suspend,
|
|
mtk_spi_slave_runtime_resume, NULL)
|
|
};
|
|
|
|
static struct platform_driver mtk_spi_slave_driver = {
|
|
.driver = {
|
|
.name = "mtk-spi-slave",
|
|
.pm = &mtk_spi_slave_pm,
|
|
.of_match_table = mtk_spi_slave_of_match,
|
|
},
|
|
.probe = mtk_spi_slave_probe,
|
|
.remove_new = mtk_spi_slave_remove,
|
|
};
|
|
|
|
module_platform_driver(mtk_spi_slave_driver);
|
|
|
|
MODULE_DESCRIPTION("MTK SPI Slave Controller driver");
|
|
MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:mtk-spi-slave");
|