734 строки
24 KiB
C
734 строки
24 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* HD-audio core stuff
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*/
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#ifndef __SOUND_HDAUDIO_H
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#define __SOUND_HDAUDIO_H
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/iopoll.h>
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#include <linux/pci.h>
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#include <linux/pm_runtime.h>
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#include <linux/timecounter.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/memalloc.h>
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#include <sound/hda_verbs.h>
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#include <drm/i915_component.h>
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/* codec node id */
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typedef u16 hda_nid_t;
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struct hdac_bus;
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struct hdac_stream;
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struct hdac_device;
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struct hdac_driver;
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struct hdac_widget_tree;
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struct hda_device_id;
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/*
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* exported bus type
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*/
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extern struct bus_type snd_hda_bus_type;
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/*
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* generic arrays
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*/
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struct snd_array {
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unsigned int used;
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unsigned int alloced;
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unsigned int elem_size;
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unsigned int alloc_align;
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void *list;
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};
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/*
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* HD-audio codec base device
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*/
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struct hdac_device {
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struct device dev;
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int type;
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struct hdac_bus *bus;
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unsigned int addr; /* codec address */
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struct list_head list; /* list point for bus codec_list */
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hda_nid_t afg; /* AFG node id */
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hda_nid_t mfg; /* MFG node id */
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/* ids */
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unsigned int vendor_id;
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unsigned int subsystem_id;
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unsigned int revision_id;
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unsigned int afg_function_id;
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unsigned int mfg_function_id;
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unsigned int afg_unsol:1;
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unsigned int mfg_unsol:1;
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unsigned int power_caps; /* FG power caps */
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const char *vendor_name; /* codec vendor name */
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const char *chip_name; /* codec chip name */
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/* verb exec op override */
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int (*exec_verb)(struct hdac_device *dev, unsigned int cmd,
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unsigned int flags, unsigned int *res);
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/* widgets */
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unsigned int num_nodes;
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hda_nid_t start_nid, end_nid;
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/* misc flags */
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atomic_t in_pm; /* suspend/resume being performed */
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/* sysfs */
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struct mutex widget_lock;
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struct hdac_widget_tree *widgets;
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/* regmap */
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struct regmap *regmap;
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struct mutex regmap_lock;
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struct snd_array vendor_verbs;
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bool lazy_cache:1; /* don't wake up for writes */
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bool caps_overwriting:1; /* caps overwrite being in process */
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bool cache_coef:1; /* cache COEF read/write too */
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unsigned int registered:1; /* codec was registered */
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};
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/* device/driver type used for matching */
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enum {
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HDA_DEV_CORE,
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HDA_DEV_LEGACY,
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HDA_DEV_ASOC,
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};
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enum {
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SND_SKL_PCI_BIND_AUTO, /* automatic selection based on pci class */
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SND_SKL_PCI_BIND_LEGACY,/* bind only with legacy driver */
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SND_SKL_PCI_BIND_ASOC /* bind only with ASoC driver */
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};
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/* direction */
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enum {
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HDA_INPUT, HDA_OUTPUT
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};
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#define dev_to_hdac_dev(_dev) container_of(_dev, struct hdac_device, dev)
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int snd_hdac_device_init(struct hdac_device *dev, struct hdac_bus *bus,
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const char *name, unsigned int addr);
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void snd_hdac_device_exit(struct hdac_device *dev);
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int snd_hdac_device_register(struct hdac_device *codec);
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void snd_hdac_device_unregister(struct hdac_device *codec);
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int snd_hdac_device_set_chip_name(struct hdac_device *codec, const char *name);
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int snd_hdac_codec_modalias(const struct hdac_device *hdac, char *buf, size_t size);
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int snd_hdac_refresh_widgets(struct hdac_device *codec);
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int snd_hdac_read(struct hdac_device *codec, hda_nid_t nid,
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unsigned int verb, unsigned int parm, unsigned int *res);
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int _snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, int parm,
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unsigned int *res);
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int snd_hdac_read_parm_uncached(struct hdac_device *codec, hda_nid_t nid,
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int parm);
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int snd_hdac_override_parm(struct hdac_device *codec, hda_nid_t nid,
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unsigned int parm, unsigned int val);
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int snd_hdac_get_connections(struct hdac_device *codec, hda_nid_t nid,
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hda_nid_t *conn_list, int max_conns);
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int snd_hdac_get_sub_nodes(struct hdac_device *codec, hda_nid_t nid,
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hda_nid_t *start_id);
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unsigned int snd_hdac_calc_stream_format(unsigned int rate,
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unsigned int channels,
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snd_pcm_format_t format,
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unsigned int maxbps,
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unsigned short spdif_ctls);
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int snd_hdac_query_supported_pcm(struct hdac_device *codec, hda_nid_t nid,
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u32 *ratesp, u64 *formatsp, unsigned int *bpsp);
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bool snd_hdac_is_supported_format(struct hdac_device *codec, hda_nid_t nid,
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unsigned int format);
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int snd_hdac_codec_read(struct hdac_device *hdac, hda_nid_t nid,
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int flags, unsigned int verb, unsigned int parm);
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int snd_hdac_codec_write(struct hdac_device *hdac, hda_nid_t nid,
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int flags, unsigned int verb, unsigned int parm);
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bool snd_hdac_check_power_state(struct hdac_device *hdac,
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hda_nid_t nid, unsigned int target_state);
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unsigned int snd_hdac_sync_power_state(struct hdac_device *hdac,
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hda_nid_t nid, unsigned int target_state);
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/**
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* snd_hdac_read_parm - read a codec parameter
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* @codec: the codec object
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* @nid: NID to read a parameter
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* @parm: parameter to read
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*
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* Returns -1 for error. If you need to distinguish the error more
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* strictly, use _snd_hdac_read_parm() directly.
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*/
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static inline int snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid,
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int parm)
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{
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unsigned int val;
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return _snd_hdac_read_parm(codec, nid, parm, &val) < 0 ? -1 : val;
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}
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#ifdef CONFIG_PM
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int snd_hdac_power_up(struct hdac_device *codec);
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int snd_hdac_power_down(struct hdac_device *codec);
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int snd_hdac_power_up_pm(struct hdac_device *codec);
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int snd_hdac_power_down_pm(struct hdac_device *codec);
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int snd_hdac_keep_power_up(struct hdac_device *codec);
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/* call this at entering into suspend/resume callbacks in codec driver */
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static inline void snd_hdac_enter_pm(struct hdac_device *codec)
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{
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atomic_inc(&codec->in_pm);
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}
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/* call this at leaving from suspend/resume callbacks in codec driver */
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static inline void snd_hdac_leave_pm(struct hdac_device *codec)
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{
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atomic_dec(&codec->in_pm);
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}
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static inline bool snd_hdac_is_in_pm(struct hdac_device *codec)
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{
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return atomic_read(&codec->in_pm);
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}
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static inline bool snd_hdac_is_power_on(struct hdac_device *codec)
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{
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return !pm_runtime_suspended(&codec->dev);
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}
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#else
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static inline int snd_hdac_power_up(struct hdac_device *codec) { return 0; }
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static inline int snd_hdac_power_down(struct hdac_device *codec) { return 0; }
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static inline int snd_hdac_power_up_pm(struct hdac_device *codec) { return 0; }
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static inline int snd_hdac_power_down_pm(struct hdac_device *codec) { return 0; }
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static inline int snd_hdac_keep_power_up(struct hdac_device *codec) { return 0; }
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static inline void snd_hdac_enter_pm(struct hdac_device *codec) {}
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static inline void snd_hdac_leave_pm(struct hdac_device *codec) {}
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static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) { return false; }
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static inline bool snd_hdac_is_power_on(struct hdac_device *codec) { return true; }
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#endif
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/*
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* HD-audio codec base driver
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*/
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struct hdac_driver {
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struct device_driver driver;
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int type;
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const struct hda_device_id *id_table;
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int (*match)(struct hdac_device *dev, struct hdac_driver *drv);
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void (*unsol_event)(struct hdac_device *dev, unsigned int event);
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/* fields used by ext bus APIs */
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int (*probe)(struct hdac_device *dev);
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int (*remove)(struct hdac_device *dev);
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void (*shutdown)(struct hdac_device *dev);
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};
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#define drv_to_hdac_driver(_drv) container_of(_drv, struct hdac_driver, driver)
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const struct hda_device_id *
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hdac_get_device_id(struct hdac_device *hdev, struct hdac_driver *drv);
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/*
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* Bus verb operators
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*/
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struct hdac_bus_ops {
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/* send a single command */
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int (*command)(struct hdac_bus *bus, unsigned int cmd);
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/* get a response from the last command */
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int (*get_response)(struct hdac_bus *bus, unsigned int addr,
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unsigned int *res);
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/* notify of codec link power-up/down */
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void (*link_power)(struct hdac_device *hdev, bool enable);
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};
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/*
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* ops used for ASoC HDA codec drivers
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*/
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struct hdac_ext_bus_ops {
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int (*hdev_attach)(struct hdac_device *hdev);
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int (*hdev_detach)(struct hdac_device *hdev);
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};
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#define HDA_UNSOL_QUEUE_SIZE 64
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#define HDA_MAX_CODECS 8 /* limit by controller side */
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/*
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* CORB/RIRB
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*
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* Each CORB entry is 4byte, RIRB is 8byte
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*/
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struct hdac_rb {
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__le32 *buf; /* virtual address of CORB/RIRB buffer */
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dma_addr_t addr; /* physical address of CORB/RIRB buffer */
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unsigned short rp, wp; /* RIRB read/write pointers */
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int cmds[HDA_MAX_CODECS]; /* number of pending requests */
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u32 res[HDA_MAX_CODECS]; /* last read value */
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};
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/*
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* HD-audio bus base driver
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*
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* @ppcap: pp capabilities pointer
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* @spbcap: SPIB capabilities pointer
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* @mlcap: MultiLink capabilities pointer
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* @gtscap: gts capabilities pointer
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* @drsmcap: dma resume capabilities pointer
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* @num_streams: streams supported
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* @idx: HDA link index
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* @hlink_list: link list of HDA links
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* @lock: lock for link and display power mgmt
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* @cmd_dma_state: state of cmd DMAs: CORB and RIRB
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*/
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struct hdac_bus {
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struct device *dev;
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const struct hdac_bus_ops *ops;
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const struct hdac_ext_bus_ops *ext_ops;
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/* h/w resources */
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unsigned long addr;
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void __iomem *remap_addr;
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int irq;
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void __iomem *ppcap;
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void __iomem *spbcap;
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void __iomem *mlcap;
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void __iomem *gtscap;
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void __iomem *drsmcap;
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/* codec linked list */
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struct list_head codec_list;
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unsigned int num_codecs;
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/* link caddr -> codec */
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struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1];
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/* unsolicited event queue */
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u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */
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unsigned int unsol_rp, unsol_wp;
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struct work_struct unsol_work;
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/* bit flags of detected codecs */
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unsigned long codec_mask;
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/* bit flags of powered codecs */
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unsigned long codec_powered;
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/* CORB/RIRB */
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struct hdac_rb corb;
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struct hdac_rb rirb;
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unsigned int last_cmd[HDA_MAX_CODECS]; /* last sent command */
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wait_queue_head_t rirb_wq;
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/* CORB/RIRB and position buffers */
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struct snd_dma_buffer rb;
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struct snd_dma_buffer posbuf;
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int dma_type; /* SNDRV_DMA_TYPE_XXX for CORB/RIRB */
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/* hdac_stream linked list */
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struct list_head stream_list;
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/* operation state */
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bool chip_init:1; /* h/w initialized */
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/* behavior flags */
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bool aligned_mmio:1; /* aligned MMIO access */
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bool sync_write:1; /* sync after verb write */
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bool use_posbuf:1; /* use position buffer */
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bool snoop:1; /* enable snooping */
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bool align_bdle_4k:1; /* BDLE align 4K boundary */
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bool reverse_assign:1; /* assign devices in reverse order */
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bool corbrp_self_clear:1; /* CORBRP clears itself after reset */
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bool polling_mode:1;
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bool needs_damn_long_delay:1;
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bool not_use_interrupts:1; /* prohibiting the RIRB IRQ */
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bool access_sdnctl_in_dword:1; /* accessing the sdnctl register by dword */
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int poll_count;
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int bdl_pos_adj; /* BDL position adjustment */
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/* delay time in us for dma stop */
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unsigned int dma_stop_delay;
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/* locks */
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spinlock_t reg_lock;
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struct mutex cmd_mutex;
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struct mutex lock;
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/* DRM component interface */
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struct drm_audio_component *audio_component;
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long display_power_status;
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unsigned long display_power_active;
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/* parameters required for enhanced capabilities */
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int num_streams;
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int idx;
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/* link management */
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struct list_head hlink_list;
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bool cmd_dma_state;
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/* factor used to derive STRIPE control value */
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unsigned int sdo_limit;
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};
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int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev,
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const struct hdac_bus_ops *ops);
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void snd_hdac_bus_exit(struct hdac_bus *bus);
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int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr,
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unsigned int cmd, unsigned int *res);
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void snd_hdac_codec_link_up(struct hdac_device *codec);
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void snd_hdac_codec_link_down(struct hdac_device *codec);
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int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val);
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int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
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unsigned int *res);
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int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus);
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bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset);
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void snd_hdac_bus_stop_chip(struct hdac_bus *bus);
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void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus);
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void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus);
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void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus);
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void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus);
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int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset);
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void snd_hdac_bus_link_power(struct hdac_device *hdev, bool enable);
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void snd_hdac_bus_update_rirb(struct hdac_bus *bus);
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int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
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void (*ack)(struct hdac_bus *,
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struct hdac_stream *));
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int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus);
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void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus);
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#ifdef CONFIG_SND_HDA_ALIGNED_MMIO
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unsigned int snd_hdac_aligned_read(void __iomem *addr, unsigned int mask);
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void snd_hdac_aligned_write(unsigned int val, void __iomem *addr,
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unsigned int mask);
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#define snd_hdac_aligned_mmio(bus) (bus)->aligned_mmio
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#else
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#define snd_hdac_aligned_mmio(bus) false
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#define snd_hdac_aligned_read(addr, mask) 0
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#define snd_hdac_aligned_write(val, addr, mask) do {} while (0)
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#endif
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static inline void snd_hdac_reg_writeb(struct hdac_bus *bus, void __iomem *addr,
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u8 val)
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{
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if (snd_hdac_aligned_mmio(bus))
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snd_hdac_aligned_write(val, addr, 0xff);
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else
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writeb(val, addr);
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}
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static inline void snd_hdac_reg_writew(struct hdac_bus *bus, void __iomem *addr,
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u16 val)
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{
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if (snd_hdac_aligned_mmio(bus))
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snd_hdac_aligned_write(val, addr, 0xffff);
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else
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writew(val, addr);
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}
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static inline u8 snd_hdac_reg_readb(struct hdac_bus *bus, void __iomem *addr)
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{
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return snd_hdac_aligned_mmio(bus) ?
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snd_hdac_aligned_read(addr, 0xff) : readb(addr);
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}
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static inline u16 snd_hdac_reg_readw(struct hdac_bus *bus, void __iomem *addr)
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{
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return snd_hdac_aligned_mmio(bus) ?
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snd_hdac_aligned_read(addr, 0xffff) : readw(addr);
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}
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#define snd_hdac_reg_writel(bus, addr, val) writel(val, addr)
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#define snd_hdac_reg_readl(bus, addr) readl(addr)
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#define snd_hdac_reg_writeq(bus, addr, val) writeq(val, addr)
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#define snd_hdac_reg_readq(bus, addr) readq(addr)
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/*
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* macros for easy use
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*/
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#define _snd_hdac_chip_writeb(chip, reg, value) \
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snd_hdac_reg_writeb(chip, (chip)->remap_addr + (reg), value)
|
|
#define _snd_hdac_chip_readb(chip, reg) \
|
|
snd_hdac_reg_readb(chip, (chip)->remap_addr + (reg))
|
|
#define _snd_hdac_chip_writew(chip, reg, value) \
|
|
snd_hdac_reg_writew(chip, (chip)->remap_addr + (reg), value)
|
|
#define _snd_hdac_chip_readw(chip, reg) \
|
|
snd_hdac_reg_readw(chip, (chip)->remap_addr + (reg))
|
|
#define _snd_hdac_chip_writel(chip, reg, value) \
|
|
snd_hdac_reg_writel(chip, (chip)->remap_addr + (reg), value)
|
|
#define _snd_hdac_chip_readl(chip, reg) \
|
|
snd_hdac_reg_readl(chip, (chip)->remap_addr + (reg))
|
|
|
|
/* read/write a register, pass without AZX_REG_ prefix */
|
|
#define snd_hdac_chip_writel(chip, reg, value) \
|
|
_snd_hdac_chip_writel(chip, AZX_REG_ ## reg, value)
|
|
#define snd_hdac_chip_writew(chip, reg, value) \
|
|
_snd_hdac_chip_writew(chip, AZX_REG_ ## reg, value)
|
|
#define snd_hdac_chip_writeb(chip, reg, value) \
|
|
_snd_hdac_chip_writeb(chip, AZX_REG_ ## reg, value)
|
|
#define snd_hdac_chip_readl(chip, reg) \
|
|
_snd_hdac_chip_readl(chip, AZX_REG_ ## reg)
|
|
#define snd_hdac_chip_readw(chip, reg) \
|
|
_snd_hdac_chip_readw(chip, AZX_REG_ ## reg)
|
|
#define snd_hdac_chip_readb(chip, reg) \
|
|
_snd_hdac_chip_readb(chip, AZX_REG_ ## reg)
|
|
|
|
/* update a register, pass without AZX_REG_ prefix */
|
|
#define snd_hdac_chip_updatel(chip, reg, mask, val) \
|
|
snd_hdac_chip_writel(chip, reg, \
|
|
(snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val))
|
|
#define snd_hdac_chip_updatew(chip, reg, mask, val) \
|
|
snd_hdac_chip_writew(chip, reg, \
|
|
(snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val))
|
|
#define snd_hdac_chip_updateb(chip, reg, mask, val) \
|
|
snd_hdac_chip_writeb(chip, reg, \
|
|
(snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val))
|
|
|
|
/* update register macro */
|
|
#define snd_hdac_updatel(addr, reg, mask, val) \
|
|
writel(((readl(addr + reg) & ~(mask)) | (val)), addr + reg)
|
|
|
|
#define snd_hdac_updatew(addr, reg, mask, val) \
|
|
writew(((readw(addr + reg) & ~(mask)) | (val)), addr + reg)
|
|
|
|
/*
|
|
* HD-audio stream
|
|
*/
|
|
struct hdac_stream {
|
|
struct hdac_bus *bus;
|
|
struct snd_dma_buffer bdl; /* BDL buffer */
|
|
__le32 *posbuf; /* position buffer pointer */
|
|
int direction; /* playback / capture (SNDRV_PCM_STREAM_*) */
|
|
|
|
unsigned int bufsize; /* size of the play buffer in bytes */
|
|
unsigned int period_bytes; /* size of the period in bytes */
|
|
unsigned int frags; /* number for period in the play buffer */
|
|
unsigned int fifo_size; /* FIFO size */
|
|
|
|
void __iomem *sd_addr; /* stream descriptor pointer */
|
|
|
|
void __iomem *spib_addr; /* software position in buffers stream pointer */
|
|
void __iomem *fifo_addr; /* software position Max fifos stream pointer */
|
|
|
|
void __iomem *dpibr_addr; /* DMA position in buffer resume pointer */
|
|
u32 dpib; /* DMA position in buffer */
|
|
u32 lpib; /* Linear position in buffer */
|
|
|
|
u32 sd_int_sta_mask; /* stream int status mask */
|
|
|
|
/* pcm support */
|
|
struct snd_pcm_substream *substream; /* assigned substream,
|
|
* set in PCM open
|
|
*/
|
|
struct snd_compr_stream *cstream;
|
|
unsigned int format_val; /* format value to be set in the
|
|
* controller and the codec
|
|
*/
|
|
unsigned char stream_tag; /* assigned stream */
|
|
unsigned char index; /* stream index */
|
|
int assigned_key; /* last device# key assigned to */
|
|
|
|
bool opened:1;
|
|
bool running:1;
|
|
bool prepared:1;
|
|
bool no_period_wakeup:1;
|
|
bool locked:1;
|
|
bool stripe:1; /* apply stripe control */
|
|
|
|
u64 curr_pos;
|
|
/* timestamp */
|
|
unsigned long start_wallclk; /* start + minimum wallclk */
|
|
unsigned long period_wallclk; /* wallclk for period */
|
|
struct timecounter tc;
|
|
struct cyclecounter cc;
|
|
int delay_negative_threshold;
|
|
|
|
struct list_head list;
|
|
#ifdef CONFIG_SND_HDA_DSP_LOADER
|
|
/* DSP access mutex */
|
|
struct mutex dsp_mutex;
|
|
#endif
|
|
};
|
|
|
|
void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
|
|
int idx, int direction, int tag);
|
|
struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
|
|
struct snd_pcm_substream *substream);
|
|
void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev);
|
|
void snd_hdac_stream_release(struct hdac_stream *azx_dev);
|
|
struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
|
|
int dir, int stream_tag);
|
|
|
|
int snd_hdac_stream_setup(struct hdac_stream *azx_dev);
|
|
void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev);
|
|
int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev);
|
|
int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
|
|
unsigned int format_val);
|
|
void snd_hdac_stream_start(struct hdac_stream *azx_dev);
|
|
void snd_hdac_stream_stop(struct hdac_stream *azx_dev);
|
|
void snd_hdac_stop_streams(struct hdac_bus *bus);
|
|
void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus);
|
|
void snd_hdac_stream_reset(struct hdac_stream *azx_dev);
|
|
void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
|
|
unsigned int streams, unsigned int reg);
|
|
void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
|
|
unsigned int streams);
|
|
void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
|
|
unsigned int streams);
|
|
int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
|
|
struct snd_pcm_substream *substream);
|
|
|
|
void snd_hdac_stream_spbcap_enable(struct hdac_bus *chip,
|
|
bool enable, int index);
|
|
int snd_hdac_stream_set_spib(struct hdac_bus *bus,
|
|
struct hdac_stream *azx_dev, u32 value);
|
|
int snd_hdac_stream_get_spbmaxfifo(struct hdac_bus *bus,
|
|
struct hdac_stream *azx_dev);
|
|
void snd_hdac_stream_drsm_enable(struct hdac_bus *bus,
|
|
bool enable, int index);
|
|
int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev);
|
|
int snd_hdac_stream_set_dpibr(struct hdac_bus *bus,
|
|
struct hdac_stream *azx_dev, u32 value);
|
|
int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value);
|
|
|
|
/*
|
|
* macros for easy use
|
|
*/
|
|
/* read/write a register, pass without AZX_REG_ prefix */
|
|
#define snd_hdac_stream_writel(dev, reg, value) \
|
|
snd_hdac_reg_writel((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)
|
|
#define snd_hdac_stream_writew(dev, reg, value) \
|
|
snd_hdac_reg_writew((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)
|
|
#define snd_hdac_stream_writeb(dev, reg, value) \
|
|
snd_hdac_reg_writeb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)
|
|
#define snd_hdac_stream_readl(dev, reg) \
|
|
snd_hdac_reg_readl((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
|
|
#define snd_hdac_stream_readw(dev, reg) \
|
|
snd_hdac_reg_readw((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
|
|
#define snd_hdac_stream_readb(dev, reg) \
|
|
snd_hdac_reg_readb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
|
|
#define snd_hdac_stream_readb_poll(dev, reg, val, cond, delay_us, timeout_us) \
|
|
read_poll_timeout_atomic(snd_hdac_reg_readb, val, cond, delay_us, timeout_us, \
|
|
false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
|
|
#define snd_hdac_stream_readl_poll(dev, reg, val, cond, delay_us, timeout_us) \
|
|
read_poll_timeout_atomic(snd_hdac_reg_readl, val, cond, delay_us, timeout_us, \
|
|
false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
|
|
|
|
/* update a register, pass without AZX_REG_ prefix */
|
|
#define snd_hdac_stream_updatel(dev, reg, mask, val) \
|
|
snd_hdac_stream_writel(dev, reg, \
|
|
(snd_hdac_stream_readl(dev, reg) & \
|
|
~(mask)) | (val))
|
|
#define snd_hdac_stream_updatew(dev, reg, mask, val) \
|
|
snd_hdac_stream_writew(dev, reg, \
|
|
(snd_hdac_stream_readw(dev, reg) & \
|
|
~(mask)) | (val))
|
|
#define snd_hdac_stream_updateb(dev, reg, mask, val) \
|
|
snd_hdac_stream_writeb(dev, reg, \
|
|
(snd_hdac_stream_readb(dev, reg) & \
|
|
~(mask)) | (val))
|
|
|
|
#ifdef CONFIG_SND_HDA_DSP_LOADER
|
|
/* DSP lock helpers */
|
|
#define snd_hdac_dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
|
|
#define snd_hdac_dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
|
|
#define snd_hdac_dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
|
|
#define snd_hdac_stream_is_locked(dev) ((dev)->locked)
|
|
/* DSP loader helpers */
|
|
int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
|
|
unsigned int byte_size, struct snd_dma_buffer *bufp);
|
|
void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start);
|
|
void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
|
|
struct snd_dma_buffer *dmab);
|
|
#else /* CONFIG_SND_HDA_DSP_LOADER */
|
|
#define snd_hdac_dsp_lock_init(dev) do {} while (0)
|
|
#define snd_hdac_dsp_lock(dev) do {} while (0)
|
|
#define snd_hdac_dsp_unlock(dev) do {} while (0)
|
|
#define snd_hdac_stream_is_locked(dev) 0
|
|
|
|
static inline int
|
|
snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
|
|
unsigned int byte_size, struct snd_dma_buffer *bufp)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
|
|
{
|
|
}
|
|
|
|
static inline void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
|
|
struct snd_dma_buffer *dmab)
|
|
{
|
|
}
|
|
#endif /* CONFIG_SND_HDA_DSP_LOADER */
|
|
|
|
|
|
/*
|
|
* generic array helpers
|
|
*/
|
|
void *snd_array_new(struct snd_array *array);
|
|
void snd_array_free(struct snd_array *array);
|
|
static inline void snd_array_init(struct snd_array *array, unsigned int size,
|
|
unsigned int align)
|
|
{
|
|
array->elem_size = size;
|
|
array->alloc_align = align;
|
|
}
|
|
|
|
static inline void *snd_array_elem(struct snd_array *array, unsigned int idx)
|
|
{
|
|
return array->list + idx * array->elem_size;
|
|
}
|
|
|
|
static inline unsigned int snd_array_index(struct snd_array *array, void *ptr)
|
|
{
|
|
return (unsigned long)(ptr - array->list) / array->elem_size;
|
|
}
|
|
|
|
/* a helper macro to iterate for each snd_array element */
|
|
#define snd_array_for_each(array, idx, ptr) \
|
|
for ((idx) = 0, (ptr) = (array)->list; (idx) < (array)->used; \
|
|
(ptr) = snd_array_elem(array, ++(idx)))
|
|
|
|
/*
|
|
* Device matching
|
|
*/
|
|
|
|
#define HDA_CONTROLLER_IS_HSW(pci) (pci_match_id((struct pci_device_id []){ \
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_0) }, \
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_2) }, \
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_3) }, \
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_BDW) }, \
|
|
{ } \
|
|
}, pci))
|
|
|
|
#define HDA_CONTROLLER_IS_APL(pci) (pci_match_id((struct pci_device_id []){ \
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_APL) }, \
|
|
{ } \
|
|
}, pci))
|
|
|
|
#define HDA_CONTROLLER_IN_GPU(pci) (pci_match_id((struct pci_device_id []){ \
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG1) }, \
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_0) }, \
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_1) }, \
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_2) }, \
|
|
{ } \
|
|
}, pci) || HDA_CONTROLLER_IS_HSW(pci))
|
|
|
|
#endif /* __SOUND_HDAUDIO_H */
|