723 строки
18 KiB
C
723 строки
18 KiB
C
/**
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* @file op_model_p4.c
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* P4 model-specific MSR operations
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*
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* @remark Copyright 2002 OProfile authors
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* @remark Read the file COPYING
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*
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* @author Graydon Hoare
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*/
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#include <linux/oprofile.h>
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#include <linux/smp.h>
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#include <asm/msr.h>
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#include <asm/ptrace.h>
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#include <asm/fixmap.h>
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#include <asm/apic.h>
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#include <asm/nmi.h>
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#include "op_x86_model.h"
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#include "op_counter.h"
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#define NUM_EVENTS 39
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#define NUM_COUNTERS_NON_HT 8
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#define NUM_ESCRS_NON_HT 45
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#define NUM_CCCRS_NON_HT 18
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#define NUM_CONTROLS_NON_HT (NUM_ESCRS_NON_HT + NUM_CCCRS_NON_HT)
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#define NUM_COUNTERS_HT2 4
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#define NUM_ESCRS_HT2 23
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#define NUM_CCCRS_HT2 9
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#define NUM_CONTROLS_HT2 (NUM_ESCRS_HT2 + NUM_CCCRS_HT2)
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static unsigned int num_counters = NUM_COUNTERS_NON_HT;
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static unsigned int num_controls = NUM_CONTROLS_NON_HT;
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/* this has to be checked dynamically since the
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hyper-threadedness of a chip is discovered at
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kernel boot-time. */
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static inline void setup_num_counters(void)
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{
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#ifdef CONFIG_SMP
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if (smp_num_siblings == 2){
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num_counters = NUM_COUNTERS_HT2;
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num_controls = NUM_CONTROLS_HT2;
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}
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#endif
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}
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static int inline addr_increment(void)
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{
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#ifdef CONFIG_SMP
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return smp_num_siblings == 2 ? 2 : 1;
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#else
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return 1;
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#endif
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}
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/* tables to simulate simplified hardware view of p4 registers */
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struct p4_counter_binding {
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int virt_counter;
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int counter_address;
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int cccr_address;
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};
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struct p4_event_binding {
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int escr_select; /* value to put in CCCR */
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int event_select; /* value to put in ESCR */
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struct {
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int virt_counter; /* for this counter... */
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int escr_address; /* use this ESCR */
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} bindings[2];
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};
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/* nb: these CTR_* defines are a duplicate of defines in
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event/i386.p4*events. */
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#define CTR_BPU_0 (1 << 0)
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#define CTR_MS_0 (1 << 1)
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#define CTR_FLAME_0 (1 << 2)
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#define CTR_IQ_4 (1 << 3)
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#define CTR_BPU_2 (1 << 4)
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#define CTR_MS_2 (1 << 5)
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#define CTR_FLAME_2 (1 << 6)
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#define CTR_IQ_5 (1 << 7)
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static struct p4_counter_binding p4_counters [NUM_COUNTERS_NON_HT] = {
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{ CTR_BPU_0, MSR_P4_BPU_PERFCTR0, MSR_P4_BPU_CCCR0 },
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{ CTR_MS_0, MSR_P4_MS_PERFCTR0, MSR_P4_MS_CCCR0 },
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{ CTR_FLAME_0, MSR_P4_FLAME_PERFCTR0, MSR_P4_FLAME_CCCR0 },
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{ CTR_IQ_4, MSR_P4_IQ_PERFCTR4, MSR_P4_IQ_CCCR4 },
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{ CTR_BPU_2, MSR_P4_BPU_PERFCTR2, MSR_P4_BPU_CCCR2 },
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{ CTR_MS_2, MSR_P4_MS_PERFCTR2, MSR_P4_MS_CCCR2 },
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{ CTR_FLAME_2, MSR_P4_FLAME_PERFCTR2, MSR_P4_FLAME_CCCR2 },
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{ CTR_IQ_5, MSR_P4_IQ_PERFCTR5, MSR_P4_IQ_CCCR5 }
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};
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#define NUM_UNUSED_CCCRS NUM_CCCRS_NON_HT - NUM_COUNTERS_NON_HT
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/* p4 event codes in libop/op_event.h are indices into this table. */
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static struct p4_event_binding p4_events[NUM_EVENTS] = {
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{ /* BRANCH_RETIRED */
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0x05, 0x06,
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{ {CTR_IQ_4, MSR_P4_CRU_ESCR2},
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{CTR_IQ_5, MSR_P4_CRU_ESCR3} }
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},
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{ /* MISPRED_BRANCH_RETIRED */
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0x04, 0x03,
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{ { CTR_IQ_4, MSR_P4_CRU_ESCR0},
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{ CTR_IQ_5, MSR_P4_CRU_ESCR1} }
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},
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{ /* TC_DELIVER_MODE */
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0x01, 0x01,
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{ { CTR_MS_0, MSR_P4_TC_ESCR0},
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{ CTR_MS_2, MSR_P4_TC_ESCR1} }
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},
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{ /* BPU_FETCH_REQUEST */
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0x00, 0x03,
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{ { CTR_BPU_0, MSR_P4_BPU_ESCR0},
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{ CTR_BPU_2, MSR_P4_BPU_ESCR1} }
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},
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{ /* ITLB_REFERENCE */
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0x03, 0x18,
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{ { CTR_BPU_0, MSR_P4_ITLB_ESCR0},
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{ CTR_BPU_2, MSR_P4_ITLB_ESCR1} }
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},
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{ /* MEMORY_CANCEL */
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0x05, 0x02,
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{ { CTR_FLAME_0, MSR_P4_DAC_ESCR0},
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{ CTR_FLAME_2, MSR_P4_DAC_ESCR1} }
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},
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{ /* MEMORY_COMPLETE */
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0x02, 0x08,
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{ { CTR_FLAME_0, MSR_P4_SAAT_ESCR0},
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{ CTR_FLAME_2, MSR_P4_SAAT_ESCR1} }
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},
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{ /* LOAD_PORT_REPLAY */
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0x02, 0x04,
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{ { CTR_FLAME_0, MSR_P4_SAAT_ESCR0},
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{ CTR_FLAME_2, MSR_P4_SAAT_ESCR1} }
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},
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{ /* STORE_PORT_REPLAY */
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0x02, 0x05,
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{ { CTR_FLAME_0, MSR_P4_SAAT_ESCR0},
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{ CTR_FLAME_2, MSR_P4_SAAT_ESCR1} }
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},
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{ /* MOB_LOAD_REPLAY */
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0x02, 0x03,
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{ { CTR_BPU_0, MSR_P4_MOB_ESCR0},
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{ CTR_BPU_2, MSR_P4_MOB_ESCR1} }
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},
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{ /* PAGE_WALK_TYPE */
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0x04, 0x01,
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{ { CTR_BPU_0, MSR_P4_PMH_ESCR0},
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{ CTR_BPU_2, MSR_P4_PMH_ESCR1} }
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},
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{ /* BSQ_CACHE_REFERENCE */
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0x07, 0x0c,
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{ { CTR_BPU_0, MSR_P4_BSU_ESCR0},
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{ CTR_BPU_2, MSR_P4_BSU_ESCR1} }
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},
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{ /* IOQ_ALLOCATION */
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0x06, 0x03,
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{ { CTR_BPU_0, MSR_P4_FSB_ESCR0},
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{ 0, 0 } }
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},
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{ /* IOQ_ACTIVE_ENTRIES */
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0x06, 0x1a,
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{ { CTR_BPU_2, MSR_P4_FSB_ESCR1},
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{ 0, 0 } }
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},
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{ /* FSB_DATA_ACTIVITY */
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0x06, 0x17,
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{ { CTR_BPU_0, MSR_P4_FSB_ESCR0},
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{ CTR_BPU_2, MSR_P4_FSB_ESCR1} }
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},
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{ /* BSQ_ALLOCATION */
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0x07, 0x05,
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{ { CTR_BPU_0, MSR_P4_BSU_ESCR0},
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{ 0, 0 } }
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},
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{ /* BSQ_ACTIVE_ENTRIES */
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0x07, 0x06,
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{ { CTR_BPU_2, MSR_P4_BSU_ESCR1 /* guess */},
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{ 0, 0 } }
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},
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{ /* X87_ASSIST */
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0x05, 0x03,
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{ { CTR_IQ_4, MSR_P4_CRU_ESCR2},
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{ CTR_IQ_5, MSR_P4_CRU_ESCR3} }
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},
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{ /* SSE_INPUT_ASSIST */
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0x01, 0x34,
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{ { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
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{ CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
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},
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{ /* PACKED_SP_UOP */
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0x01, 0x08,
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{ { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
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{ CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
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},
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{ /* PACKED_DP_UOP */
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0x01, 0x0c,
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{ { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
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{ CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
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},
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{ /* SCALAR_SP_UOP */
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0x01, 0x0a,
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{ { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
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{ CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
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},
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{ /* SCALAR_DP_UOP */
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0x01, 0x0e,
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{ { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
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{ CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
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},
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{ /* 64BIT_MMX_UOP */
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0x01, 0x02,
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{ { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
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{ CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
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},
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{ /* 128BIT_MMX_UOP */
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0x01, 0x1a,
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{ { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
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{ CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
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},
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{ /* X87_FP_UOP */
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0x01, 0x04,
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{ { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
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{ CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
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},
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{ /* X87_SIMD_MOVES_UOP */
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0x01, 0x2e,
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{ { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
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{ CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
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},
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{ /* MACHINE_CLEAR */
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0x05, 0x02,
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{ { CTR_IQ_4, MSR_P4_CRU_ESCR2},
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{ CTR_IQ_5, MSR_P4_CRU_ESCR3} }
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},
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{ /* GLOBAL_POWER_EVENTS */
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0x06, 0x13 /* older manual says 0x05, newer 0x13 */,
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{ { CTR_BPU_0, MSR_P4_FSB_ESCR0},
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{ CTR_BPU_2, MSR_P4_FSB_ESCR1} }
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},
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{ /* TC_MS_XFER */
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0x00, 0x05,
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{ { CTR_MS_0, MSR_P4_MS_ESCR0},
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{ CTR_MS_2, MSR_P4_MS_ESCR1} }
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},
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{ /* UOP_QUEUE_WRITES */
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0x00, 0x09,
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{ { CTR_MS_0, MSR_P4_MS_ESCR0},
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{ CTR_MS_2, MSR_P4_MS_ESCR1} }
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},
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{ /* FRONT_END_EVENT */
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0x05, 0x08,
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{ { CTR_IQ_4, MSR_P4_CRU_ESCR2},
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{ CTR_IQ_5, MSR_P4_CRU_ESCR3} }
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},
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{ /* EXECUTION_EVENT */
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0x05, 0x0c,
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{ { CTR_IQ_4, MSR_P4_CRU_ESCR2},
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{ CTR_IQ_5, MSR_P4_CRU_ESCR3} }
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},
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{ /* REPLAY_EVENT */
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0x05, 0x09,
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{ { CTR_IQ_4, MSR_P4_CRU_ESCR2},
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{ CTR_IQ_5, MSR_P4_CRU_ESCR3} }
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},
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{ /* INSTR_RETIRED */
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0x04, 0x02,
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{ { CTR_IQ_4, MSR_P4_CRU_ESCR0},
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{ CTR_IQ_5, MSR_P4_CRU_ESCR1} }
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},
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{ /* UOPS_RETIRED */
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0x04, 0x01,
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{ { CTR_IQ_4, MSR_P4_CRU_ESCR0},
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{ CTR_IQ_5, MSR_P4_CRU_ESCR1} }
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},
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{ /* UOP_TYPE */
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0x02, 0x02,
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{ { CTR_IQ_4, MSR_P4_RAT_ESCR0},
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{ CTR_IQ_5, MSR_P4_RAT_ESCR1} }
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},
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{ /* RETIRED_MISPRED_BRANCH_TYPE */
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0x02, 0x05,
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{ { CTR_MS_0, MSR_P4_TBPU_ESCR0},
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{ CTR_MS_2, MSR_P4_TBPU_ESCR1} }
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},
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{ /* RETIRED_BRANCH_TYPE */
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0x02, 0x04,
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{ { CTR_MS_0, MSR_P4_TBPU_ESCR0},
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{ CTR_MS_2, MSR_P4_TBPU_ESCR1} }
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}
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};
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#define MISC_PMC_ENABLED_P(x) ((x) & 1 << 7)
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#define ESCR_RESERVED_BITS 0x80000003
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#define ESCR_CLEAR(escr) ((escr) &= ESCR_RESERVED_BITS)
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#define ESCR_SET_USR_0(escr, usr) ((escr) |= (((usr) & 1) << 2))
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#define ESCR_SET_OS_0(escr, os) ((escr) |= (((os) & 1) << 3))
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#define ESCR_SET_USR_1(escr, usr) ((escr) |= (((usr) & 1)))
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#define ESCR_SET_OS_1(escr, os) ((escr) |= (((os) & 1) << 1))
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#define ESCR_SET_EVENT_SELECT(escr, sel) ((escr) |= (((sel) & 0x3f) << 25))
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#define ESCR_SET_EVENT_MASK(escr, mask) ((escr) |= (((mask) & 0xffff) << 9))
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#define ESCR_READ(escr,high,ev,i) do {rdmsr(ev->bindings[(i)].escr_address, (escr), (high));} while (0)
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#define ESCR_WRITE(escr,high,ev,i) do {wrmsr(ev->bindings[(i)].escr_address, (escr), (high));} while (0)
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#define CCCR_RESERVED_BITS 0x38030FFF
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#define CCCR_CLEAR(cccr) ((cccr) &= CCCR_RESERVED_BITS)
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#define CCCR_SET_REQUIRED_BITS(cccr) ((cccr) |= 0x00030000)
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#define CCCR_SET_ESCR_SELECT(cccr, sel) ((cccr) |= (((sel) & 0x07) << 13))
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#define CCCR_SET_PMI_OVF_0(cccr) ((cccr) |= (1<<26))
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#define CCCR_SET_PMI_OVF_1(cccr) ((cccr) |= (1<<27))
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#define CCCR_SET_ENABLE(cccr) ((cccr) |= (1<<12))
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#define CCCR_SET_DISABLE(cccr) ((cccr) &= ~(1<<12))
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#define CCCR_READ(low, high, i) do {rdmsr(p4_counters[(i)].cccr_address, (low), (high));} while (0)
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#define CCCR_WRITE(low, high, i) do {wrmsr(p4_counters[(i)].cccr_address, (low), (high));} while (0)
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#define CCCR_OVF_P(cccr) ((cccr) & (1U<<31))
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#define CCCR_CLEAR_OVF(cccr) ((cccr) &= (~(1U<<31)))
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#define CTRL_IS_RESERVED(msrs,c) (msrs->controls[(c)].addr ? 1 : 0)
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#define CTR_IS_RESERVED(msrs,c) (msrs->counters[(c)].addr ? 1 : 0)
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#define CTR_READ(l,h,i) do {rdmsr(p4_counters[(i)].counter_address, (l), (h));} while (0)
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#define CTR_WRITE(l,i) do {wrmsr(p4_counters[(i)].counter_address, -(u32)(l), -1);} while (0)
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#define CTR_OVERFLOW_P(ctr) (!((ctr) & 0x80000000))
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/* this assigns a "stagger" to the current CPU, which is used throughout
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the code in this module as an extra array offset, to select the "even"
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or "odd" part of all the divided resources. */
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static unsigned int get_stagger(void)
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{
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#ifdef CONFIG_SMP
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int cpu = smp_processor_id();
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return (cpu != first_cpu(per_cpu(cpu_sibling_map, cpu)));
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#endif
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return 0;
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}
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/* finally, mediate access to a real hardware counter
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by passing a "virtual" counter numer to this macro,
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along with your stagger setting. */
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#define VIRT_CTR(stagger, i) ((i) + ((num_counters) * (stagger)))
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static unsigned long reset_value[NUM_COUNTERS_NON_HT];
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static void p4_fill_in_addresses(struct op_msrs * const msrs)
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{
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unsigned int i;
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unsigned int addr, cccraddr, stag;
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setup_num_counters();
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stag = get_stagger();
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/* initialize some registers */
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for (i = 0; i < num_counters; ++i) {
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msrs->counters[i].addr = 0;
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}
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for (i = 0; i < num_controls; ++i) {
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msrs->controls[i].addr = 0;
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}
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/* the counter & cccr registers we pay attention to */
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for (i = 0; i < num_counters; ++i) {
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addr = p4_counters[VIRT_CTR(stag, i)].counter_address;
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cccraddr = p4_counters[VIRT_CTR(stag, i)].cccr_address;
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if (reserve_perfctr_nmi(addr)){
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msrs->counters[i].addr = addr;
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msrs->controls[i].addr = cccraddr;
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}
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}
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/* 43 ESCR registers in three or four discontiguous group */
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for (addr = MSR_P4_BSU_ESCR0 + stag;
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addr < MSR_P4_IQ_ESCR0; ++i, addr += addr_increment()) {
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if (reserve_evntsel_nmi(addr))
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msrs->controls[i].addr = addr;
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}
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/* no IQ_ESCR0/1 on some models, we save a seconde time BSU_ESCR0/1
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* to avoid special case in nmi_{save|restore}_registers() */
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if (boot_cpu_data.x86_model >= 0x3) {
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for (addr = MSR_P4_BSU_ESCR0 + stag;
|
|
addr <= MSR_P4_BSU_ESCR1; ++i, addr += addr_increment()) {
|
|
if (reserve_evntsel_nmi(addr))
|
|
msrs->controls[i].addr = addr;
|
|
}
|
|
} else {
|
|
for (addr = MSR_P4_IQ_ESCR0 + stag;
|
|
addr <= MSR_P4_IQ_ESCR1; ++i, addr += addr_increment()) {
|
|
if (reserve_evntsel_nmi(addr))
|
|
msrs->controls[i].addr = addr;
|
|
}
|
|
}
|
|
|
|
for (addr = MSR_P4_RAT_ESCR0 + stag;
|
|
addr <= MSR_P4_SSU_ESCR0; ++i, addr += addr_increment()) {
|
|
if (reserve_evntsel_nmi(addr))
|
|
msrs->controls[i].addr = addr;
|
|
}
|
|
|
|
for (addr = MSR_P4_MS_ESCR0 + stag;
|
|
addr <= MSR_P4_TC_ESCR1; ++i, addr += addr_increment()) {
|
|
if (reserve_evntsel_nmi(addr))
|
|
msrs->controls[i].addr = addr;
|
|
}
|
|
|
|
for (addr = MSR_P4_IX_ESCR0 + stag;
|
|
addr <= MSR_P4_CRU_ESCR3; ++i, addr += addr_increment()) {
|
|
if (reserve_evntsel_nmi(addr))
|
|
msrs->controls[i].addr = addr;
|
|
}
|
|
|
|
/* there are 2 remaining non-contiguously located ESCRs */
|
|
|
|
if (num_counters == NUM_COUNTERS_NON_HT) {
|
|
/* standard non-HT CPUs handle both remaining ESCRs*/
|
|
if (reserve_evntsel_nmi(MSR_P4_CRU_ESCR5))
|
|
msrs->controls[i++].addr = MSR_P4_CRU_ESCR5;
|
|
if (reserve_evntsel_nmi(MSR_P4_CRU_ESCR4))
|
|
msrs->controls[i++].addr = MSR_P4_CRU_ESCR4;
|
|
|
|
} else if (stag == 0) {
|
|
/* HT CPUs give the first remainder to the even thread, as
|
|
the 32nd control register */
|
|
if (reserve_evntsel_nmi(MSR_P4_CRU_ESCR4))
|
|
msrs->controls[i++].addr = MSR_P4_CRU_ESCR4;
|
|
|
|
} else {
|
|
/* and two copies of the second to the odd thread,
|
|
for the 22st and 23nd control registers */
|
|
if (reserve_evntsel_nmi(MSR_P4_CRU_ESCR5)) {
|
|
msrs->controls[i++].addr = MSR_P4_CRU_ESCR5;
|
|
msrs->controls[i++].addr = MSR_P4_CRU_ESCR5;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
static void pmc_setup_one_p4_counter(unsigned int ctr)
|
|
{
|
|
int i;
|
|
int const maxbind = 2;
|
|
unsigned int cccr = 0;
|
|
unsigned int escr = 0;
|
|
unsigned int high = 0;
|
|
unsigned int counter_bit;
|
|
struct p4_event_binding *ev = NULL;
|
|
unsigned int stag;
|
|
|
|
stag = get_stagger();
|
|
|
|
/* convert from counter *number* to counter *bit* */
|
|
counter_bit = 1 << VIRT_CTR(stag, ctr);
|
|
|
|
/* find our event binding structure. */
|
|
if (counter_config[ctr].event <= 0 || counter_config[ctr].event > NUM_EVENTS) {
|
|
printk(KERN_ERR
|
|
"oprofile: P4 event code 0x%lx out of range\n",
|
|
counter_config[ctr].event);
|
|
return;
|
|
}
|
|
|
|
ev = &(p4_events[counter_config[ctr].event - 1]);
|
|
|
|
for (i = 0; i < maxbind; i++) {
|
|
if (ev->bindings[i].virt_counter & counter_bit) {
|
|
|
|
/* modify ESCR */
|
|
ESCR_READ(escr, high, ev, i);
|
|
ESCR_CLEAR(escr);
|
|
if (stag == 0) {
|
|
ESCR_SET_USR_0(escr, counter_config[ctr].user);
|
|
ESCR_SET_OS_0(escr, counter_config[ctr].kernel);
|
|
} else {
|
|
ESCR_SET_USR_1(escr, counter_config[ctr].user);
|
|
ESCR_SET_OS_1(escr, counter_config[ctr].kernel);
|
|
}
|
|
ESCR_SET_EVENT_SELECT(escr, ev->event_select);
|
|
ESCR_SET_EVENT_MASK(escr, counter_config[ctr].unit_mask);
|
|
ESCR_WRITE(escr, high, ev, i);
|
|
|
|
/* modify CCCR */
|
|
CCCR_READ(cccr, high, VIRT_CTR(stag, ctr));
|
|
CCCR_CLEAR(cccr);
|
|
CCCR_SET_REQUIRED_BITS(cccr);
|
|
CCCR_SET_ESCR_SELECT(cccr, ev->escr_select);
|
|
if (stag == 0) {
|
|
CCCR_SET_PMI_OVF_0(cccr);
|
|
} else {
|
|
CCCR_SET_PMI_OVF_1(cccr);
|
|
}
|
|
CCCR_WRITE(cccr, high, VIRT_CTR(stag, ctr));
|
|
return;
|
|
}
|
|
}
|
|
|
|
printk(KERN_ERR
|
|
"oprofile: P4 event code 0x%lx no binding, stag %d ctr %d\n",
|
|
counter_config[ctr].event, stag, ctr);
|
|
}
|
|
|
|
|
|
static void p4_setup_ctrs(struct op_msrs const * const msrs)
|
|
{
|
|
unsigned int i;
|
|
unsigned int low, high;
|
|
unsigned int stag;
|
|
|
|
stag = get_stagger();
|
|
|
|
rdmsr(MSR_IA32_MISC_ENABLE, low, high);
|
|
if (! MISC_PMC_ENABLED_P(low)) {
|
|
printk(KERN_ERR "oprofile: P4 PMC not available\n");
|
|
return;
|
|
}
|
|
|
|
/* clear the cccrs we will use */
|
|
for (i = 0 ; i < num_counters ; i++) {
|
|
if (unlikely(!CTRL_IS_RESERVED(msrs,i)))
|
|
continue;
|
|
rdmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high);
|
|
CCCR_CLEAR(low);
|
|
CCCR_SET_REQUIRED_BITS(low);
|
|
wrmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high);
|
|
}
|
|
|
|
/* clear all escrs (including those outside our concern) */
|
|
for (i = num_counters; i < num_controls; i++) {
|
|
if (unlikely(!CTRL_IS_RESERVED(msrs,i)))
|
|
continue;
|
|
wrmsr(msrs->controls[i].addr, 0, 0);
|
|
}
|
|
|
|
/* setup all counters */
|
|
for (i = 0 ; i < num_counters ; ++i) {
|
|
if ((counter_config[i].enabled) && (CTRL_IS_RESERVED(msrs,i))) {
|
|
reset_value[i] = counter_config[i].count;
|
|
pmc_setup_one_p4_counter(i);
|
|
CTR_WRITE(counter_config[i].count, VIRT_CTR(stag, i));
|
|
} else {
|
|
reset_value[i] = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
static int p4_check_ctrs(struct pt_regs * const regs,
|
|
struct op_msrs const * const msrs)
|
|
{
|
|
unsigned long ctr, low, high, stag, real;
|
|
int i;
|
|
|
|
stag = get_stagger();
|
|
|
|
for (i = 0; i < num_counters; ++i) {
|
|
|
|
if (!reset_value[i])
|
|
continue;
|
|
|
|
/*
|
|
* there is some eccentricity in the hardware which
|
|
* requires that we perform 2 extra corrections:
|
|
*
|
|
* - check both the CCCR:OVF flag for overflow and the
|
|
* counter high bit for un-flagged overflows.
|
|
*
|
|
* - write the counter back twice to ensure it gets
|
|
* updated properly.
|
|
*
|
|
* the former seems to be related to extra NMIs happening
|
|
* during the current NMI; the latter is reported as errata
|
|
* N15 in intel doc 249199-029, pentium 4 specification
|
|
* update, though their suggested work-around does not
|
|
* appear to solve the problem.
|
|
*/
|
|
|
|
real = VIRT_CTR(stag, i);
|
|
|
|
CCCR_READ(low, high, real);
|
|
CTR_READ(ctr, high, real);
|
|
if (CCCR_OVF_P(low) || CTR_OVERFLOW_P(ctr)) {
|
|
oprofile_add_sample(regs, i);
|
|
CTR_WRITE(reset_value[i], real);
|
|
CCCR_CLEAR_OVF(low);
|
|
CCCR_WRITE(low, high, real);
|
|
CTR_WRITE(reset_value[i], real);
|
|
}
|
|
}
|
|
|
|
/* P4 quirk: you have to re-unmask the apic vector */
|
|
apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
|
|
|
|
/* See op_model_ppro.c */
|
|
return 1;
|
|
}
|
|
|
|
|
|
static void p4_start(struct op_msrs const * const msrs)
|
|
{
|
|
unsigned int low, high, stag;
|
|
int i;
|
|
|
|
stag = get_stagger();
|
|
|
|
for (i = 0; i < num_counters; ++i) {
|
|
if (!reset_value[i])
|
|
continue;
|
|
CCCR_READ(low, high, VIRT_CTR(stag, i));
|
|
CCCR_SET_ENABLE(low);
|
|
CCCR_WRITE(low, high, VIRT_CTR(stag, i));
|
|
}
|
|
}
|
|
|
|
|
|
static void p4_stop(struct op_msrs const * const msrs)
|
|
{
|
|
unsigned int low, high, stag;
|
|
int i;
|
|
|
|
stag = get_stagger();
|
|
|
|
for (i = 0; i < num_counters; ++i) {
|
|
if (!reset_value[i])
|
|
continue;
|
|
CCCR_READ(low, high, VIRT_CTR(stag, i));
|
|
CCCR_SET_DISABLE(low);
|
|
CCCR_WRITE(low, high, VIRT_CTR(stag, i));
|
|
}
|
|
}
|
|
|
|
static void p4_shutdown(struct op_msrs const * const msrs)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0 ; i < num_counters ; ++i) {
|
|
if (CTR_IS_RESERVED(msrs,i))
|
|
release_perfctr_nmi(msrs->counters[i].addr);
|
|
}
|
|
/* some of the control registers are specially reserved in
|
|
* conjunction with the counter registers (hence the starting offset).
|
|
* This saves a few bits.
|
|
*/
|
|
for (i = num_counters ; i < num_controls ; ++i) {
|
|
if (CTRL_IS_RESERVED(msrs,i))
|
|
release_evntsel_nmi(msrs->controls[i].addr);
|
|
}
|
|
}
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
struct op_x86_model_spec const op_p4_ht2_spec = {
|
|
.num_counters = NUM_COUNTERS_HT2,
|
|
.num_controls = NUM_CONTROLS_HT2,
|
|
.fill_in_addresses = &p4_fill_in_addresses,
|
|
.setup_ctrs = &p4_setup_ctrs,
|
|
.check_ctrs = &p4_check_ctrs,
|
|
.start = &p4_start,
|
|
.stop = &p4_stop,
|
|
.shutdown = &p4_shutdown
|
|
};
|
|
#endif
|
|
|
|
struct op_x86_model_spec const op_p4_spec = {
|
|
.num_counters = NUM_COUNTERS_NON_HT,
|
|
.num_controls = NUM_CONTROLS_NON_HT,
|
|
.fill_in_addresses = &p4_fill_in_addresses,
|
|
.setup_ctrs = &p4_setup_ctrs,
|
|
.check_ctrs = &p4_check_ctrs,
|
|
.start = &p4_start,
|
|
.stop = &p4_stop,
|
|
.shutdown = &p4_shutdown
|
|
};
|