873 строки
21 KiB
C
873 строки
21 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* arch/arm/mach-at91/pm.c
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* AT91 Power Management
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*
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* Copyright (C) 2005 David Brownell
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*/
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#include <linux/genalloc.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/parser.h>
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#include <linux/suspend.h>
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#include <linux/clk/at91_pmc.h>
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#include <asm/cacheflush.h>
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#include <asm/fncpy.h>
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#include <asm/system_misc.h>
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#include <asm/suspend.h>
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#include "generic.h"
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#include "pm.h"
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/*
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* FIXME: this is needed to communicate between the pinctrl driver and
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* the PM implementation in the machine. Possibly part of the PM
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* implementation should be moved down into the pinctrl driver and get
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* called as part of the generic suspend/resume path.
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*/
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#ifdef CONFIG_PINCTRL_AT91
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extern void at91_pinctrl_gpio_suspend(void);
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extern void at91_pinctrl_gpio_resume(void);
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#endif
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struct at91_soc_pm {
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int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
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int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
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const struct of_device_id *ws_ids;
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struct at91_pm_data data;
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};
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static struct at91_soc_pm soc_pm = {
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.data = {
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.standby_mode = AT91_PM_STANDBY,
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.suspend_mode = AT91_PM_ULP0,
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},
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};
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static const match_table_t pm_modes __initconst = {
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{ AT91_PM_STANDBY, "standby" },
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{ AT91_PM_ULP0, "ulp0" },
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{ AT91_PM_ULP1, "ulp1" },
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{ AT91_PM_BACKUP, "backup" },
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{ -1, NULL },
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};
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#define at91_ramc_read(id, field) \
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__raw_readl(soc_pm.data.ramc[id] + field)
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#define at91_ramc_write(id, field, value) \
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__raw_writel(value, soc_pm.data.ramc[id] + field)
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static int at91_pm_valid_state(suspend_state_t state)
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{
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switch (state) {
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case PM_SUSPEND_ON:
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case PM_SUSPEND_STANDBY:
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case PM_SUSPEND_MEM:
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return 1;
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default:
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return 0;
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}
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}
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static int canary = 0xA5A5A5A5;
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static struct at91_pm_bu {
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int suspended;
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unsigned long reserved;
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phys_addr_t canary;
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phys_addr_t resume;
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} *pm_bu;
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struct wakeup_source_info {
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unsigned int pmc_fsmr_bit;
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unsigned int shdwc_mr_bit;
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bool set_polarity;
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};
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static const struct wakeup_source_info ws_info[] = {
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{ .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true },
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{ .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) },
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{ .pmc_fsmr_bit = AT91_PMC_USBAL },
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{ .pmc_fsmr_bit = AT91_PMC_SDMMC_CD },
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{ .pmc_fsmr_bit = AT91_PMC_RTTAL },
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{ .pmc_fsmr_bit = AT91_PMC_RXLP_MCE },
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};
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static const struct of_device_id sama5d2_ws_ids[] = {
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{ .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
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{ .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] },
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{ .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
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{ .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
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{ .compatible = "usb-ohci", .data = &ws_info[2] },
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{ .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
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{ .compatible = "usb-ehci", .data = &ws_info[2] },
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{ .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] },
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{ /* sentinel */ }
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};
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static const struct of_device_id sam9x60_ws_ids[] = {
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{ .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] },
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{ .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
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{ .compatible = "usb-ohci", .data = &ws_info[2] },
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{ .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
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{ .compatible = "usb-ehci", .data = &ws_info[2] },
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{ .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] },
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{ .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] },
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{ /* sentinel */ }
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};
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static int at91_pm_config_ws(unsigned int pm_mode, bool set)
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{
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const struct wakeup_source_info *wsi;
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const struct of_device_id *match;
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struct platform_device *pdev;
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struct device_node *np;
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unsigned int mode = 0, polarity = 0, val = 0;
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if (pm_mode != AT91_PM_ULP1)
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return 0;
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if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids)
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return -EPERM;
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if (!set) {
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writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
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return 0;
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}
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if (soc_pm.config_shdwc_ws)
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soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity);
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/* SHDWC.MR */
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val = readl(soc_pm.data.shdwc + 0x04);
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/* Loop through defined wakeup sources. */
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for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) {
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pdev = of_find_device_by_node(np);
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if (!pdev)
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continue;
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if (device_may_wakeup(&pdev->dev)) {
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wsi = match->data;
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/* Check if enabled on SHDWC. */
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if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit))
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goto put_device;
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mode |= wsi->pmc_fsmr_bit;
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if (wsi->set_polarity)
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polarity |= wsi->pmc_fsmr_bit;
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}
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put_device:
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put_device(&pdev->dev);
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}
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if (mode) {
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if (soc_pm.config_pmc_ws)
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soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity);
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} else {
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pr_err("AT91: PM: no ULP1 wakeup sources found!");
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}
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return mode ? 0 : -EPERM;
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}
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static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode,
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u32 *polarity)
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{
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u32 val;
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/* SHDWC.WUIR */
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val = readl(shdwc + 0x0c);
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*mode |= (val & 0x3ff);
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*polarity |= ((val >> 16) & 0x3ff);
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return 0;
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}
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static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
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{
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writel(mode, pmc + AT91_PMC_FSMR);
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writel(polarity, pmc + AT91_PMC_FSPR);
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return 0;
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}
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static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
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{
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writel(mode, pmc + AT91_PMC_FSMR);
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return 0;
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}
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/*
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* Called after processes are frozen, but before we shutdown devices.
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*/
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static int at91_pm_begin(suspend_state_t state)
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{
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switch (state) {
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case PM_SUSPEND_MEM:
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soc_pm.data.mode = soc_pm.data.suspend_mode;
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break;
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case PM_SUSPEND_STANDBY:
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soc_pm.data.mode = soc_pm.data.standby_mode;
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break;
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default:
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soc_pm.data.mode = -1;
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}
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return at91_pm_config_ws(soc_pm.data.mode, true);
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}
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/*
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* Verify that all the clocks are correct before entering
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* slow-clock mode.
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*/
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static int at91_pm_verify_clocks(void)
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{
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unsigned long scsr;
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int i;
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scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR);
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/* USB must not be using PLLB */
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if ((scsr & soc_pm.data.uhp_udp_mask) != 0) {
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pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
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return 0;
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}
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/* PCK0..PCK3 must be disabled, or configured to use clk32k */
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for (i = 0; i < 4; i++) {
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u32 css;
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if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
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continue;
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css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
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if (css != AT91_PMC_CSS_SLOW) {
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pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
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return 0;
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}
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}
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return 1;
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}
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/*
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* Call this from platform driver suspend() to see how deeply to suspend.
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* For example, some controllers (like OHCI) need one of the PLL clocks
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* in order to act as a wakeup source, and those are not available when
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* going into slow clock mode.
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*
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* REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
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* the very same problem (but not using at91 main_clk), and it'd be better
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* to add one generic API rather than lots of platform-specific ones.
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*/
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int at91_suspend_entering_slow_clock(void)
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{
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return (soc_pm.data.mode >= AT91_PM_ULP0);
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}
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EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
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static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
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extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
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extern u32 at91_pm_suspend_in_sram_sz;
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static int at91_suspend_finish(unsigned long val)
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{
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flush_cache_all();
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outer_disable();
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at91_suspend_sram_fn(&soc_pm.data);
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return 0;
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}
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static void at91_pm_suspend(suspend_state_t state)
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{
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if (soc_pm.data.mode == AT91_PM_BACKUP) {
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pm_bu->suspended = 1;
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cpu_suspend(0, at91_suspend_finish);
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/* The SRAM is lost between suspend cycles */
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at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
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&at91_pm_suspend_in_sram,
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at91_pm_suspend_in_sram_sz);
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} else {
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at91_suspend_finish(0);
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}
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outer_resume();
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}
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/*
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* STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
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* event sources; and reduces DRAM power. But otherwise it's identical to
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* PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
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*
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* AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must
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* suspend more deeply, the master clock switches to the clk32k and turns off
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* the main oscillator
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*
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* AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
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*/
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static int at91_pm_enter(suspend_state_t state)
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{
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#ifdef CONFIG_PINCTRL_AT91
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at91_pinctrl_gpio_suspend();
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#endif
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switch (state) {
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case PM_SUSPEND_MEM:
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case PM_SUSPEND_STANDBY:
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/*
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* Ensure that clocks are in a valid state.
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*/
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if (soc_pm.data.mode >= AT91_PM_ULP0 &&
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!at91_pm_verify_clocks())
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goto error;
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at91_pm_suspend(state);
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break;
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case PM_SUSPEND_ON:
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cpu_do_idle();
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break;
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default:
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pr_debug("AT91: PM - bogus suspend state %d\n", state);
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goto error;
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}
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error:
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#ifdef CONFIG_PINCTRL_AT91
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at91_pinctrl_gpio_resume();
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#endif
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return 0;
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}
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/*
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* Called right prior to thawing processes.
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*/
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static void at91_pm_end(void)
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{
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at91_pm_config_ws(soc_pm.data.mode, false);
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}
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static const struct platform_suspend_ops at91_pm_ops = {
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.valid = at91_pm_valid_state,
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.begin = at91_pm_begin,
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.enter = at91_pm_enter,
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.end = at91_pm_end,
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};
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static struct platform_device at91_cpuidle_device = {
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.name = "cpuidle-at91",
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};
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/*
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* The AT91RM9200 goes into self-refresh mode with this command, and will
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* terminate self-refresh automatically on the next SDRAM access.
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*
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* Self-refresh mode is exited as soon as a memory access is made, but we don't
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* know for sure when that happens. However, we need to restore the low-power
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* mode if it was enabled before going idle. Restoring low-power mode while
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* still in self-refresh is "not recommended", but seems to work.
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*/
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static void at91rm9200_standby(void)
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{
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asm volatile(
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"b 1f\n\t"
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".align 5\n\t"
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"1: mcr p15, 0, %0, c7, c10, 4\n\t"
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" str %2, [%1, %3]\n\t"
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" mcr p15, 0, %0, c7, c0, 4\n\t"
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:
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: "r" (0), "r" (soc_pm.data.ramc[0]),
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"r" (1), "r" (AT91_MC_SDRAMC_SRR));
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}
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/* We manage both DDRAM/SDRAM controllers, we need more than one value to
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* remember.
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*/
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static void at91_ddr_standby(void)
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{
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/* Those two values allow us to delay self-refresh activation
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* to the maximum. */
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u32 lpr0, lpr1 = 0;
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u32 mdr, saved_mdr0, saved_mdr1 = 0;
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u32 saved_lpr0, saved_lpr1 = 0;
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/* LPDDR1 --> force DDR2 mode during self-refresh */
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saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
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if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
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mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
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mdr |= AT91_DDRSDRC_MD_DDR2;
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at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
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}
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if (soc_pm.data.ramc[1]) {
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saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
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lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
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lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
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saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
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if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
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mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
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mdr |= AT91_DDRSDRC_MD_DDR2;
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at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
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}
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}
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saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
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lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
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lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
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/* self-refresh mode now */
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at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
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if (soc_pm.data.ramc[1])
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at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
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cpu_do_idle();
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at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
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at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
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if (soc_pm.data.ramc[1]) {
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at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
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at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
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}
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}
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static void sama5d3_ddr_standby(void)
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{
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u32 lpr0;
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u32 saved_lpr0;
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saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
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lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
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lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
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at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
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cpu_do_idle();
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at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
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}
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/* We manage both DDRAM/SDRAM controllers, we need more than one value to
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* remember.
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*/
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static void at91sam9_sdram_standby(void)
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{
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u32 lpr0, lpr1 = 0;
|
|
u32 saved_lpr0, saved_lpr1 = 0;
|
|
|
|
if (soc_pm.data.ramc[1]) {
|
|
saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
|
|
lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
|
|
lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
|
|
}
|
|
|
|
saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
|
|
lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
|
|
lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
|
|
|
|
/* self-refresh mode now */
|
|
at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
|
|
if (soc_pm.data.ramc[1])
|
|
at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
|
|
|
|
cpu_do_idle();
|
|
|
|
at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
|
|
if (soc_pm.data.ramc[1])
|
|
at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
|
|
}
|
|
|
|
struct ramc_info {
|
|
void (*idle)(void);
|
|
unsigned int memctrl;
|
|
};
|
|
|
|
static const struct ramc_info ramc_infos[] __initconst = {
|
|
{ .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
|
|
{ .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
|
|
{ .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
|
|
{ .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
|
|
};
|
|
|
|
static const struct of_device_id ramc_ids[] __initconst = {
|
|
{ .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
|
|
{ .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
|
|
{ .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
|
|
{ .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
|
|
{ /*sentinel*/ }
|
|
};
|
|
|
|
static __init void at91_dt_ramc(void)
|
|
{
|
|
struct device_node *np;
|
|
const struct of_device_id *of_id;
|
|
int idx = 0;
|
|
void *standby = NULL;
|
|
const struct ramc_info *ramc;
|
|
|
|
for_each_matching_node_and_match(np, ramc_ids, &of_id) {
|
|
soc_pm.data.ramc[idx] = of_iomap(np, 0);
|
|
if (!soc_pm.data.ramc[idx])
|
|
panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
|
|
|
|
ramc = of_id->data;
|
|
if (!standby)
|
|
standby = ramc->idle;
|
|
soc_pm.data.memctrl = ramc->memctrl;
|
|
|
|
idx++;
|
|
}
|
|
|
|
if (!idx)
|
|
panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
|
|
|
|
if (!standby) {
|
|
pr_warn("ramc no standby function available\n");
|
|
return;
|
|
}
|
|
|
|
at91_cpuidle_device.dev.platform_data = standby;
|
|
}
|
|
|
|
static void at91rm9200_idle(void)
|
|
{
|
|
/*
|
|
* Disable the processor clock. The processor will be automatically
|
|
* re-enabled by an interrupt or by a reset.
|
|
*/
|
|
writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
|
|
}
|
|
|
|
static void at91sam9x60_idle(void)
|
|
{
|
|
cpu_do_idle();
|
|
}
|
|
|
|
static void at91sam9_idle(void)
|
|
{
|
|
writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
|
|
cpu_do_idle();
|
|
}
|
|
|
|
static void __init at91_pm_sram_init(void)
|
|
{
|
|
struct gen_pool *sram_pool;
|
|
phys_addr_t sram_pbase;
|
|
unsigned long sram_base;
|
|
struct device_node *node;
|
|
struct platform_device *pdev = NULL;
|
|
|
|
for_each_compatible_node(node, NULL, "mmio-sram") {
|
|
pdev = of_find_device_by_node(node);
|
|
if (pdev) {
|
|
of_node_put(node);
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!pdev) {
|
|
pr_warn("%s: failed to find sram device!\n", __func__);
|
|
return;
|
|
}
|
|
|
|
sram_pool = gen_pool_get(&pdev->dev, NULL);
|
|
if (!sram_pool) {
|
|
pr_warn("%s: sram pool unavailable!\n", __func__);
|
|
return;
|
|
}
|
|
|
|
sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
|
|
if (!sram_base) {
|
|
pr_warn("%s: unable to alloc sram!\n", __func__);
|
|
return;
|
|
}
|
|
|
|
sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
|
|
at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
|
|
at91_pm_suspend_in_sram_sz, false);
|
|
if (!at91_suspend_sram_fn) {
|
|
pr_warn("SRAM: Could not map\n");
|
|
return;
|
|
}
|
|
|
|
/* Copy the pm suspend handler to SRAM */
|
|
at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
|
|
&at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
|
|
}
|
|
|
|
static bool __init at91_is_pm_mode_active(int pm_mode)
|
|
{
|
|
return (soc_pm.data.standby_mode == pm_mode ||
|
|
soc_pm.data.suspend_mode == pm_mode);
|
|
}
|
|
|
|
static int __init at91_pm_backup_init(void)
|
|
{
|
|
struct gen_pool *sram_pool;
|
|
struct device_node *np;
|
|
struct platform_device *pdev = NULL;
|
|
int ret = -ENODEV;
|
|
|
|
if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
|
|
return -EPERM;
|
|
|
|
if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
|
|
return 0;
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
|
|
if (!np) {
|
|
pr_warn("%s: failed to find sfrbu!\n", __func__);
|
|
return ret;
|
|
}
|
|
|
|
soc_pm.data.sfrbu = of_iomap(np, 0);
|
|
of_node_put(np);
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
|
|
if (!np)
|
|
goto securam_fail_no_ref_dev;
|
|
|
|
pdev = of_find_device_by_node(np);
|
|
of_node_put(np);
|
|
if (!pdev) {
|
|
pr_warn("%s: failed to find securam device!\n", __func__);
|
|
goto securam_fail_no_ref_dev;
|
|
}
|
|
|
|
sram_pool = gen_pool_get(&pdev->dev, NULL);
|
|
if (!sram_pool) {
|
|
pr_warn("%s: securam pool unavailable!\n", __func__);
|
|
goto securam_fail;
|
|
}
|
|
|
|
pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
|
|
if (!pm_bu) {
|
|
pr_warn("%s: unable to alloc securam!\n", __func__);
|
|
ret = -ENOMEM;
|
|
goto securam_fail;
|
|
}
|
|
|
|
pm_bu->suspended = 0;
|
|
pm_bu->canary = __pa_symbol(&canary);
|
|
pm_bu->resume = __pa_symbol(cpu_resume);
|
|
|
|
return 0;
|
|
|
|
securam_fail:
|
|
put_device(&pdev->dev);
|
|
securam_fail_no_ref_dev:
|
|
iounmap(soc_pm.data.sfrbu);
|
|
soc_pm.data.sfrbu = NULL;
|
|
return ret;
|
|
}
|
|
|
|
static void __init at91_pm_use_default_mode(int pm_mode)
|
|
{
|
|
if (pm_mode != AT91_PM_ULP1 && pm_mode != AT91_PM_BACKUP)
|
|
return;
|
|
|
|
if (soc_pm.data.standby_mode == pm_mode)
|
|
soc_pm.data.standby_mode = AT91_PM_ULP0;
|
|
if (soc_pm.data.suspend_mode == pm_mode)
|
|
soc_pm.data.suspend_mode = AT91_PM_ULP0;
|
|
}
|
|
|
|
static void __init at91_pm_modes_init(void)
|
|
{
|
|
struct device_node *np;
|
|
int ret;
|
|
|
|
if (!at91_is_pm_mode_active(AT91_PM_BACKUP) &&
|
|
!at91_is_pm_mode_active(AT91_PM_ULP1))
|
|
return;
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-shdwc");
|
|
if (!np) {
|
|
pr_warn("%s: failed to find shdwc!\n", __func__);
|
|
goto ulp1_default;
|
|
}
|
|
|
|
soc_pm.data.shdwc = of_iomap(np, 0);
|
|
of_node_put(np);
|
|
|
|
ret = at91_pm_backup_init();
|
|
if (ret) {
|
|
if (!at91_is_pm_mode_active(AT91_PM_ULP1))
|
|
goto unmap;
|
|
else
|
|
goto backup_default;
|
|
}
|
|
|
|
return;
|
|
|
|
unmap:
|
|
iounmap(soc_pm.data.shdwc);
|
|
soc_pm.data.shdwc = NULL;
|
|
ulp1_default:
|
|
at91_pm_use_default_mode(AT91_PM_ULP1);
|
|
backup_default:
|
|
at91_pm_use_default_mode(AT91_PM_BACKUP);
|
|
}
|
|
|
|
struct pmc_info {
|
|
unsigned long uhp_udp_mask;
|
|
};
|
|
|
|
static const struct pmc_info pmc_infos[] __initconst = {
|
|
{ .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP },
|
|
{ .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP },
|
|
{ .uhp_udp_mask = AT91SAM926x_PMC_UHP },
|
|
{ .uhp_udp_mask = 0 },
|
|
};
|
|
|
|
static const struct of_device_id atmel_pmc_ids[] __initconst = {
|
|
{ .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
|
|
{ .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
|
|
{ .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] },
|
|
{ .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] },
|
|
{ .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
|
|
{ .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
|
|
{ .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] },
|
|
{ .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
|
|
{ .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
|
|
{ .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
|
|
{ .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
|
|
{ /* sentinel */ },
|
|
};
|
|
|
|
static void __init at91_pm_init(void (*pm_idle)(void))
|
|
{
|
|
struct device_node *pmc_np;
|
|
const struct of_device_id *of_id;
|
|
const struct pmc_info *pmc;
|
|
|
|
if (at91_cpuidle_device.dev.platform_data)
|
|
platform_device_register(&at91_cpuidle_device);
|
|
|
|
pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
|
|
soc_pm.data.pmc = of_iomap(pmc_np, 0);
|
|
if (!soc_pm.data.pmc) {
|
|
pr_err("AT91: PM not supported, PMC not found\n");
|
|
return;
|
|
}
|
|
|
|
pmc = of_id->data;
|
|
soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
|
|
|
|
if (pm_idle)
|
|
arm_pm_idle = pm_idle;
|
|
|
|
at91_pm_sram_init();
|
|
|
|
if (at91_suspend_sram_fn) {
|
|
suspend_set_ops(&at91_pm_ops);
|
|
pr_info("AT91: PM: standby: %s, suspend: %s\n",
|
|
pm_modes[soc_pm.data.standby_mode].pattern,
|
|
pm_modes[soc_pm.data.suspend_mode].pattern);
|
|
} else {
|
|
pr_info("AT91: PM not supported, due to no SRAM allocated\n");
|
|
}
|
|
}
|
|
|
|
void __init at91rm9200_pm_init(void)
|
|
{
|
|
if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
|
|
return;
|
|
|
|
at91_dt_ramc();
|
|
|
|
/*
|
|
* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
|
|
*/
|
|
at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
|
|
|
|
at91_pm_init(at91rm9200_idle);
|
|
}
|
|
|
|
void __init sam9x60_pm_init(void)
|
|
{
|
|
if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
|
|
return;
|
|
|
|
at91_pm_modes_init();
|
|
at91_dt_ramc();
|
|
at91_pm_init(at91sam9x60_idle);
|
|
|
|
soc_pm.ws_ids = sam9x60_ws_ids;
|
|
soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
|
|
}
|
|
|
|
void __init at91sam9_pm_init(void)
|
|
{
|
|
if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
|
|
return;
|
|
|
|
at91_dt_ramc();
|
|
at91_pm_init(at91sam9_idle);
|
|
}
|
|
|
|
void __init sama5_pm_init(void)
|
|
{
|
|
if (!IS_ENABLED(CONFIG_SOC_SAMA5))
|
|
return;
|
|
|
|
at91_dt_ramc();
|
|
at91_pm_init(NULL);
|
|
}
|
|
|
|
void __init sama5d2_pm_init(void)
|
|
{
|
|
if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
|
|
return;
|
|
|
|
at91_pm_modes_init();
|
|
sama5_pm_init();
|
|
|
|
soc_pm.ws_ids = sama5d2_ws_ids;
|
|
soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
|
|
soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
|
|
}
|
|
|
|
static int __init at91_pm_modes_select(char *str)
|
|
{
|
|
char *s;
|
|
substring_t args[MAX_OPT_ARGS];
|
|
int standby, suspend;
|
|
|
|
if (!str)
|
|
return 0;
|
|
|
|
s = strsep(&str, ",");
|
|
standby = match_token(s, pm_modes, args);
|
|
if (standby < 0)
|
|
return 0;
|
|
|
|
suspend = match_token(str, pm_modes, args);
|
|
if (suspend < 0)
|
|
return 0;
|
|
|
|
soc_pm.data.standby_mode = standby;
|
|
soc_pm.data.suspend_mode = suspend;
|
|
|
|
return 0;
|
|
}
|
|
early_param("atmel.pm_modes", at91_pm_modes_select);
|