525 строки
13 KiB
C
525 строки
13 KiB
C
/*
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* OMAP3xxx clockdomains
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*
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* Copyright (C) 2008-2011 Texas Instruments, Inc.
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* Copyright (C) 2008-2010 Nokia Corporation
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*
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* Paul Walmsley, Jouni Högander
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*
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* This file contains clockdomains and clockdomain wakeup/sleep
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* dependencies for the OMAP3xxx chips. Some notes:
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*
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* A useful validation rule for struct clockdomain: Any clockdomain
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* referenced by a wkdep_srcs or sleepdep_srcs array must have a
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* dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really just
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* software-controllable dependencies. Non-software-controllable
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* dependencies do exist, but they are not encoded below (yet).
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*
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* The overly-specific dep_bit names are due to a bit name collision
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* with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
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* value are the same for all powerdomains: 2
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*
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* XXX should dep_bit be a mask, so we can test to see if it is 0 as a
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* sanity check?
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* XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
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*/
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/*
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* To-Do List
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* -> Port the Sleep/Wakeup dependencies for the domains
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* from the Power domain framework
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include "clockdomain.h"
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#include "prm2xxx_3xxx.h"
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#include "cm2xxx_3xxx.h"
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#include "cm-regbits-34xx.h"
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#include "prm-regbits-34xx.h"
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/*
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* Clockdomain dependencies for wkdeps/sleepdeps
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*
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* XXX Hardware dependencies (e.g., dependencies that cannot be
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* changed in software) are not included here yet, but should be.
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*/
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/* OMAP3-specific possible dependencies */
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/*
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* 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
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* 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
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*/
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static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = {
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{ .clkdm_name = "iva2_clkdm" },
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{ .clkdm_name = "mpu_clkdm" },
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{ .clkdm_name = "wkup_clkdm" },
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{ NULL },
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};
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static struct clkdm_dep gfx_sgx_am35x_wkdeps[] = {
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{ .clkdm_name = "mpu_clkdm" },
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{ .clkdm_name = "wkup_clkdm" },
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{ NULL },
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};
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/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
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static struct clkdm_dep per_wkdeps[] = {
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{ .clkdm_name = "core_l3_clkdm" },
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{ .clkdm_name = "core_l4_clkdm" },
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{ .clkdm_name = "iva2_clkdm" },
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{ .clkdm_name = "mpu_clkdm" },
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{ .clkdm_name = "wkup_clkdm" },
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{ NULL },
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};
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static struct clkdm_dep per_am35x_wkdeps[] = {
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{ .clkdm_name = "core_l3_clkdm" },
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{ .clkdm_name = "core_l4_clkdm" },
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{ .clkdm_name = "mpu_clkdm" },
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{ .clkdm_name = "wkup_clkdm" },
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{ NULL },
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};
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/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
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static struct clkdm_dep usbhost_wkdeps[] = {
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{ .clkdm_name = "core_l3_clkdm" },
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{ .clkdm_name = "core_l4_clkdm" },
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{ .clkdm_name = "iva2_clkdm" },
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{ .clkdm_name = "mpu_clkdm" },
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{ .clkdm_name = "wkup_clkdm" },
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{ NULL },
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};
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static struct clkdm_dep usbhost_am35x_wkdeps[] = {
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{ .clkdm_name = "core_l3_clkdm" },
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{ .clkdm_name = "core_l4_clkdm" },
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{ .clkdm_name = "mpu_clkdm" },
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{ .clkdm_name = "wkup_clkdm" },
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{ NULL },
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};
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/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
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static struct clkdm_dep mpu_3xxx_wkdeps[] = {
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{ .clkdm_name = "core_l3_clkdm" },
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{ .clkdm_name = "core_l4_clkdm" },
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{ .clkdm_name = "iva2_clkdm" },
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{ .clkdm_name = "dss_clkdm" },
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{ .clkdm_name = "per_clkdm" },
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{ NULL },
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};
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static struct clkdm_dep mpu_am35x_wkdeps[] = {
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{ .clkdm_name = "core_l3_clkdm" },
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{ .clkdm_name = "core_l4_clkdm" },
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{ .clkdm_name = "dss_clkdm" },
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{ .clkdm_name = "per_clkdm" },
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{ NULL },
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};
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/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
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static struct clkdm_dep iva2_wkdeps[] = {
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{ .clkdm_name = "core_l3_clkdm" },
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{ .clkdm_name = "core_l4_clkdm" },
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{ .clkdm_name = "mpu_clkdm" },
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{ .clkdm_name = "wkup_clkdm" },
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{ .clkdm_name = "dss_clkdm" },
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{ .clkdm_name = "per_clkdm" },
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{ NULL },
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};
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/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
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static struct clkdm_dep cam_wkdeps[] = {
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{ .clkdm_name = "iva2_clkdm" },
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{ .clkdm_name = "mpu_clkdm" },
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{ .clkdm_name = "wkup_clkdm" },
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{ NULL },
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};
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/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
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static struct clkdm_dep dss_wkdeps[] = {
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{ .clkdm_name = "iva2_clkdm" },
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{ .clkdm_name = "mpu_clkdm" },
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{ .clkdm_name = "wkup_clkdm" },
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{ NULL },
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};
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static struct clkdm_dep dss_am35x_wkdeps[] = {
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{ .clkdm_name = "mpu_clkdm" },
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{ .clkdm_name = "wkup_clkdm" },
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{ NULL },
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};
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/* 3430: PM_WKDEP_NEON: MPU */
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static struct clkdm_dep neon_wkdeps[] = {
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{ .clkdm_name = "mpu_clkdm" },
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{ NULL },
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};
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/* Sleep dependency source arrays for OMAP3-specific clkdms */
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/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
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static struct clkdm_dep dss_sleepdeps[] = {
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{ .clkdm_name = "mpu_clkdm" },
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{ .clkdm_name = "iva2_clkdm" },
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{ NULL },
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};
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static struct clkdm_dep dss_am35x_sleepdeps[] = {
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{ .clkdm_name = "mpu_clkdm" },
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{ NULL },
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};
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/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
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static struct clkdm_dep per_sleepdeps[] = {
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{ .clkdm_name = "mpu_clkdm" },
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{ .clkdm_name = "iva2_clkdm" },
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{ NULL },
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};
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static struct clkdm_dep per_am35x_sleepdeps[] = {
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{ .clkdm_name = "mpu_clkdm" },
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{ NULL },
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};
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/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
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static struct clkdm_dep usbhost_sleepdeps[] = {
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{ .clkdm_name = "mpu_clkdm" },
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{ .clkdm_name = "iva2_clkdm" },
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{ NULL },
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};
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static struct clkdm_dep usbhost_am35x_sleepdeps[] = {
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{ .clkdm_name = "mpu_clkdm" },
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{ NULL },
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};
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/* 3430: CM_SLEEPDEP_CAM: MPU */
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static struct clkdm_dep cam_sleepdeps[] = {
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{ .clkdm_name = "mpu_clkdm" },
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{ NULL },
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};
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/*
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* 3430ES1: CM_SLEEPDEP_GFX: MPU
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* 3430ES2: CM_SLEEPDEP_SGX: MPU
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* These can share data since they will never be present simultaneously
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* on the same device.
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*/
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static struct clkdm_dep gfx_sgx_sleepdeps[] = {
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{ .clkdm_name = "mpu_clkdm" },
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{ NULL },
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};
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/*
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* OMAP3 clockdomains
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*/
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static struct clockdomain mpu_3xxx_clkdm = {
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.name = "mpu_clkdm",
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.pwrdm = { .name = "mpu_pwrdm" },
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.flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
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.dep_bit = OMAP3430_EN_MPU_SHIFT,
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.wkdep_srcs = mpu_3xxx_wkdeps,
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
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};
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static struct clockdomain mpu_am35x_clkdm = {
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.name = "mpu_clkdm",
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.pwrdm = { .name = "mpu_pwrdm" },
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.flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
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.dep_bit = OMAP3430_EN_MPU_SHIFT,
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.wkdep_srcs = mpu_am35x_wkdeps,
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
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};
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static struct clockdomain neon_clkdm = {
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.name = "neon_clkdm",
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.pwrdm = { .name = "neon_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.wkdep_srcs = neon_wkdeps,
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
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};
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static struct clockdomain iva2_clkdm = {
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.name = "iva2_clkdm",
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.pwrdm = { .name = "iva2_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
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.wkdep_srcs = iva2_wkdeps,
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
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};
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static struct clockdomain gfx_3430es1_clkdm = {
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.name = "gfx_clkdm",
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.pwrdm = { .name = "gfx_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.wkdep_srcs = gfx_sgx_3xxx_wkdeps,
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.sleepdep_srcs = gfx_sgx_sleepdeps,
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.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
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};
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static struct clockdomain sgx_clkdm = {
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.name = "sgx_clkdm",
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.pwrdm = { .name = "sgx_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.wkdep_srcs = gfx_sgx_3xxx_wkdeps,
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.sleepdep_srcs = gfx_sgx_sleepdeps,
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.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
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};
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static struct clockdomain sgx_am35x_clkdm = {
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.name = "sgx_clkdm",
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.pwrdm = { .name = "sgx_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.wkdep_srcs = gfx_sgx_am35x_wkdeps,
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.sleepdep_srcs = gfx_sgx_sleepdeps,
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.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
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};
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/*
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* The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
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* then that information was removed from the 34xx ES2+ TRM. It is
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* unclear whether the core is still there, but the clockdomain logic
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* is there, and must be programmed to an appropriate state if the
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* CORE clockdomain is to become inactive.
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*/
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static struct clockdomain d2d_clkdm = {
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.name = "d2d_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
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};
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/*
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* XXX add usecounting for clkdm dependencies, otherwise the presence
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* of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
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* could cause trouble
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*/
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static struct clockdomain core_l3_3xxx_clkdm = {
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.name = "core_l3_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.flags = CLKDM_CAN_HWSUP,
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.dep_bit = OMAP3430_EN_CORE_SHIFT,
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
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};
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/*
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* XXX add usecounting for clkdm dependencies, otherwise the presence
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* of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
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* could cause trouble
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*/
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static struct clockdomain core_l4_3xxx_clkdm = {
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.name = "core_l4_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.flags = CLKDM_CAN_HWSUP,
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.dep_bit = OMAP3430_EN_CORE_SHIFT,
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
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};
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/* Another case of bit name collisions between several registers: EN_DSS */
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static struct clockdomain dss_3xxx_clkdm = {
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.name = "dss_clkdm",
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.pwrdm = { .name = "dss_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
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.wkdep_srcs = dss_wkdeps,
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.sleepdep_srcs = dss_sleepdeps,
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
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};
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static struct clockdomain dss_am35x_clkdm = {
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.name = "dss_clkdm",
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.pwrdm = { .name = "dss_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
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.wkdep_srcs = dss_am35x_wkdeps,
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.sleepdep_srcs = dss_am35x_sleepdeps,
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
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};
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static struct clockdomain cam_clkdm = {
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.name = "cam_clkdm",
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.pwrdm = { .name = "cam_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.wkdep_srcs = cam_wkdeps,
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.sleepdep_srcs = cam_sleepdeps,
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
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};
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static struct clockdomain usbhost_clkdm = {
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.name = "usbhost_clkdm",
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.pwrdm = { .name = "usbhost_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.wkdep_srcs = usbhost_wkdeps,
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.sleepdep_srcs = usbhost_sleepdeps,
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.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
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};
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static struct clockdomain usbhost_am35x_clkdm = {
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.name = "usbhost_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.wkdep_srcs = usbhost_am35x_wkdeps,
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.sleepdep_srcs = usbhost_am35x_sleepdeps,
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.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
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};
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static struct clockdomain per_clkdm = {
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.name = "per_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.dep_bit = OMAP3430_EN_PER_SHIFT,
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.wkdep_srcs = per_wkdeps,
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.sleepdep_srcs = per_sleepdeps,
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
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};
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static struct clockdomain per_am35x_clkdm = {
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.name = "per_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.dep_bit = OMAP3430_EN_PER_SHIFT,
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.wkdep_srcs = per_am35x_wkdeps,
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.sleepdep_srcs = per_am35x_sleepdeps,
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
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};
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static struct clockdomain emu_clkdm = {
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.name = "emu_clkdm",
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.pwrdm = { .name = "emu_pwrdm" },
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.flags = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP |
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CLKDM_MISSING_IDLE_REPORTING),
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
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};
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static struct clockdomain dpll1_clkdm = {
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.name = "dpll1_clkdm",
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.pwrdm = { .name = "dpll1_pwrdm" },
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};
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static struct clockdomain dpll2_clkdm = {
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.name = "dpll2_clkdm",
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.pwrdm = { .name = "dpll2_pwrdm" },
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};
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static struct clockdomain dpll3_clkdm = {
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.name = "dpll3_clkdm",
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.pwrdm = { .name = "dpll3_pwrdm" },
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};
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static struct clockdomain dpll4_clkdm = {
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.name = "dpll4_clkdm",
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.pwrdm = { .name = "dpll4_pwrdm" },
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};
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static struct clockdomain dpll5_clkdm = {
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.name = "dpll5_clkdm",
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.pwrdm = { .name = "dpll5_pwrdm" },
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};
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/*
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* Clockdomain hwsup dependencies
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*/
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static struct clkdm_autodep clkdm_autodeps[] = {
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{
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.clkdm = { .name = "mpu_clkdm" },
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},
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{
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.clkdm = { .name = "iva2_clkdm" },
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},
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{
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.clkdm = { .name = NULL },
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}
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};
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static struct clkdm_autodep clkdm_am35x_autodeps[] = {
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{
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.clkdm = { .name = "mpu_clkdm" },
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},
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{
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.clkdm = { .name = NULL },
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}
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};
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/*
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*
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*/
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|
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static struct clockdomain *clockdomains_common[] __initdata = {
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&wkup_common_clkdm,
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&neon_clkdm,
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&core_l3_3xxx_clkdm,
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&core_l4_3xxx_clkdm,
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&emu_clkdm,
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&dpll1_clkdm,
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&dpll3_clkdm,
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|
&dpll4_clkdm,
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|
NULL
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|
};
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|
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static struct clockdomain *clockdomains_omap3430[] __initdata = {
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&mpu_3xxx_clkdm,
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&iva2_clkdm,
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&d2d_clkdm,
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&dss_3xxx_clkdm,
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&cam_clkdm,
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|
&per_clkdm,
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|
&dpll2_clkdm,
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|
NULL
|
|
};
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|
|
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static struct clockdomain *clockdomains_omap3430es1[] __initdata = {
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|
&gfx_3430es1_clkdm,
|
|
NULL,
|
|
};
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|
|
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static struct clockdomain *clockdomains_omap3430es2plus[] __initdata = {
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|
&sgx_clkdm,
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|
&dpll5_clkdm,
|
|
&usbhost_clkdm,
|
|
NULL,
|
|
};
|
|
|
|
static struct clockdomain *clockdomains_am35x[] __initdata = {
|
|
&mpu_am35x_clkdm,
|
|
&sgx_am35x_clkdm,
|
|
&dss_am35x_clkdm,
|
|
&per_am35x_clkdm,
|
|
&usbhost_am35x_clkdm,
|
|
&dpll5_clkdm,
|
|
NULL
|
|
};
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|
|
|
void __init omap3xxx_clockdomains_init(void)
|
|
{
|
|
struct clockdomain **sc;
|
|
unsigned int rev;
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|
|
|
if (!cpu_is_omap34xx())
|
|
return;
|
|
|
|
clkdm_register_platform_funcs(&omap3_clkdm_operations);
|
|
clkdm_register_clkdms(clockdomains_common);
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|
|
|
rev = omap_rev();
|
|
|
|
if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
|
|
clkdm_register_clkdms(clockdomains_am35x);
|
|
clkdm_register_autodeps(clkdm_am35x_autodeps);
|
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} else {
|
|
clkdm_register_clkdms(clockdomains_omap3430);
|
|
|
|
sc = (rev == OMAP3430_REV_ES1_0) ?
|
|
clockdomains_omap3430es1 : clockdomains_omap3430es2plus;
|
|
|
|
clkdm_register_clkdms(sc);
|
|
clkdm_register_autodeps(clkdm_autodeps);
|
|
}
|
|
|
|
clkdm_complete_init();
|
|
}
|