464 строки
15 KiB
C
464 строки
15 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Christian König.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Christian König
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* Rafał Miłecki
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*/
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#include <linux/hdmi.h>
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "radeon_audio.h"
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#include "evergreend.h"
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#include "atom.h"
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/* enable the audio stream */
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void dce4_audio_enable(struct radeon_device *rdev,
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struct r600_audio_pin *pin,
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u8 enable_mask)
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{
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u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
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if (!pin)
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return;
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if (enable_mask) {
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tmp |= AUDIO_ENABLED;
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if (enable_mask & 1)
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tmp |= PIN0_AUDIO_ENABLED;
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if (enable_mask & 2)
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tmp |= PIN1_AUDIO_ENABLED;
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if (enable_mask & 4)
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tmp |= PIN2_AUDIO_ENABLED;
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if (enable_mask & 8)
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tmp |= PIN3_AUDIO_ENABLED;
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} else {
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tmp &= ~(AUDIO_ENABLED |
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PIN0_AUDIO_ENABLED |
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PIN1_AUDIO_ENABLED |
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PIN2_AUDIO_ENABLED |
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PIN3_AUDIO_ENABLED);
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}
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WREG32(AZ_HOT_PLUG_CONTROL, tmp);
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}
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void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset,
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const struct radeon_hdmi_acr *acr)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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int bpc = 8;
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if (encoder->crtc) {
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
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bpc = radeon_crtc->bpc;
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}
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if (bpc > 8)
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WREG32(HDMI_ACR_PACKET_CONTROL + offset,
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HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
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else
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WREG32(HDMI_ACR_PACKET_CONTROL + offset,
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HDMI_ACR_SOURCE | /* select SW CTS value */
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HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
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WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz));
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WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz);
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WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz));
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WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz);
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WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz));
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WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz);
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}
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void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
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struct drm_connector *connector, struct drm_display_mode *mode)
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{
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struct radeon_device *rdev = encoder->dev->dev_private;
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u32 tmp = 0;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
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if (connector->latency_present[1])
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tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
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AUDIO_LIPSYNC(connector->audio_latency[1]);
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else
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tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
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} else {
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if (connector->latency_present[0])
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tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
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AUDIO_LIPSYNC(connector->audio_latency[0]);
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else
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tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
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}
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WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
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}
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void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
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u8 *sadb, int sad_count)
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{
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struct radeon_device *rdev = encoder->dev->dev_private;
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u32 tmp;
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/* program the speaker allocation */
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tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
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tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
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/* set HDMI mode */
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tmp |= HDMI_CONNECTION;
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if (sad_count)
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tmp |= SPEAKER_ALLOCATION(sadb[0]);
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else
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tmp |= SPEAKER_ALLOCATION(5); /* stereo */
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WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
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}
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void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
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u8 *sadb, int sad_count)
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{
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struct radeon_device *rdev = encoder->dev->dev_private;
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u32 tmp;
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/* program the speaker allocation */
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tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
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tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
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/* set DP mode */
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tmp |= DP_CONNECTION;
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if (sad_count)
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tmp |= SPEAKER_ALLOCATION(sadb[0]);
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else
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tmp |= SPEAKER_ALLOCATION(5); /* stereo */
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WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
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}
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void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder,
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struct cea_sad *sads, int sad_count)
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{
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int i;
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struct radeon_device *rdev = encoder->dev->dev_private;
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static const u16 eld_reg_to_type[][2] = {
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
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{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
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};
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for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
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u32 value = 0;
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u8 stereo_freqs = 0;
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int max_channels = -1;
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int j;
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for (j = 0; j < sad_count; j++) {
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struct cea_sad *sad = &sads[j];
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if (sad->format == eld_reg_to_type[i][1]) {
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if (sad->channels > max_channels) {
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value = MAX_CHANNELS(sad->channels) |
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DESCRIPTOR_BYTE_2(sad->byte2) |
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SUPPORTED_FREQUENCIES(sad->freq);
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max_channels = sad->channels;
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}
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if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
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stereo_freqs |= sad->freq;
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else
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break;
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}
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}
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value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
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WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);
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}
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}
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/*
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* build a AVI Info Frame
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*/
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void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset,
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unsigned char *buffer, size_t size)
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{
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uint8_t *frame = buffer + 3;
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WREG32(AFMT_AVI_INFO0 + offset,
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frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
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WREG32(AFMT_AVI_INFO1 + offset,
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frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
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WREG32(AFMT_AVI_INFO2 + offset,
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frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
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WREG32(AFMT_AVI_INFO3 + offset,
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frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24));
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WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
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HDMI_AVI_INFO_SEND | /* enable AVI info frames */
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HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
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WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
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HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
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~HDMI_AVI_INFO_LINE_MASK);
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}
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void dce4_hdmi_audio_set_dto(struct radeon_device *rdev,
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struct radeon_crtc *crtc, unsigned int clock)
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{
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unsigned int max_ratio = clock / 24000;
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u32 dto_phase;
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u32 wallclock_ratio;
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u32 value;
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if (max_ratio >= 8) {
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dto_phase = 192 * 1000;
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wallclock_ratio = 3;
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} else if (max_ratio >= 4) {
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dto_phase = 96 * 1000;
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wallclock_ratio = 2;
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} else if (max_ratio >= 2) {
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dto_phase = 48 * 1000;
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wallclock_ratio = 1;
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} else {
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dto_phase = 24 * 1000;
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wallclock_ratio = 0;
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}
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value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
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value |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
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value &= ~DCCG_AUDIO_DTO1_USE_512FBR_DTO;
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WREG32(DCCG_AUDIO_DTO0_CNTL, value);
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/* Two dtos; generally use dto0 for HDMI */
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value = 0;
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if (crtc)
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value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
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WREG32(DCCG_AUDIO_DTO_SOURCE, value);
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/* Express [24MHz / target pixel clock] as an exact rational
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* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
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* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
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*/
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WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
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WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
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}
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void dce4_dp_audio_set_dto(struct radeon_device *rdev,
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struct radeon_crtc *crtc, unsigned int clock)
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{
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u32 value;
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value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
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value |= DCCG_AUDIO_DTO1_USE_512FBR_DTO;
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WREG32(DCCG_AUDIO_DTO1_CNTL, value);
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/* Two dtos; generally use dto1 for DP */
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value = 0;
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value |= DCCG_AUDIO_DTO_SEL;
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if (crtc)
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value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
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WREG32(DCCG_AUDIO_DTO_SOURCE, value);
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/* Express [24MHz / target pixel clock] as an exact rational
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* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
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* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
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*/
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WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
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WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
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}
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void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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WREG32(HDMI_VBI_PACKET_CONTROL + offset,
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HDMI_NULL_SEND | /* send null packets when required */
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HDMI_GC_SEND | /* send general control packets */
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HDMI_GC_CONT); /* send general control packets every frame */
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}
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void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
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uint32_t val;
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val = RREG32(HDMI_CONTROL + offset);
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val &= ~HDMI_DEEP_COLOR_ENABLE;
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val &= ~HDMI_DEEP_COLOR_DEPTH_MASK;
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switch (bpc) {
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case 0:
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case 6:
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case 8:
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case 16:
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default:
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DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
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connector->name, bpc);
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break;
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case 10:
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val |= HDMI_DEEP_COLOR_ENABLE;
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val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR);
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DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
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connector->name);
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break;
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case 12:
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val |= HDMI_DEEP_COLOR_ENABLE;
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val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR);
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DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
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connector->name);
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break;
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}
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WREG32(HDMI_CONTROL + offset, val);
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}
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void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
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AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
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WREG32(AFMT_60958_0 + offset,
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AFMT_60958_CS_CHANNEL_NUMBER_L(1));
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WREG32(AFMT_60958_1 + offset,
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AFMT_60958_CS_CHANNEL_NUMBER_R(2));
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WREG32(AFMT_60958_2 + offset,
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AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
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AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
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AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
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AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
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AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
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AFMT_60958_CS_CHANNEL_NUMBER_7(8));
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WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
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AFMT_AUDIO_CHANNEL_ENABLE(0xff));
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/* allow 60958 channel status and send audio packets fields to be updated */
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WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
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AFMT_AUDIO_SAMPLE_SEND | AFMT_RESET_FIFO_WHEN_AUDIO_DIS | AFMT_60958_CS_UPDATE);
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}
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void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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if (mute)
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WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE);
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else
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WREG32_AND(HDMI_GC + offset, ~HDMI_GC_AVMUTE);
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}
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void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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if (!dig || !dig->afmt)
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return;
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if (enable) {
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WREG32(HDMI_INFOFRAME_CONTROL1 + dig->afmt->offset,
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HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
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WREG32(HDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset,
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HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
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HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
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WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,
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HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
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HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
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} else {
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WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0);
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}
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dig->afmt->enabled = enable;
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DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
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enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
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}
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void evergreen_dp_enable(struct drm_encoder *encoder, bool enable)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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if (!dig || !dig->afmt)
|
|
return;
|
|
|
|
if (enable) {
|
|
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
|
|
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
|
|
struct radeon_connector_atom_dig *dig_connector;
|
|
uint32_t val;
|
|
|
|
WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset,
|
|
EVERGREEN_DP_SEC_TIMESTAMP_MODE(1));
|
|
|
|
if (radeon_connector->con_priv) {
|
|
dig_connector = radeon_connector->con_priv;
|
|
val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset);
|
|
val &= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf);
|
|
|
|
if (dig_connector->dp_clock == 162000)
|
|
val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(3);
|
|
else
|
|
val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5);
|
|
|
|
WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val);
|
|
}
|
|
|
|
WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset,
|
|
EVERGREEN_DP_SEC_ASP_ENABLE | /* Audio packet transmission */
|
|
EVERGREEN_DP_SEC_ATP_ENABLE | /* Audio timestamp packet transmission */
|
|
EVERGREEN_DP_SEC_AIP_ENABLE | /* Audio infoframe packet transmission */
|
|
EVERGREEN_DP_SEC_STREAM_ENABLE); /* Master enable for secondary stream engine */
|
|
} else {
|
|
WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0);
|
|
}
|
|
|
|
dig->afmt->enabled = enable;
|
|
}
|