7d4b5ca2e2
In preparation for infrastructure that enumerates and configures the CXL decode mechanism of an upstream port to its downstream ports, add a representation of a CXL downstream port. On ACPI systems the top-most logical downstream ports in the hierarchy are the host bridges (ACPI0016 devices) that decode the memory windows described by the CXL Early Discovery Table Fixed Memory Window Structures (CEDT.CFMWS). Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://lore.kernel.org/r/162325450624.2293126.3533006409920271718.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com> |
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| ABI | ||
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| arch.rst | ||
| asm-annotations.rst | ||
| atomic_bitops.txt | ||
| atomic_t.txt | ||
| conf.py | ||
| docutils.conf | ||
| dontdiff | ||
| index.rst | ||
| logo.gif | ||
| memory-barriers.txt | ||
| watch_queue.rst | ||
