717 строки
18 KiB
C
717 строки
18 KiB
C
/*
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* intel_idle.c - native hardware idle loop for modern Intel processors
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*
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* Copyright (c) 2013, Intel Corporation.
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* Len Brown <len.brown@intel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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/*
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* intel_idle is a cpuidle driver that loads on specific Intel processors
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* in lieu of the legacy ACPI processor_idle driver. The intent is to
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* make Linux more efficient on these processors, as intel_idle knows
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* more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
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*/
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/*
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* Design Assumptions
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*
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* All CPUs have same idle states as boot CPU
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*
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* Chipset BM_STS (bus master status) bit is a NOP
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* for preventing entry into deep C-stats
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*/
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/*
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* Known limitations
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*
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* The driver currently initializes for_each_online_cpu() upon modprobe.
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* It it unaware of subsequent processors hot-added to the system.
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* This means that if you boot with maxcpus=n and later online
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* processors above n, those processors will use C1 only.
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*
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* ACPI has a .suspend hack to turn off deep c-statees during suspend
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* to avoid complications with the lapic timer workaround.
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* Have not seen issues with suspend, but may need same workaround here.
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*
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* There is currently no kernel-based automatic probing/loading mechanism
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* if the driver is built as a module.
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*/
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/* un-comment DEBUG to enable pr_debug() statements */
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#define DEBUG
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#include <linux/kernel.h>
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#include <linux/cpuidle.h>
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#include <linux/clockchips.h>
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#include <trace/events/power.h>
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#include <linux/sched.h>
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#include <linux/notifier.h>
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#include <linux/cpu.h>
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#include <linux/module.h>
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#include <asm/cpu_device_id.h>
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#include <asm/mwait.h>
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#include <asm/msr.h>
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#define INTEL_IDLE_VERSION "0.4"
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#define PREFIX "intel_idle: "
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static struct cpuidle_driver intel_idle_driver = {
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.name = "intel_idle",
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.owner = THIS_MODULE,
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};
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/* intel_idle.max_cstate=0 disables driver */
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static int max_cstate = CPUIDLE_STATE_MAX - 1;
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static unsigned int mwait_substates;
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#define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
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/* Reliable LAPIC Timer States, bit 1 for C1 etc. */
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static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */
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struct idle_cpu {
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struct cpuidle_state *state_table;
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/*
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* Hardware C-state auto-demotion may not always be optimal.
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* Indicate which enable bits to clear here.
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*/
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unsigned long auto_demotion_disable_flags;
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bool disable_promotion_to_c1e;
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};
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static const struct idle_cpu *icpu;
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static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
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static int intel_idle(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index);
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static int intel_idle_cpu_init(int cpu);
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static struct cpuidle_state *cpuidle_state_table;
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/*
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* Set this flag for states where the HW flushes the TLB for us
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* and so we don't need cross-calls to keep it consistent.
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* If this flag is set, SW flushes the TLB, so even if the
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* HW doesn't do the flushing, this flag is safe to use.
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*/
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#define CPUIDLE_FLAG_TLB_FLUSHED 0x10000
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/*
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* MWAIT takes an 8-bit "hint" in EAX "suggesting"
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* the C-state (top nibble) and sub-state (bottom nibble)
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* 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
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*
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* We store the hint at the top of our "flags" for each state.
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*/
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#define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
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#define MWAIT2flg(eax) ((eax & 0xFF) << 24)
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/*
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* States are indexed by the cstate number,
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* which is also the index into the MWAIT hint array.
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* Thus C0 is a dummy.
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*/
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static struct cpuidle_state nehalem_cstates[] = {
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{
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.name = "C1-NHM",
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.desc = "MWAIT 0x00",
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.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 3,
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.target_residency = 6,
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.enter = &intel_idle },
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{
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.name = "C1E-NHM",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 10,
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.target_residency = 20,
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.enter = &intel_idle },
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{
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.name = "C3-NHM",
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.desc = "MWAIT 0x10",
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.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 20,
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.target_residency = 80,
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.enter = &intel_idle },
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{
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.name = "C6-NHM",
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.desc = "MWAIT 0x20",
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.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 200,
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.target_residency = 800,
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.enter = &intel_idle },
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{
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.enter = NULL }
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};
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static struct cpuidle_state snb_cstates[] = {
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{
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.name = "C1-SNB",
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.desc = "MWAIT 0x00",
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.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 2,
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.target_residency = 2,
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.enter = &intel_idle },
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{
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.name = "C1E-SNB",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 10,
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.target_residency = 20,
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.enter = &intel_idle },
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{
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.name = "C3-SNB",
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.desc = "MWAIT 0x10",
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.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 80,
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.target_residency = 211,
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.enter = &intel_idle },
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{
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.name = "C6-SNB",
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.desc = "MWAIT 0x20",
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.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 104,
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.target_residency = 345,
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.enter = &intel_idle },
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{
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.name = "C7-SNB",
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.desc = "MWAIT 0x30",
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.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 109,
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.target_residency = 345,
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.enter = &intel_idle },
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{
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.enter = NULL }
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};
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static struct cpuidle_state ivb_cstates[] = {
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{
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.name = "C1-IVB",
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.desc = "MWAIT 0x00",
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.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 1,
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.target_residency = 1,
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.enter = &intel_idle },
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{
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.name = "C1E-IVB",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 10,
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.target_residency = 20,
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.enter = &intel_idle },
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{
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.name = "C3-IVB",
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.desc = "MWAIT 0x10",
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.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 59,
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.target_residency = 156,
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.enter = &intel_idle },
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{
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.name = "C6-IVB",
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.desc = "MWAIT 0x20",
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.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 80,
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.target_residency = 300,
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.enter = &intel_idle },
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{
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.name = "C7-IVB",
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.desc = "MWAIT 0x30",
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.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 87,
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.target_residency = 300,
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.enter = &intel_idle },
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{
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.enter = NULL }
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};
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static struct cpuidle_state hsw_cstates[] = {
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{
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.name = "C1-HSW",
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.desc = "MWAIT 0x00",
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.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 2,
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.target_residency = 2,
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.enter = &intel_idle },
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{
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.name = "C1E-HSW",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 10,
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.target_residency = 20,
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.enter = &intel_idle },
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{
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.name = "C3-HSW",
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.desc = "MWAIT 0x10",
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.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 33,
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.target_residency = 100,
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.enter = &intel_idle },
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{
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.name = "C6-HSW",
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.desc = "MWAIT 0x20",
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.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 133,
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.target_residency = 400,
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.enter = &intel_idle },
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{
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.name = "C7s-HSW",
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.desc = "MWAIT 0x32",
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.flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 166,
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.target_residency = 500,
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.enter = &intel_idle },
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{
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.name = "C8-HSW",
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.desc = "MWAIT 0x40",
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.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 300,
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.target_residency = 900,
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.enter = &intel_idle },
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{
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.name = "C9-HSW",
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.desc = "MWAIT 0x50",
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.flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 600,
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.target_residency = 1800,
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.enter = &intel_idle },
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{
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.name = "C10-HSW",
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.desc = "MWAIT 0x60",
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.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 2600,
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.target_residency = 7700,
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.enter = &intel_idle },
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{
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.enter = NULL }
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};
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static struct cpuidle_state atom_cstates[] = {
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{
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.name = "C1E-ATM",
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.desc = "MWAIT 0x00",
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.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 10,
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.target_residency = 20,
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.enter = &intel_idle },
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{
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.name = "C2-ATM",
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.desc = "MWAIT 0x10",
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.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 20,
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.target_residency = 80,
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.enter = &intel_idle },
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{
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.name = "C4-ATM",
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.desc = "MWAIT 0x30",
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.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 100,
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.target_residency = 400,
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.enter = &intel_idle },
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{
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.name = "C6-ATM",
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.desc = "MWAIT 0x52",
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.flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 140,
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.target_residency = 560,
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.enter = &intel_idle },
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{
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.enter = NULL }
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};
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static struct cpuidle_state avn_cstates[] = {
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{
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.name = "C1-AVN",
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.desc = "MWAIT 0x00",
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.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 2,
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.target_residency = 2,
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.enter = &intel_idle },
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{
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.name = "C6-AVN",
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.desc = "MWAIT 0x51",
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.flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 15,
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.target_residency = 45,
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.enter = &intel_idle },
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{
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.enter = NULL }
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};
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/**
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* intel_idle
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* @dev: cpuidle_device
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* @drv: cpuidle driver
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* @index: index of cpuidle state
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*
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* Must be called under local_irq_disable().
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*/
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static int intel_idle(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index)
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{
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unsigned long ecx = 1; /* break on interrupt flag */
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struct cpuidle_state *state = &drv->states[index];
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unsigned long eax = flg2MWAIT(state->flags);
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unsigned int cstate;
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int cpu = smp_processor_id();
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cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
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/*
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* leave_mm() to avoid costly and often unnecessary wakeups
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* for flushing the user TLB's associated with the active mm.
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*/
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if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
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leave_mm(cpu);
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if (!(lapic_timer_reliable_states & (1 << (cstate))))
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
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mwait_idle_with_hints(eax, ecx);
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if (!(lapic_timer_reliable_states & (1 << (cstate))))
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
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return index;
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}
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static void __setup_broadcast_timer(void *arg)
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{
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unsigned long reason = (unsigned long)arg;
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int cpu = smp_processor_id();
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reason = reason ?
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CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
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clockevents_notify(reason, &cpu);
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}
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static int cpu_hotplug_notify(struct notifier_block *n,
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unsigned long action, void *hcpu)
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{
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int hotcpu = (unsigned long)hcpu;
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struct cpuidle_device *dev;
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switch (action & ~CPU_TASKS_FROZEN) {
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case CPU_ONLINE:
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if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
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smp_call_function_single(hotcpu, __setup_broadcast_timer,
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(void *)true, 1);
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/*
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* Some systems can hotplug a cpu at runtime after
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* the kernel has booted, we have to initialize the
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* driver in this case
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*/
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dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
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if (!dev->registered)
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intel_idle_cpu_init(hotcpu);
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block cpu_hotplug_notifier = {
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.notifier_call = cpu_hotplug_notify,
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};
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static void auto_demotion_disable(void *dummy)
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{
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unsigned long long msr_bits;
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rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
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msr_bits &= ~(icpu->auto_demotion_disable_flags);
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wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
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}
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static void c1e_promotion_disable(void *dummy)
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{
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unsigned long long msr_bits;
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rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
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msr_bits &= ~0x2;
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wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
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}
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static const struct idle_cpu idle_cpu_nehalem = {
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.state_table = nehalem_cstates,
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.auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
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.disable_promotion_to_c1e = true,
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};
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static const struct idle_cpu idle_cpu_atom = {
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.state_table = atom_cstates,
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};
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static const struct idle_cpu idle_cpu_lincroft = {
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.state_table = atom_cstates,
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.auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
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};
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static const struct idle_cpu idle_cpu_snb = {
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.state_table = snb_cstates,
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.disable_promotion_to_c1e = true,
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};
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static const struct idle_cpu idle_cpu_ivb = {
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.state_table = ivb_cstates,
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.disable_promotion_to_c1e = true,
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};
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static const struct idle_cpu idle_cpu_hsw = {
|
|
.state_table = hsw_cstates,
|
|
.disable_promotion_to_c1e = true,
|
|
};
|
|
|
|
static const struct idle_cpu idle_cpu_avn = {
|
|
.state_table = avn_cstates,
|
|
.disable_promotion_to_c1e = true,
|
|
};
|
|
|
|
#define ICPU(model, cpu) \
|
|
{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
|
|
|
|
static const struct x86_cpu_id intel_idle_ids[] = {
|
|
ICPU(0x1a, idle_cpu_nehalem),
|
|
ICPU(0x1e, idle_cpu_nehalem),
|
|
ICPU(0x1f, idle_cpu_nehalem),
|
|
ICPU(0x25, idle_cpu_nehalem),
|
|
ICPU(0x2c, idle_cpu_nehalem),
|
|
ICPU(0x2e, idle_cpu_nehalem),
|
|
ICPU(0x1c, idle_cpu_atom),
|
|
ICPU(0x26, idle_cpu_lincroft),
|
|
ICPU(0x2f, idle_cpu_nehalem),
|
|
ICPU(0x2a, idle_cpu_snb),
|
|
ICPU(0x2d, idle_cpu_snb),
|
|
ICPU(0x3a, idle_cpu_ivb),
|
|
ICPU(0x3e, idle_cpu_ivb),
|
|
ICPU(0x3c, idle_cpu_hsw),
|
|
ICPU(0x3f, idle_cpu_hsw),
|
|
ICPU(0x45, idle_cpu_hsw),
|
|
ICPU(0x46, idle_cpu_hsw),
|
|
ICPU(0x4D, idle_cpu_avn),
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);
|
|
|
|
/*
|
|
* intel_idle_probe()
|
|
*/
|
|
static int __init intel_idle_probe(void)
|
|
{
|
|
unsigned int eax, ebx, ecx;
|
|
const struct x86_cpu_id *id;
|
|
|
|
if (max_cstate == 0) {
|
|
pr_debug(PREFIX "disabled\n");
|
|
return -EPERM;
|
|
}
|
|
|
|
id = x86_match_cpu(intel_idle_ids);
|
|
if (!id) {
|
|
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
|
|
boot_cpu_data.x86 == 6)
|
|
pr_debug(PREFIX "does not run on family %d model %d\n",
|
|
boot_cpu_data.x86, boot_cpu_data.x86_model);
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
|
|
return -ENODEV;
|
|
|
|
cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
|
|
|
|
if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
|
|
!(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
|
|
!mwait_substates)
|
|
return -ENODEV;
|
|
|
|
pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
|
|
|
|
icpu = (const struct idle_cpu *)id->driver_data;
|
|
cpuidle_state_table = icpu->state_table;
|
|
|
|
if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
|
|
lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
|
|
else
|
|
on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
|
|
|
|
pr_debug(PREFIX "v" INTEL_IDLE_VERSION
|
|
" model 0x%X\n", boot_cpu_data.x86_model);
|
|
|
|
pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
|
|
lapic_timer_reliable_states);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* intel_idle_cpuidle_devices_uninit()
|
|
* unregister, free cpuidle_devices
|
|
*/
|
|
static void intel_idle_cpuidle_devices_uninit(void)
|
|
{
|
|
int i;
|
|
struct cpuidle_device *dev;
|
|
|
|
for_each_online_cpu(i) {
|
|
dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
|
|
cpuidle_unregister_device(dev);
|
|
}
|
|
|
|
free_percpu(intel_idle_cpuidle_devices);
|
|
return;
|
|
}
|
|
/*
|
|
* intel_idle_cpuidle_driver_init()
|
|
* allocate, initialize cpuidle_states
|
|
*/
|
|
static int __init intel_idle_cpuidle_driver_init(void)
|
|
{
|
|
int cstate;
|
|
struct cpuidle_driver *drv = &intel_idle_driver;
|
|
|
|
drv->state_count = 1;
|
|
|
|
for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
|
|
int num_substates, mwait_hint, mwait_cstate, mwait_substate;
|
|
|
|
if (cpuidle_state_table[cstate].enter == NULL)
|
|
break;
|
|
|
|
if (cstate + 1 > max_cstate) {
|
|
printk(PREFIX "max_cstate %d reached\n",
|
|
max_cstate);
|
|
break;
|
|
}
|
|
|
|
mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
|
|
mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint);
|
|
mwait_substate = MWAIT_HINT2SUBSTATE(mwait_hint);
|
|
|
|
/* does the state exist in CPUID.MWAIT? */
|
|
num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4))
|
|
& MWAIT_SUBSTATE_MASK;
|
|
|
|
/* if sub-state in table is not enumerated by CPUID */
|
|
if ((mwait_substate + 1) > num_substates)
|
|
continue;
|
|
|
|
if (((mwait_cstate + 1) > 2) &&
|
|
!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
|
|
mark_tsc_unstable("TSC halts in idle"
|
|
" states deeper than C2");
|
|
|
|
drv->states[drv->state_count] = /* structure copy */
|
|
cpuidle_state_table[cstate];
|
|
|
|
drv->state_count += 1;
|
|
}
|
|
|
|
if (icpu->auto_demotion_disable_flags)
|
|
on_each_cpu(auto_demotion_disable, NULL, 1);
|
|
|
|
if (icpu->disable_promotion_to_c1e) /* each-cpu is redundant */
|
|
on_each_cpu(c1e_promotion_disable, NULL, 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* intel_idle_cpu_init()
|
|
* allocate, initialize, register cpuidle_devices
|
|
* @cpu: cpu/core to initialize
|
|
*/
|
|
static int intel_idle_cpu_init(int cpu)
|
|
{
|
|
struct cpuidle_device *dev;
|
|
|
|
dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
|
|
|
|
dev->cpu = cpu;
|
|
|
|
if (cpuidle_register_device(dev)) {
|
|
pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu);
|
|
intel_idle_cpuidle_devices_uninit();
|
|
return -EIO;
|
|
}
|
|
|
|
if (icpu->auto_demotion_disable_flags)
|
|
smp_call_function_single(cpu, auto_demotion_disable, NULL, 1);
|
|
|
|
if (icpu->disable_promotion_to_c1e)
|
|
smp_call_function_single(cpu, c1e_promotion_disable, NULL, 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __init intel_idle_init(void)
|
|
{
|
|
int retval, i;
|
|
|
|
/* Do not load intel_idle at all for now if idle= is passed */
|
|
if (boot_option_idle_override != IDLE_NO_OVERRIDE)
|
|
return -ENODEV;
|
|
|
|
retval = intel_idle_probe();
|
|
if (retval)
|
|
return retval;
|
|
|
|
intel_idle_cpuidle_driver_init();
|
|
retval = cpuidle_register_driver(&intel_idle_driver);
|
|
if (retval) {
|
|
struct cpuidle_driver *drv = cpuidle_get_driver();
|
|
printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
|
|
drv ? drv->name : "none");
|
|
return retval;
|
|
}
|
|
|
|
intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
|
|
if (intel_idle_cpuidle_devices == NULL)
|
|
return -ENOMEM;
|
|
|
|
for_each_online_cpu(i) {
|
|
retval = intel_idle_cpu_init(i);
|
|
if (retval) {
|
|
cpuidle_unregister_driver(&intel_idle_driver);
|
|
return retval;
|
|
}
|
|
}
|
|
register_cpu_notifier(&cpu_hotplug_notifier);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __exit intel_idle_exit(void)
|
|
{
|
|
intel_idle_cpuidle_devices_uninit();
|
|
cpuidle_unregister_driver(&intel_idle_driver);
|
|
|
|
|
|
if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
|
|
on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
|
|
unregister_cpu_notifier(&cpu_hotplug_notifier);
|
|
|
|
return;
|
|
}
|
|
|
|
module_init(intel_idle_init);
|
|
module_exit(intel_idle_exit);
|
|
|
|
module_param(max_cstate, int, 0444);
|
|
|
|
MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
|
|
MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
|
|
MODULE_LICENSE("GPL");
|