444 строки
14 KiB
C
444 строки
14 KiB
C
#ifndef _ASM_POWERPC_PGTABLE_PPC64_H_
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#define _ASM_POWERPC_PGTABLE_PPC64_H_
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/*
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* This file contains the functions and defines necessary to modify and use
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* the ppc64 hashed page table.
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*/
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#ifndef __ASSEMBLY__
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#include <linux/stddef.h>
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#include <asm/tlbflush.h>
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#endif /* __ASSEMBLY__ */
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#ifdef CONFIG_PPC_64K_PAGES
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#include <asm/pgtable-64k.h>
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#else
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#include <asm/pgtable-4k.h>
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#endif
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#define FIRST_USER_ADDRESS 0
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/*
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* Size of EA range mapped by our pagetables.
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*/
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#define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
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PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
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#define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
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#if TASK_SIZE_USER64 > PGTABLE_RANGE
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#error TASK_SIZE_USER64 exceeds pagetable range
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#endif
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#if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
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#error TASK_SIZE_USER64 exceeds user VSID range
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#endif
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/*
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* Define the address range of the vmalloc VM area.
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*/
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#define VMALLOC_START ASM_CONST(0xD000000000000000)
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#define VMALLOC_SIZE (PGTABLE_RANGE >> 1)
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#define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE)
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/*
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* Define the address ranges for MMIO and IO space :
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*
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* ISA_IO_BASE = VMALLOC_END, 64K reserved area
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* PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
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* IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
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*/
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#define FULL_IO_SIZE 0x80000000ul
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#define ISA_IO_BASE (VMALLOC_END)
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#define ISA_IO_END (VMALLOC_END + 0x10000ul)
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#define PHB_IO_BASE (ISA_IO_END)
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#define PHB_IO_END (VMALLOC_END + FULL_IO_SIZE)
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#define IOREMAP_BASE (PHB_IO_END)
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#define IOREMAP_END (VMALLOC_START + PGTABLE_RANGE)
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/*
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* Region IDs
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*/
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#define REGION_SHIFT 60UL
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#define REGION_MASK (0xfUL << REGION_SHIFT)
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#define REGION_ID(ea) (((unsigned long)(ea)) >> REGION_SHIFT)
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#define VMALLOC_REGION_ID (REGION_ID(VMALLOC_START))
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#define KERNEL_REGION_ID (REGION_ID(PAGE_OFFSET))
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#define USER_REGION_ID (0UL)
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/*
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* Defines the address of the vmemap area, in the top 16th of the
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* kernel region.
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*/
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#define VMEMMAP_BASE (ASM_CONST(CONFIG_KERNEL_START) + \
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(0xfUL << (REGION_SHIFT - 4)))
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#define vmemmap ((struct page *)VMEMMAP_BASE)
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/*
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* Common bits in a linux-style PTE. These match the bits in the
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* (hardware-defined) PowerPC PTE as closely as possible. Additional
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* bits may be defined in pgtable-*.h
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*/
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#define _PAGE_PRESENT 0x0001 /* software: pte contains a translation */
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#define _PAGE_USER 0x0002 /* matches one of the PP bits */
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#define _PAGE_FILE 0x0002 /* (!present only) software: pte holds file offset */
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#define _PAGE_EXEC 0x0004 /* No execute on POWER4 and newer (we invert) */
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#define _PAGE_GUARDED 0x0008
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#define _PAGE_COHERENT 0x0010 /* M: enforce memory coherence (SMP systems) */
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#define _PAGE_NO_CACHE 0x0020 /* I: cache inhibit */
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#define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */
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#define _PAGE_DIRTY 0x0080 /* C: page changed */
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#define _PAGE_ACCESSED 0x0100 /* R: page referenced */
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#define _PAGE_RW 0x0200 /* software: user write access allowed */
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#define _PAGE_HASHPTE 0x0400 /* software: pte has an associated HPTE */
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#define _PAGE_BUSY 0x0800 /* software: PTE & hash are busy */
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#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT)
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#define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY)
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/* __pgprot defined in asm-powerpc/page.h */
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#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
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#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER)
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#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER | _PAGE_EXEC)
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#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
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#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
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#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
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#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
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#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_WRENABLE)
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#define PAGE_KERNEL_CI __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
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_PAGE_WRENABLE | _PAGE_NO_CACHE | _PAGE_GUARDED)
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#define PAGE_KERNEL_EXEC __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_EXEC)
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#define PAGE_AGP __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_NO_CACHE)
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#define HAVE_PAGE_AGP
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/* PTEIDX nibble */
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#define _PTEIDX_SECONDARY 0x8
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#define _PTEIDX_GROUP_IX 0x7
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/*
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* POWER4 and newer have per page execute protection, older chips can only
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* do this on a segment (256MB) basis.
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*
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* Also, write permissions imply read permissions.
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* This is the closest we can get..
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*
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* Note due to the way vm flags are laid out, the bits are XWR
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*/
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#define __P000 PAGE_NONE
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#define __P001 PAGE_READONLY
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#define __P010 PAGE_COPY
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#define __P011 PAGE_COPY
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#define __P100 PAGE_READONLY_X
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#define __P101 PAGE_READONLY_X
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#define __P110 PAGE_COPY_X
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#define __P111 PAGE_COPY_X
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#define __S000 PAGE_NONE
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#define __S001 PAGE_READONLY
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#define __S010 PAGE_SHARED
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#define __S011 PAGE_SHARED
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#define __S100 PAGE_READONLY_X
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#define __S101 PAGE_READONLY_X
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#define __S110 PAGE_SHARED_X
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#define __S111 PAGE_SHARED_X
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#ifdef CONFIG_HUGETLB_PAGE
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#define HAVE_ARCH_UNMAPPED_AREA
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#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
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#endif
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#ifndef __ASSEMBLY__
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/*
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* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*
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* mk_pte takes a (struct page *) as input
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*/
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#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
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static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
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{
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pte_t pte;
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pte_val(pte) = (pfn << PTE_RPN_SHIFT) | pgprot_val(pgprot);
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return pte;
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}
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#define pte_modify(_pte, newprot) \
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(__pte((pte_val(_pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)))
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#define pte_none(pte) ((pte_val(pte) & ~_PAGE_HPTEFLAGS) == 0)
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#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
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/* pte_clear moved to later in this file */
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#define pte_pfn(x) ((unsigned long)((pte_val(x)>>PTE_RPN_SHIFT)))
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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#define PMD_BAD_BITS (PTE_TABLE_SIZE-1)
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#define PUD_BAD_BITS (PMD_TABLE_SIZE-1)
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#define pmd_set(pmdp, pmdval) (pmd_val(*(pmdp)) = (pmdval))
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#define pmd_none(pmd) (!pmd_val(pmd))
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#define pmd_bad(pmd) (!is_kernel_addr(pmd_val(pmd)) \
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|| (pmd_val(pmd) & PMD_BAD_BITS))
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#define pmd_present(pmd) (pmd_val(pmd) != 0)
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#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0)
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#define pmd_page_vaddr(pmd) (pmd_val(pmd) & ~PMD_MASKED_BITS)
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#define pmd_page(pmd) virt_to_page(pmd_page_vaddr(pmd))
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#define pud_set(pudp, pudval) (pud_val(*(pudp)) = (pudval))
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#define pud_none(pud) (!pud_val(pud))
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#define pud_bad(pud) (!is_kernel_addr(pud_val(pud)) \
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|| (pud_val(pud) & PUD_BAD_BITS))
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#define pud_present(pud) (pud_val(pud) != 0)
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#define pud_clear(pudp) (pud_val(*(pudp)) = 0)
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#define pud_page_vaddr(pud) (pud_val(pud) & ~PUD_MASKED_BITS)
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#define pud_page(pud) virt_to_page(pud_page_vaddr(pud))
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#define pgd_set(pgdp, pudp) ({pgd_val(*(pgdp)) = (unsigned long)(pudp);})
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/*
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* Find an entry in a page-table-directory. We combine the address region
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* (the high order N bits) and the pgd portion of the address.
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*/
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/* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */
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#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x1ff)
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#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
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#define pmd_offset(pudp,addr) \
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(((pmd_t *) pud_page_vaddr(*(pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
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#define pte_offset_kernel(dir,addr) \
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(((pte_t *) pmd_page_vaddr(*(dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
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#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
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#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
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#define pte_unmap(pte) do { } while(0)
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#define pte_unmap_nested(pte) do { } while(0)
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/* to find an entry in a kernel page-table-directory */
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/* This now only contains the vmalloc pages */
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#define pgd_offset_k(address) pgd_offset(&init_mm, address)
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/*
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* The following only work if pte_present() is true.
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* Undefined behaviour if not..
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*/
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static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW;}
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static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY;}
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static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED;}
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static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE;}
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static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
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static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; }
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static inline pte_t pte_wrprotect(pte_t pte) {
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pte_val(pte) &= ~(_PAGE_RW); return pte; }
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static inline pte_t pte_mkclean(pte_t pte) {
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pte_val(pte) &= ~(_PAGE_DIRTY); return pte; }
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static inline pte_t pte_mkold(pte_t pte) {
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pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
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static inline pte_t pte_mkwrite(pte_t pte) {
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pte_val(pte) |= _PAGE_RW; return pte; }
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static inline pte_t pte_mkdirty(pte_t pte) {
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pte_val(pte) |= _PAGE_DIRTY; return pte; }
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static inline pte_t pte_mkyoung(pte_t pte) {
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pte_val(pte) |= _PAGE_ACCESSED; return pte; }
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static inline pte_t pte_mkhuge(pte_t pte) {
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return pte; }
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/* Atomic PTE updates */
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static inline unsigned long pte_update(struct mm_struct *mm,
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unsigned long addr,
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pte_t *ptep, unsigned long clr,
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int huge)
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{
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unsigned long old, tmp;
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__asm__ __volatile__(
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"1: ldarx %0,0,%3 # pte_update\n\
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andi. %1,%0,%6\n\
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bne- 1b \n\
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andc %1,%0,%4 \n\
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stdcx. %1,0,%3 \n\
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bne- 1b"
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: "=&r" (old), "=&r" (tmp), "=m" (*ptep)
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: "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY)
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: "cc" );
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if (old & _PAGE_HASHPTE)
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hpte_need_flush(mm, addr, ptep, old, huge);
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return old;
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}
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static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
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unsigned long addr, pte_t *ptep)
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{
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unsigned long old;
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if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
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return 0;
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old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0);
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return (old & _PAGE_ACCESSED) != 0;
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}
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#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
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#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
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({ \
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int __r; \
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__r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
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__r; \
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})
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#define __HAVE_ARCH_PTEP_SET_WRPROTECT
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static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep)
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{
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unsigned long old;
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if ((pte_val(*ptep) & _PAGE_RW) == 0)
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return;
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old = pte_update(mm, addr, ptep, _PAGE_RW, 0);
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}
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/*
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* We currently remove entries from the hashtable regardless of whether
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* the entry was young or dirty. The generic routines only flush if the
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* entry was young or dirty which is not good enough.
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*
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* We should be more intelligent about this but for the moment we override
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* these functions and force a tlb flush unconditionally
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*/
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#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
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#define ptep_clear_flush_young(__vma, __address, __ptep) \
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({ \
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int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
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__ptep); \
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__young; \
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})
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#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
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static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
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unsigned long addr, pte_t *ptep)
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{
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unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0);
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return __pte(old);
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}
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static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
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pte_t * ptep)
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{
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pte_update(mm, addr, ptep, ~0UL, 0);
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}
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/*
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* set_pte stores a linux PTE into the linux page table.
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*/
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static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, pte_t pte)
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{
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if (pte_present(*ptep))
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pte_clear(mm, addr, ptep);
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pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
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*ptep = pte;
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}
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/* Set the dirty and/or accessed bits atomically in a linux PTE, this
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* function doesn't need to flush the hash entry
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*/
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#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
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static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
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{
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unsigned long bits = pte_val(entry) &
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(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
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unsigned long old, tmp;
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__asm__ __volatile__(
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"1: ldarx %0,0,%4\n\
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andi. %1,%0,%6\n\
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bne- 1b \n\
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or %0,%3,%0\n\
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stdcx. %0,0,%4\n\
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bne- 1b"
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:"=&r" (old), "=&r" (tmp), "=m" (*ptep)
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:"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
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:"cc");
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}
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#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
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({ \
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int __changed = !pte_same(*(__ptep), __entry); \
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if (__changed) { \
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__ptep_set_access_flags(__ptep, __entry, __dirty); \
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flush_tlb_page_nohash(__vma, __address); \
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} \
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__changed; \
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})
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/*
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* Macro to mark a page protection value as "uncacheable".
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*/
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#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
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struct file;
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extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
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unsigned long size, pgprot_t vma_prot);
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#define __HAVE_PHYS_MEM_ACCESS_PROT
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#define __HAVE_ARCH_PTE_SAME
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#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
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#define pte_ERROR(e) \
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printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
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#define pmd_ERROR(e) \
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printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
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#define pgd_ERROR(e) \
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printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
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/* Encode and de-code a swap entry */
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#define __swp_type(entry) (((entry).val >> 1) & 0x3f)
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#define __swp_offset(entry) ((entry).val >> 8)
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#define __swp_entry(type, offset) ((swp_entry_t){((type)<< 1)|((offset)<<8)})
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#define __pte_to_swp_entry(pte) ((swp_entry_t){pte_val(pte) >> PTE_RPN_SHIFT})
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val << PTE_RPN_SHIFT })
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#define pte_to_pgoff(pte) (pte_val(pte) >> PTE_RPN_SHIFT)
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#define pgoff_to_pte(off) ((pte_t) {((off) << PTE_RPN_SHIFT)|_PAGE_FILE})
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#define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_RPN_SHIFT)
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void pgtable_cache_init(void);
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/*
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* find_linux_pte returns the address of a linux pte for a given
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* effective address and directory. If not found, it returns zero.
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*/static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea)
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{
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pgd_t *pg;
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pud_t *pu;
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pmd_t *pm;
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pte_t *pt = NULL;
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pg = pgdir + pgd_index(ea);
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if (!pgd_none(*pg)) {
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pu = pud_offset(pg, ea);
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if (!pud_none(*pu)) {
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pm = pmd_offset(pu, ea);
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if (pmd_present(*pm))
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pt = pte_offset_kernel(pm, ea);
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}
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}
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return pt;
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}
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_POWERPC_PGTABLE_PPC64_H_ */
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