568 строки
16 KiB
C
568 строки
16 KiB
C
/*
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* AMD Memory Encryption Support
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*
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* Copyright (C) 2016 Advanced Micro Devices, Inc.
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*
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* Author: Tom Lendacky <thomas.lendacky@amd.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define DISABLE_BRANCH_PROFILING
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/*
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* Since we're dealing with identity mappings, physical and virtual
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* addresses are the same, so override these defines which are ultimately
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* used by the headers in misc.h.
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*/
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#define __pa(x) ((unsigned long)(x))
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#define __va(x) ((void *)((unsigned long)(x)))
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/*
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* Special hack: we have to be careful, because no indirections are
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* allowed here, and paravirt_ops is a kind of one. As it will only run in
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* baremetal anyway, we just keep it from happening. (This list needs to
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* be extended when new paravirt and debugging variants are added.)
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*/
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#undef CONFIG_PARAVIRT
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#undef CONFIG_PARAVIRT_SPINLOCKS
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/mem_encrypt.h>
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#include <asm/setup.h>
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#include <asm/sections.h>
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#include <asm/cmdline.h>
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#include "mm_internal.h"
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#define PGD_FLAGS _KERNPG_TABLE_NOENC
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#define P4D_FLAGS _KERNPG_TABLE_NOENC
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#define PUD_FLAGS _KERNPG_TABLE_NOENC
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#define PMD_FLAGS _KERNPG_TABLE_NOENC
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#define PMD_FLAGS_LARGE (__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL)
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#define PMD_FLAGS_DEC PMD_FLAGS_LARGE
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#define PMD_FLAGS_DEC_WP ((PMD_FLAGS_DEC & ~_PAGE_CACHE_MASK) | \
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(_PAGE_PAT | _PAGE_PWT))
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#define PMD_FLAGS_ENC (PMD_FLAGS_LARGE | _PAGE_ENC)
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#define PTE_FLAGS (__PAGE_KERNEL_EXEC & ~_PAGE_GLOBAL)
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#define PTE_FLAGS_DEC PTE_FLAGS
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#define PTE_FLAGS_DEC_WP ((PTE_FLAGS_DEC & ~_PAGE_CACHE_MASK) | \
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(_PAGE_PAT | _PAGE_PWT))
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#define PTE_FLAGS_ENC (PTE_FLAGS | _PAGE_ENC)
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struct sme_populate_pgd_data {
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void *pgtable_area;
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pgd_t *pgd;
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pmdval_t pmd_flags;
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pteval_t pte_flags;
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unsigned long paddr;
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unsigned long vaddr;
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unsigned long vaddr_end;
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};
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static char sme_cmdline_arg[] __initdata = "mem_encrypt";
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static char sme_cmdline_on[] __initdata = "on";
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static char sme_cmdline_off[] __initdata = "off";
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static void __init sme_clear_pgd(struct sme_populate_pgd_data *ppd)
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{
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unsigned long pgd_start, pgd_end, pgd_size;
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pgd_t *pgd_p;
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pgd_start = ppd->vaddr & PGDIR_MASK;
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pgd_end = ppd->vaddr_end & PGDIR_MASK;
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pgd_size = (((pgd_end - pgd_start) / PGDIR_SIZE) + 1) * sizeof(pgd_t);
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pgd_p = ppd->pgd + pgd_index(ppd->vaddr);
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memset(pgd_p, 0, pgd_size);
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}
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static pud_t __init *sme_prepare_pgd(struct sme_populate_pgd_data *ppd)
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{
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pgd_t *pgd;
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p4d_t *p4d;
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pud_t *pud;
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pmd_t *pmd;
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pgd = ppd->pgd + pgd_index(ppd->vaddr);
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if (pgd_none(*pgd)) {
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p4d = ppd->pgtable_area;
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memset(p4d, 0, sizeof(*p4d) * PTRS_PER_P4D);
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ppd->pgtable_area += sizeof(*p4d) * PTRS_PER_P4D;
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set_pgd(pgd, __pgd(PGD_FLAGS | __pa(p4d)));
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}
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p4d = p4d_offset(pgd, ppd->vaddr);
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if (p4d_none(*p4d)) {
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pud = ppd->pgtable_area;
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memset(pud, 0, sizeof(*pud) * PTRS_PER_PUD);
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ppd->pgtable_area += sizeof(*pud) * PTRS_PER_PUD;
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set_p4d(p4d, __p4d(P4D_FLAGS | __pa(pud)));
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}
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pud = pud_offset(p4d, ppd->vaddr);
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if (pud_none(*pud)) {
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pmd = ppd->pgtable_area;
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memset(pmd, 0, sizeof(*pmd) * PTRS_PER_PMD);
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ppd->pgtable_area += sizeof(*pmd) * PTRS_PER_PMD;
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set_pud(pud, __pud(PUD_FLAGS | __pa(pmd)));
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}
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if (pud_large(*pud))
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return NULL;
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return pud;
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}
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static void __init sme_populate_pgd_large(struct sme_populate_pgd_data *ppd)
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{
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pud_t *pud;
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pmd_t *pmd;
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pud = sme_prepare_pgd(ppd);
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if (!pud)
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return;
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pmd = pmd_offset(pud, ppd->vaddr);
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if (pmd_large(*pmd))
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return;
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set_pmd(pmd, __pmd(ppd->paddr | ppd->pmd_flags));
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}
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static void __init sme_populate_pgd(struct sme_populate_pgd_data *ppd)
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{
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pud_t *pud;
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pmd_t *pmd;
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pte_t *pte;
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pud = sme_prepare_pgd(ppd);
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if (!pud)
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return;
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pmd = pmd_offset(pud, ppd->vaddr);
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if (pmd_none(*pmd)) {
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pte = ppd->pgtable_area;
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memset(pte, 0, sizeof(pte) * PTRS_PER_PTE);
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ppd->pgtable_area += sizeof(pte) * PTRS_PER_PTE;
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set_pmd(pmd, __pmd(PMD_FLAGS | __pa(pte)));
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}
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if (pmd_large(*pmd))
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return;
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pte = pte_offset_map(pmd, ppd->vaddr);
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if (pte_none(*pte))
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set_pte(pte, __pte(ppd->paddr | ppd->pte_flags));
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}
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static void __init __sme_map_range_pmd(struct sme_populate_pgd_data *ppd)
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{
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while (ppd->vaddr < ppd->vaddr_end) {
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sme_populate_pgd_large(ppd);
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ppd->vaddr += PMD_PAGE_SIZE;
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ppd->paddr += PMD_PAGE_SIZE;
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}
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}
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static void __init __sme_map_range_pte(struct sme_populate_pgd_data *ppd)
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{
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while (ppd->vaddr < ppd->vaddr_end) {
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sme_populate_pgd(ppd);
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ppd->vaddr += PAGE_SIZE;
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ppd->paddr += PAGE_SIZE;
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}
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}
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static void __init __sme_map_range(struct sme_populate_pgd_data *ppd,
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pmdval_t pmd_flags, pteval_t pte_flags)
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{
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unsigned long vaddr_end;
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ppd->pmd_flags = pmd_flags;
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ppd->pte_flags = pte_flags;
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/* Save original end value since we modify the struct value */
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vaddr_end = ppd->vaddr_end;
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/* If start is not 2MB aligned, create PTE entries */
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ppd->vaddr_end = ALIGN(ppd->vaddr, PMD_PAGE_SIZE);
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__sme_map_range_pte(ppd);
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/* Create PMD entries */
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ppd->vaddr_end = vaddr_end & PMD_PAGE_MASK;
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__sme_map_range_pmd(ppd);
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/* If end is not 2MB aligned, create PTE entries */
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ppd->vaddr_end = vaddr_end;
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__sme_map_range_pte(ppd);
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}
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static void __init sme_map_range_encrypted(struct sme_populate_pgd_data *ppd)
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{
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__sme_map_range(ppd, PMD_FLAGS_ENC, PTE_FLAGS_ENC);
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}
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static void __init sme_map_range_decrypted(struct sme_populate_pgd_data *ppd)
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{
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__sme_map_range(ppd, PMD_FLAGS_DEC, PTE_FLAGS_DEC);
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}
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static void __init sme_map_range_decrypted_wp(struct sme_populate_pgd_data *ppd)
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{
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__sme_map_range(ppd, PMD_FLAGS_DEC_WP, PTE_FLAGS_DEC_WP);
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}
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static unsigned long __init sme_pgtable_calc(unsigned long len)
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{
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unsigned long entries = 0, tables = 0;
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/*
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* Perform a relatively simplistic calculation of the pagetable
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* entries that are needed. Those mappings will be covered mostly
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* by 2MB PMD entries so we can conservatively calculate the required
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* number of P4D, PUD and PMD structures needed to perform the
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* mappings. For mappings that are not 2MB aligned, PTE mappings
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* would be needed for the start and end portion of the address range
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* that fall outside of the 2MB alignment. This results in, at most,
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* two extra pages to hold PTE entries for each range that is mapped.
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* Incrementing the count for each covers the case where the addresses
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* cross entries.
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*/
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/* PGDIR_SIZE is equal to P4D_SIZE on 4-level machine. */
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if (PTRS_PER_P4D > 1)
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entries += (DIV_ROUND_UP(len, PGDIR_SIZE) + 1) * sizeof(p4d_t) * PTRS_PER_P4D;
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entries += (DIV_ROUND_UP(len, P4D_SIZE) + 1) * sizeof(pud_t) * PTRS_PER_PUD;
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entries += (DIV_ROUND_UP(len, PUD_SIZE) + 1) * sizeof(pmd_t) * PTRS_PER_PMD;
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entries += 2 * sizeof(pte_t) * PTRS_PER_PTE;
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/*
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* Now calculate the added pagetable structures needed to populate
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* the new pagetables.
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*/
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if (PTRS_PER_P4D > 1)
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tables += DIV_ROUND_UP(entries, PGDIR_SIZE) * sizeof(p4d_t) * PTRS_PER_P4D;
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tables += DIV_ROUND_UP(entries, P4D_SIZE) * sizeof(pud_t) * PTRS_PER_PUD;
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tables += DIV_ROUND_UP(entries, PUD_SIZE) * sizeof(pmd_t) * PTRS_PER_PMD;
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return entries + tables;
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}
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void __init sme_encrypt_kernel(struct boot_params *bp)
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{
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unsigned long workarea_start, workarea_end, workarea_len;
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unsigned long execute_start, execute_end, execute_len;
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unsigned long kernel_start, kernel_end, kernel_len;
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unsigned long initrd_start, initrd_end, initrd_len;
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struct sme_populate_pgd_data ppd;
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unsigned long pgtable_area_len;
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unsigned long decrypted_base;
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if (!sme_active())
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return;
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/*
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* Prepare for encrypting the kernel and initrd by building new
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* pagetables with the necessary attributes needed to encrypt the
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* kernel in place.
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*
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* One range of virtual addresses will map the memory occupied
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* by the kernel and initrd as encrypted.
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*
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* Another range of virtual addresses will map the memory occupied
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* by the kernel and initrd as decrypted and write-protected.
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*
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* The use of write-protect attribute will prevent any of the
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* memory from being cached.
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*/
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/* Physical addresses gives us the identity mapped virtual addresses */
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kernel_start = __pa_symbol(_text);
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kernel_end = ALIGN(__pa_symbol(_end), PMD_PAGE_SIZE);
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kernel_len = kernel_end - kernel_start;
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initrd_start = 0;
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initrd_end = 0;
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initrd_len = 0;
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#ifdef CONFIG_BLK_DEV_INITRD
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initrd_len = (unsigned long)bp->hdr.ramdisk_size |
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((unsigned long)bp->ext_ramdisk_size << 32);
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if (initrd_len) {
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initrd_start = (unsigned long)bp->hdr.ramdisk_image |
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((unsigned long)bp->ext_ramdisk_image << 32);
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initrd_end = PAGE_ALIGN(initrd_start + initrd_len);
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initrd_len = initrd_end - initrd_start;
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}
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#endif
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/* Set the encryption workarea to be immediately after the kernel */
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workarea_start = kernel_end;
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/*
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* Calculate required number of workarea bytes needed:
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* executable encryption area size:
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* stack page (PAGE_SIZE)
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* encryption routine page (PAGE_SIZE)
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* intermediate copy buffer (PMD_PAGE_SIZE)
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* pagetable structures for the encryption of the kernel
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* pagetable structures for workarea (in case not currently mapped)
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*/
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execute_start = workarea_start;
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execute_end = execute_start + (PAGE_SIZE * 2) + PMD_PAGE_SIZE;
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execute_len = execute_end - execute_start;
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/*
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* One PGD for both encrypted and decrypted mappings and a set of
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* PUDs and PMDs for each of the encrypted and decrypted mappings.
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*/
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pgtable_area_len = sizeof(pgd_t) * PTRS_PER_PGD;
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pgtable_area_len += sme_pgtable_calc(execute_end - kernel_start) * 2;
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if (initrd_len)
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pgtable_area_len += sme_pgtable_calc(initrd_len) * 2;
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/* PUDs and PMDs needed in the current pagetables for the workarea */
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pgtable_area_len += sme_pgtable_calc(execute_len + pgtable_area_len);
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/*
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* The total workarea includes the executable encryption area and
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* the pagetable area. The start of the workarea is already 2MB
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* aligned, align the end of the workarea on a 2MB boundary so that
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* we don't try to create/allocate PTE entries from the workarea
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* before it is mapped.
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*/
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workarea_len = execute_len + pgtable_area_len;
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workarea_end = ALIGN(workarea_start + workarea_len, PMD_PAGE_SIZE);
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/*
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* Set the address to the start of where newly created pagetable
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* structures (PGDs, PUDs and PMDs) will be allocated. New pagetable
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* structures are created when the workarea is added to the current
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* pagetables and when the new encrypted and decrypted kernel
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* mappings are populated.
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*/
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ppd.pgtable_area = (void *)execute_end;
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/*
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* Make sure the current pagetable structure has entries for
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* addressing the workarea.
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*/
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ppd.pgd = (pgd_t *)native_read_cr3_pa();
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ppd.paddr = workarea_start;
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ppd.vaddr = workarea_start;
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ppd.vaddr_end = workarea_end;
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sme_map_range_decrypted(&ppd);
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/* Flush the TLB - no globals so cr3 is enough */
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native_write_cr3(__native_read_cr3());
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/*
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* A new pagetable structure is being built to allow for the kernel
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* and initrd to be encrypted. It starts with an empty PGD that will
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* then be populated with new PUDs and PMDs as the encrypted and
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* decrypted kernel mappings are created.
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*/
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ppd.pgd = ppd.pgtable_area;
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memset(ppd.pgd, 0, sizeof(pgd_t) * PTRS_PER_PGD);
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ppd.pgtable_area += sizeof(pgd_t) * PTRS_PER_PGD;
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/*
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* A different PGD index/entry must be used to get different
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* pagetable entries for the decrypted mapping. Choose the next
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* PGD index and convert it to a virtual address to be used as
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* the base of the mapping.
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*/
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decrypted_base = (pgd_index(workarea_end) + 1) & (PTRS_PER_PGD - 1);
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if (initrd_len) {
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unsigned long check_base;
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check_base = (pgd_index(initrd_end) + 1) & (PTRS_PER_PGD - 1);
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decrypted_base = max(decrypted_base, check_base);
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}
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decrypted_base <<= PGDIR_SHIFT;
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/* Add encrypted kernel (identity) mappings */
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ppd.paddr = kernel_start;
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ppd.vaddr = kernel_start;
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ppd.vaddr_end = kernel_end;
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sme_map_range_encrypted(&ppd);
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/* Add decrypted, write-protected kernel (non-identity) mappings */
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ppd.paddr = kernel_start;
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ppd.vaddr = kernel_start + decrypted_base;
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ppd.vaddr_end = kernel_end + decrypted_base;
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sme_map_range_decrypted_wp(&ppd);
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if (initrd_len) {
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/* Add encrypted initrd (identity) mappings */
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ppd.paddr = initrd_start;
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ppd.vaddr = initrd_start;
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ppd.vaddr_end = initrd_end;
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sme_map_range_encrypted(&ppd);
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/*
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* Add decrypted, write-protected initrd (non-identity) mappings
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*/
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ppd.paddr = initrd_start;
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ppd.vaddr = initrd_start + decrypted_base;
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ppd.vaddr_end = initrd_end + decrypted_base;
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sme_map_range_decrypted_wp(&ppd);
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}
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/* Add decrypted workarea mappings to both kernel mappings */
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ppd.paddr = workarea_start;
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ppd.vaddr = workarea_start;
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ppd.vaddr_end = workarea_end;
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sme_map_range_decrypted(&ppd);
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ppd.paddr = workarea_start;
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ppd.vaddr = workarea_start + decrypted_base;
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ppd.vaddr_end = workarea_end + decrypted_base;
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sme_map_range_decrypted(&ppd);
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/* Perform the encryption */
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sme_encrypt_execute(kernel_start, kernel_start + decrypted_base,
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kernel_len, workarea_start, (unsigned long)ppd.pgd);
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if (initrd_len)
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sme_encrypt_execute(initrd_start, initrd_start + decrypted_base,
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initrd_len, workarea_start,
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(unsigned long)ppd.pgd);
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/*
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* At this point we are running encrypted. Remove the mappings for
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* the decrypted areas - all that is needed for this is to remove
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* the PGD entry/entries.
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*/
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ppd.vaddr = kernel_start + decrypted_base;
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ppd.vaddr_end = kernel_end + decrypted_base;
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sme_clear_pgd(&ppd);
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if (initrd_len) {
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ppd.vaddr = initrd_start + decrypted_base;
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ppd.vaddr_end = initrd_end + decrypted_base;
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sme_clear_pgd(&ppd);
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}
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ppd.vaddr = workarea_start + decrypted_base;
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ppd.vaddr_end = workarea_end + decrypted_base;
|
|
sme_clear_pgd(&ppd);
|
|
|
|
/* Flush the TLB - no globals so cr3 is enough */
|
|
native_write_cr3(__native_read_cr3());
|
|
}
|
|
|
|
void __init sme_enable(struct boot_params *bp)
|
|
{
|
|
const char *cmdline_ptr, *cmdline_arg, *cmdline_on, *cmdline_off;
|
|
unsigned int eax, ebx, ecx, edx;
|
|
unsigned long feature_mask;
|
|
bool active_by_default;
|
|
unsigned long me_mask;
|
|
char buffer[16];
|
|
u64 msr;
|
|
|
|
/* Check for the SME/SEV support leaf */
|
|
eax = 0x80000000;
|
|
ecx = 0;
|
|
native_cpuid(&eax, &ebx, &ecx, &edx);
|
|
if (eax < 0x8000001f)
|
|
return;
|
|
|
|
#define AMD_SME_BIT BIT(0)
|
|
#define AMD_SEV_BIT BIT(1)
|
|
/*
|
|
* Set the feature mask (SME or SEV) based on whether we are
|
|
* running under a hypervisor.
|
|
*/
|
|
eax = 1;
|
|
ecx = 0;
|
|
native_cpuid(&eax, &ebx, &ecx, &edx);
|
|
feature_mask = (ecx & BIT(31)) ? AMD_SEV_BIT : AMD_SME_BIT;
|
|
|
|
/*
|
|
* Check for the SME/SEV feature:
|
|
* CPUID Fn8000_001F[EAX]
|
|
* - Bit 0 - Secure Memory Encryption support
|
|
* - Bit 1 - Secure Encrypted Virtualization support
|
|
* CPUID Fn8000_001F[EBX]
|
|
* - Bits 5:0 - Pagetable bit position used to indicate encryption
|
|
*/
|
|
eax = 0x8000001f;
|
|
ecx = 0;
|
|
native_cpuid(&eax, &ebx, &ecx, &edx);
|
|
if (!(eax & feature_mask))
|
|
return;
|
|
|
|
me_mask = 1UL << (ebx & 0x3f);
|
|
|
|
/* Check if memory encryption is enabled */
|
|
if (feature_mask == AMD_SME_BIT) {
|
|
/* For SME, check the SYSCFG MSR */
|
|
msr = __rdmsr(MSR_K8_SYSCFG);
|
|
if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
|
|
return;
|
|
} else {
|
|
/* For SEV, check the SEV MSR */
|
|
msr = __rdmsr(MSR_AMD64_SEV);
|
|
if (!(msr & MSR_AMD64_SEV_ENABLED))
|
|
return;
|
|
|
|
/* SEV state cannot be controlled by a command line option */
|
|
sme_me_mask = me_mask;
|
|
sev_enabled = true;
|
|
physical_mask &= ~sme_me_mask;
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Fixups have not been applied to phys_base yet and we're running
|
|
* identity mapped, so we must obtain the address to the SME command
|
|
* line argument data using rip-relative addressing.
|
|
*/
|
|
asm ("lea sme_cmdline_arg(%%rip), %0"
|
|
: "=r" (cmdline_arg)
|
|
: "p" (sme_cmdline_arg));
|
|
asm ("lea sme_cmdline_on(%%rip), %0"
|
|
: "=r" (cmdline_on)
|
|
: "p" (sme_cmdline_on));
|
|
asm ("lea sme_cmdline_off(%%rip), %0"
|
|
: "=r" (cmdline_off)
|
|
: "p" (sme_cmdline_off));
|
|
|
|
if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT))
|
|
active_by_default = true;
|
|
else
|
|
active_by_default = false;
|
|
|
|
cmdline_ptr = (const char *)((u64)bp->hdr.cmd_line_ptr |
|
|
((u64)bp->ext_cmd_line_ptr << 32));
|
|
|
|
cmdline_find_option(cmdline_ptr, cmdline_arg, buffer, sizeof(buffer));
|
|
|
|
if (!strncmp(buffer, cmdline_on, sizeof(buffer)))
|
|
sme_me_mask = me_mask;
|
|
else if (!strncmp(buffer, cmdline_off, sizeof(buffer)))
|
|
sme_me_mask = 0;
|
|
else
|
|
sme_me_mask = active_by_default ? me_mask : 0;
|
|
|
|
physical_mask &= ~sme_me_mask;
|
|
}
|