880 строки
22 KiB
C
880 строки
22 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Dave DNET Ethernet Controller driver
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*
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* Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
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* Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
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*/
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/phy.h>
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#include "dnet.h"
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#undef DEBUG
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/* function for reading internal MAC register */
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static u16 dnet_readw_mac(struct dnet *bp, u16 reg)
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{
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u16 data_read;
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/* issue a read */
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dnet_writel(bp, reg, MACREG_ADDR);
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/* since a read/write op to the MAC is very slow,
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* we must wait before reading the data */
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ndelay(500);
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/* read data read from the MAC register */
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data_read = dnet_readl(bp, MACREG_DATA);
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/* all done */
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return data_read;
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}
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/* function for writing internal MAC register */
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static void dnet_writew_mac(struct dnet *bp, u16 reg, u16 val)
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{
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/* load data to write */
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dnet_writel(bp, val, MACREG_DATA);
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/* issue a write */
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dnet_writel(bp, reg | DNET_INTERNAL_WRITE, MACREG_ADDR);
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/* since a read/write op to the MAC is very slow,
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* we must wait before exiting */
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ndelay(500);
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}
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static void __dnet_set_hwaddr(struct dnet *bp)
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{
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u16 tmp;
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tmp = be16_to_cpup((const __be16 *)bp->dev->dev_addr);
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dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG, tmp);
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tmp = be16_to_cpup((const __be16 *)(bp->dev->dev_addr + 2));
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dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG, tmp);
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tmp = be16_to_cpup((const __be16 *)(bp->dev->dev_addr + 4));
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dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG, tmp);
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}
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static void dnet_get_hwaddr(struct dnet *bp)
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{
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u16 tmp;
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u8 addr[6];
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/*
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* from MAC docs:
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* "Note that the MAC address is stored in the registers in Hexadecimal
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* form. For example, to set the MAC Address to: AC-DE-48-00-00-80
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* would require writing 0xAC (octet 0) to address 0x0B (high byte of
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* Mac_addr[15:0]), 0xDE (octet 1) to address 0x0A (Low byte of
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* Mac_addr[15:0]), 0x48 (octet 2) to address 0x0D (high byte of
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* Mac_addr[15:0]), 0x00 (octet 3) to address 0x0C (Low byte of
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* Mac_addr[15:0]), 0x00 (octet 4) to address 0x0F (high byte of
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* Mac_addr[15:0]), and 0x80 (octet 5) to address * 0x0E (Low byte of
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* Mac_addr[15:0]).
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*/
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tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG);
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*((__be16 *)addr) = cpu_to_be16(tmp);
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tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG);
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*((__be16 *)(addr + 2)) = cpu_to_be16(tmp);
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tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG);
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*((__be16 *)(addr + 4)) = cpu_to_be16(tmp);
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if (is_valid_ether_addr(addr))
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eth_hw_addr_set(bp->dev, addr);
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}
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static int dnet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
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{
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struct dnet *bp = bus->priv;
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u16 value;
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while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
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& DNET_INTERNAL_GMII_MNG_CMD_FIN))
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cpu_relax();
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/* only 5 bits allowed for phy-addr and reg_offset */
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mii_id &= 0x1f;
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regnum &= 0x1f;
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/* prepare reg_value for a read */
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value = (mii_id << 8);
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value |= regnum;
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/* write control word */
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dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, value);
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/* wait for end of transfer */
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while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
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& DNET_INTERNAL_GMII_MNG_CMD_FIN))
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cpu_relax();
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value = dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG);
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pr_debug("mdio_read %02x:%02x <- %04x\n", mii_id, regnum, value);
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return value;
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}
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static int dnet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
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u16 value)
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{
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struct dnet *bp = bus->priv;
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u16 tmp;
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pr_debug("mdio_write %02x:%02x <- %04x\n", mii_id, regnum, value);
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while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
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& DNET_INTERNAL_GMII_MNG_CMD_FIN))
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cpu_relax();
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/* prepare for a write operation */
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tmp = (1 << 13);
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/* only 5 bits allowed for phy-addr and reg_offset */
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mii_id &= 0x1f;
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regnum &= 0x1f;
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/* only 16 bits on data */
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value &= 0xffff;
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/* prepare reg_value for a write */
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tmp |= (mii_id << 8);
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tmp |= regnum;
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/* write data to write first */
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dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG, value);
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/* write control word */
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dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, tmp);
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while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
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& DNET_INTERNAL_GMII_MNG_CMD_FIN))
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cpu_relax();
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return 0;
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}
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static void dnet_handle_link_change(struct net_device *dev)
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{
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struct dnet *bp = netdev_priv(dev);
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struct phy_device *phydev = dev->phydev;
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unsigned long flags;
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u32 mode_reg, ctl_reg;
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int status_change = 0;
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spin_lock_irqsave(&bp->lock, flags);
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mode_reg = dnet_readw_mac(bp, DNET_INTERNAL_MODE_REG);
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ctl_reg = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG);
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if (phydev->link) {
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if (bp->duplex != phydev->duplex) {
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if (phydev->duplex)
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ctl_reg &=
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~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP);
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else
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ctl_reg |=
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DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP;
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bp->duplex = phydev->duplex;
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status_change = 1;
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}
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if (bp->speed != phydev->speed) {
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status_change = 1;
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switch (phydev->speed) {
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case 1000:
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mode_reg |= DNET_INTERNAL_MODE_GBITEN;
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break;
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case 100:
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case 10:
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mode_reg &= ~DNET_INTERNAL_MODE_GBITEN;
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break;
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default:
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printk(KERN_WARNING
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"%s: Ack! Speed (%d) is not "
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"10/100/1000!\n", dev->name,
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phydev->speed);
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break;
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}
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bp->speed = phydev->speed;
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}
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}
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if (phydev->link != bp->link) {
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if (phydev->link) {
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mode_reg |=
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(DNET_INTERNAL_MODE_RXEN | DNET_INTERNAL_MODE_TXEN);
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} else {
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mode_reg &=
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~(DNET_INTERNAL_MODE_RXEN |
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DNET_INTERNAL_MODE_TXEN);
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bp->speed = 0;
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bp->duplex = -1;
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}
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bp->link = phydev->link;
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status_change = 1;
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}
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if (status_change) {
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dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg);
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dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, mode_reg);
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}
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spin_unlock_irqrestore(&bp->lock, flags);
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if (status_change) {
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if (phydev->link)
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printk(KERN_INFO "%s: link up (%d/%s)\n",
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dev->name, phydev->speed,
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DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
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else
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printk(KERN_INFO "%s: link down\n", dev->name);
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}
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}
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static int dnet_mii_probe(struct net_device *dev)
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{
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struct dnet *bp = netdev_priv(dev);
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struct phy_device *phydev = NULL;
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/* find the first phy */
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phydev = phy_find_first(bp->mii_bus);
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if (!phydev) {
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printk(KERN_ERR "%s: no PHY found\n", dev->name);
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return -ENODEV;
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}
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/* TODO : add pin_irq */
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/* attach the mac to the phy */
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if (bp->capabilities & DNET_HAS_RMII) {
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phydev = phy_connect(dev, phydev_name(phydev),
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&dnet_handle_link_change,
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PHY_INTERFACE_MODE_RMII);
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} else {
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phydev = phy_connect(dev, phydev_name(phydev),
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&dnet_handle_link_change,
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PHY_INTERFACE_MODE_MII);
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}
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if (IS_ERR(phydev)) {
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printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
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return PTR_ERR(phydev);
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}
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/* mask with MAC supported features */
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if (bp->capabilities & DNET_HAS_GIGABIT)
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phy_set_max_speed(phydev, SPEED_1000);
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else
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phy_set_max_speed(phydev, SPEED_100);
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phy_support_asym_pause(phydev);
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bp->link = 0;
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bp->speed = 0;
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bp->duplex = -1;
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return 0;
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}
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static int dnet_mii_init(struct dnet *bp)
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{
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int err;
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bp->mii_bus = mdiobus_alloc();
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if (bp->mii_bus == NULL)
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return -ENOMEM;
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bp->mii_bus->name = "dnet_mii_bus";
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bp->mii_bus->read = &dnet_mdio_read;
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bp->mii_bus->write = &dnet_mdio_write;
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snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
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bp->pdev->name, bp->pdev->id);
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bp->mii_bus->priv = bp;
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if (mdiobus_register(bp->mii_bus)) {
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err = -ENXIO;
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goto err_out;
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}
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if (dnet_mii_probe(bp->dev) != 0) {
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err = -ENXIO;
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goto err_out_unregister_bus;
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}
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return 0;
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err_out_unregister_bus:
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mdiobus_unregister(bp->mii_bus);
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err_out:
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mdiobus_free(bp->mii_bus);
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return err;
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}
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/* For Neptune board: LINK1000 as Link LED and TX as activity LED */
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static int dnet_phy_marvell_fixup(struct phy_device *phydev)
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{
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return phy_write(phydev, 0x18, 0x4148);
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}
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static void dnet_update_stats(struct dnet *bp)
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{
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u32 __iomem *reg = bp->regs + DNET_RX_PKT_IGNR_CNT;
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u32 *p = &bp->hw_stats.rx_pkt_ignr;
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u32 *end = &bp->hw_stats.rx_byte + 1;
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WARN_ON((unsigned long)(end - p - 1) !=
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(DNET_RX_BYTE_CNT - DNET_RX_PKT_IGNR_CNT) / 4);
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for (; p < end; p++, reg++)
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*p += readl(reg);
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reg = bp->regs + DNET_TX_UNICAST_CNT;
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p = &bp->hw_stats.tx_unicast;
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end = &bp->hw_stats.tx_byte + 1;
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WARN_ON((unsigned long)(end - p - 1) !=
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(DNET_TX_BYTE_CNT - DNET_TX_UNICAST_CNT) / 4);
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for (; p < end; p++, reg++)
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*p += readl(reg);
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}
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static int dnet_poll(struct napi_struct *napi, int budget)
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{
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struct dnet *bp = container_of(napi, struct dnet, napi);
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struct net_device *dev = bp->dev;
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int npackets = 0;
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unsigned int pkt_len;
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struct sk_buff *skb;
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unsigned int *data_ptr;
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u32 int_enable;
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u32 cmd_word;
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int i;
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while (npackets < budget) {
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/*
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* break out of while loop if there are no more
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* packets waiting
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*/
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if (!(dnet_readl(bp, RX_FIFO_WCNT) >> 16))
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break;
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cmd_word = dnet_readl(bp, RX_LEN_FIFO);
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pkt_len = cmd_word & 0xFFFF;
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if (cmd_word & 0xDF180000)
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printk(KERN_ERR "%s packet receive error %x\n",
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__func__, cmd_word);
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skb = netdev_alloc_skb(dev, pkt_len + 5);
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if (skb != NULL) {
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/* Align IP on 16 byte boundaries */
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skb_reserve(skb, 2);
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/*
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* 'skb_put()' points to the start of sk_buff
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* data area.
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*/
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data_ptr = skb_put(skb, pkt_len);
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for (i = 0; i < (pkt_len + 3) >> 2; i++)
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*data_ptr++ = dnet_readl(bp, RX_DATA_FIFO);
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skb->protocol = eth_type_trans(skb, dev);
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netif_receive_skb(skb);
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npackets++;
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} else
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printk(KERN_NOTICE
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"%s: No memory to allocate a sk_buff of "
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"size %u.\n", dev->name, pkt_len);
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}
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if (npackets < budget) {
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/* We processed all packets available. Tell NAPI it can
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* stop polling then re-enable rx interrupts.
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*/
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napi_complete_done(napi, npackets);
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int_enable = dnet_readl(bp, INTR_ENB);
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int_enable |= DNET_INTR_SRC_RX_CMDFIFOAF;
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dnet_writel(bp, int_enable, INTR_ENB);
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}
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return npackets;
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}
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static irqreturn_t dnet_interrupt(int irq, void *dev_id)
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{
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struct net_device *dev = dev_id;
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struct dnet *bp = netdev_priv(dev);
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u32 int_src, int_enable, int_current;
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unsigned long flags;
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unsigned int handled = 0;
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spin_lock_irqsave(&bp->lock, flags);
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/* read and clear the DNET irq (clear on read) */
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int_src = dnet_readl(bp, INTR_SRC);
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int_enable = dnet_readl(bp, INTR_ENB);
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int_current = int_src & int_enable;
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/* restart the queue if we had stopped it for TX fifo almost full */
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if (int_current & DNET_INTR_SRC_TX_FIFOAE) {
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int_enable = dnet_readl(bp, INTR_ENB);
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int_enable &= ~DNET_INTR_ENB_TX_FIFOAE;
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dnet_writel(bp, int_enable, INTR_ENB);
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netif_wake_queue(dev);
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handled = 1;
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}
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/* RX FIFO error checking */
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if (int_current &
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(DNET_INTR_SRC_RX_CMDFIFOFF | DNET_INTR_SRC_RX_DATAFIFOFF)) {
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printk(KERN_ERR "%s: RX fifo error %x, irq %x\n", __func__,
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dnet_readl(bp, RX_STATUS), int_current);
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/* we can only flush the RX FIFOs */
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dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH, SYS_CTL);
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ndelay(500);
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dnet_writel(bp, 0, SYS_CTL);
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handled = 1;
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}
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/* TX FIFO error checking */
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if (int_current &
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(DNET_INTR_SRC_TX_FIFOFULL | DNET_INTR_SRC_TX_DISCFRM)) {
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printk(KERN_ERR "%s: TX fifo error %x, irq %x\n", __func__,
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dnet_readl(bp, TX_STATUS), int_current);
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/* we can only flush the TX FIFOs */
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dnet_writel(bp, DNET_SYS_CTL_TXFIFOFLUSH, SYS_CTL);
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ndelay(500);
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dnet_writel(bp, 0, SYS_CTL);
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handled = 1;
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}
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if (int_current & DNET_INTR_SRC_RX_CMDFIFOAF) {
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if (napi_schedule_prep(&bp->napi)) {
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/*
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* There's no point taking any more interrupts
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* until we have processed the buffers
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*/
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/* Disable Rx interrupts and schedule NAPI poll */
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int_enable = dnet_readl(bp, INTR_ENB);
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int_enable &= ~DNET_INTR_SRC_RX_CMDFIFOAF;
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dnet_writel(bp, int_enable, INTR_ENB);
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__napi_schedule(&bp->napi);
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}
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handled = 1;
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}
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if (!handled)
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pr_debug("%s: irq %x remains\n", __func__, int_current);
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spin_unlock_irqrestore(&bp->lock, flags);
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return IRQ_RETVAL(handled);
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}
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#ifdef DEBUG
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static inline void dnet_print_skb(struct sk_buff *skb)
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{
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int k;
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printk(KERN_DEBUG PFX "data:");
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for (k = 0; k < skb->len; k++)
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printk(" %02x", (unsigned int)skb->data[k]);
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printk("\n");
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}
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#else
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#define dnet_print_skb(skb) do {} while (0)
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#endif
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static netdev_tx_t dnet_start_xmit(struct sk_buff *skb, struct net_device *dev)
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{
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struct dnet *bp = netdev_priv(dev);
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unsigned int i, tx_cmd, wrsz;
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unsigned long flags;
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unsigned int *bufp;
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u32 irq_enable;
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dnet_readl(bp, TX_STATUS);
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pr_debug("start_xmit: len %u head %p data %p\n",
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skb->len, skb->head, skb->data);
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dnet_print_skb(skb);
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spin_lock_irqsave(&bp->lock, flags);
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dnet_readl(bp, TX_STATUS);
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bufp = (unsigned int *)(((unsigned long) skb->data) & ~0x3UL);
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wrsz = (u32) skb->len + 3;
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wrsz += ((unsigned long) skb->data) & 0x3;
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wrsz >>= 2;
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tx_cmd = ((((unsigned long)(skb->data)) & 0x03) << 16) | (u32) skb->len;
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/* check if there is enough room for the current frame */
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if (wrsz < (DNET_FIFO_SIZE - dnet_readl(bp, TX_FIFO_WCNT))) {
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for (i = 0; i < wrsz; i++)
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dnet_writel(bp, *bufp++, TX_DATA_FIFO);
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/*
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* inform MAC that a packet's written and ready to be
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* shipped out
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*/
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dnet_writel(bp, tx_cmd, TX_LEN_FIFO);
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}
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if (dnet_readl(bp, TX_FIFO_WCNT) > DNET_FIFO_TX_DATA_AF_TH) {
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netif_stop_queue(dev);
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dnet_readl(bp, INTR_SRC);
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irq_enable = dnet_readl(bp, INTR_ENB);
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irq_enable |= DNET_INTR_ENB_TX_FIFOAE;
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dnet_writel(bp, irq_enable, INTR_ENB);
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}
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skb_tx_timestamp(skb);
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/* free the buffer */
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dev_kfree_skb(skb);
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spin_unlock_irqrestore(&bp->lock, flags);
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return NETDEV_TX_OK;
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}
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static void dnet_reset_hw(struct dnet *bp)
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{
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/* put ts_mac in IDLE state i.e. disable rx/tx */
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dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, DNET_INTERNAL_MODE_FCEN);
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/*
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* RX FIFO almost full threshold: only cmd FIFO almost full is
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* implemented for RX side
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*/
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dnet_writel(bp, DNET_FIFO_RX_CMD_AF_TH, RX_FIFO_TH);
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/*
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* TX FIFO almost empty threshold: only data FIFO almost empty
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* is implemented for TX side
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*/
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dnet_writel(bp, DNET_FIFO_TX_DATA_AE_TH, TX_FIFO_TH);
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/* flush rx/tx fifos */
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dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH | DNET_SYS_CTL_TXFIFOFLUSH,
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SYS_CTL);
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msleep(1);
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dnet_writel(bp, 0, SYS_CTL);
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}
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static void dnet_init_hw(struct dnet *bp)
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{
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u32 config;
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dnet_reset_hw(bp);
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__dnet_set_hwaddr(bp);
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config = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG);
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if (bp->dev->flags & IFF_PROMISC)
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/* Copy All Frames */
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config |= DNET_INTERNAL_RXTX_CONTROL_ENPROMISC;
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if (!(bp->dev->flags & IFF_BROADCAST))
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/* No BroadCast */
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config |= DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST;
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config |= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE |
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DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST |
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DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL |
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DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS;
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dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, config);
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/* clear irq before enabling them */
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config = dnet_readl(bp, INTR_SRC);
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/* enable RX/TX interrupt, recv packet ready interrupt */
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dnet_writel(bp, DNET_INTR_ENB_GLOBAL_ENABLE | DNET_INTR_ENB_RX_SUMMARY |
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DNET_INTR_ENB_TX_SUMMARY | DNET_INTR_ENB_RX_FIFOERR |
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DNET_INTR_ENB_RX_ERROR | DNET_INTR_ENB_RX_FIFOFULL |
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DNET_INTR_ENB_TX_FIFOFULL | DNET_INTR_ENB_TX_DISCFRM |
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DNET_INTR_ENB_RX_PKTRDY, INTR_ENB);
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}
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static int dnet_open(struct net_device *dev)
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{
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struct dnet *bp = netdev_priv(dev);
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/* if the phy is not yet register, retry later */
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if (!dev->phydev)
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return -EAGAIN;
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napi_enable(&bp->napi);
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dnet_init_hw(bp);
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phy_start_aneg(dev->phydev);
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/* schedule a link state check */
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phy_start(dev->phydev);
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netif_start_queue(dev);
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return 0;
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}
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static int dnet_close(struct net_device *dev)
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{
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struct dnet *bp = netdev_priv(dev);
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netif_stop_queue(dev);
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napi_disable(&bp->napi);
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if (dev->phydev)
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phy_stop(dev->phydev);
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dnet_reset_hw(bp);
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netif_carrier_off(dev);
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return 0;
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}
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static inline void dnet_print_pretty_hwstats(struct dnet_stats *hwstat)
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{
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pr_debug("%s\n", __func__);
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pr_debug("----------------------------- RX statistics "
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"-------------------------------\n");
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pr_debug("RX_PKT_IGNR_CNT %-8x\n", hwstat->rx_pkt_ignr);
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pr_debug("RX_LEN_CHK_ERR_CNT %-8x\n", hwstat->rx_len_chk_err);
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pr_debug("RX_LNG_FRM_CNT %-8x\n", hwstat->rx_lng_frm);
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pr_debug("RX_SHRT_FRM_CNT %-8x\n", hwstat->rx_shrt_frm);
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pr_debug("RX_IPG_VIOL_CNT %-8x\n", hwstat->rx_ipg_viol);
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pr_debug("RX_CRC_ERR_CNT %-8x\n", hwstat->rx_crc_err);
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pr_debug("RX_OK_PKT_CNT %-8x\n", hwstat->rx_ok_pkt);
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pr_debug("RX_CTL_FRM_CNT %-8x\n", hwstat->rx_ctl_frm);
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pr_debug("RX_PAUSE_FRM_CNT %-8x\n", hwstat->rx_pause_frm);
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pr_debug("RX_MULTICAST_CNT %-8x\n", hwstat->rx_multicast);
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pr_debug("RX_BROADCAST_CNT %-8x\n", hwstat->rx_broadcast);
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pr_debug("RX_VLAN_TAG_CNT %-8x\n", hwstat->rx_vlan_tag);
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pr_debug("RX_PRE_SHRINK_CNT %-8x\n", hwstat->rx_pre_shrink);
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pr_debug("RX_DRIB_NIB_CNT %-8x\n", hwstat->rx_drib_nib);
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pr_debug("RX_UNSUP_OPCD_CNT %-8x\n", hwstat->rx_unsup_opcd);
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pr_debug("RX_BYTE_CNT %-8x\n", hwstat->rx_byte);
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pr_debug("----------------------------- TX statistics "
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"-------------------------------\n");
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pr_debug("TX_UNICAST_CNT %-8x\n", hwstat->tx_unicast);
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pr_debug("TX_PAUSE_FRM_CNT %-8x\n", hwstat->tx_pause_frm);
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pr_debug("TX_MULTICAST_CNT %-8x\n", hwstat->tx_multicast);
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pr_debug("TX_BRDCAST_CNT %-8x\n", hwstat->tx_brdcast);
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pr_debug("TX_VLAN_TAG_CNT %-8x\n", hwstat->tx_vlan_tag);
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pr_debug("TX_BAD_FCS_CNT %-8x\n", hwstat->tx_bad_fcs);
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pr_debug("TX_JUMBO_CNT %-8x\n", hwstat->tx_jumbo);
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pr_debug("TX_BYTE_CNT %-8x\n", hwstat->tx_byte);
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}
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static struct net_device_stats *dnet_get_stats(struct net_device *dev)
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{
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struct dnet *bp = netdev_priv(dev);
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struct net_device_stats *nstat = &dev->stats;
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struct dnet_stats *hwstat = &bp->hw_stats;
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/* read stats from hardware */
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dnet_update_stats(bp);
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/* Convert HW stats into netdevice stats */
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nstat->rx_errors = (hwstat->rx_len_chk_err +
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hwstat->rx_lng_frm + hwstat->rx_shrt_frm +
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/* ignore IGP violation error
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hwstat->rx_ipg_viol + */
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hwstat->rx_crc_err +
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hwstat->rx_pre_shrink +
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hwstat->rx_drib_nib + hwstat->rx_unsup_opcd);
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nstat->tx_errors = hwstat->tx_bad_fcs;
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nstat->rx_length_errors = (hwstat->rx_len_chk_err +
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hwstat->rx_lng_frm +
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hwstat->rx_shrt_frm + hwstat->rx_pre_shrink);
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nstat->rx_crc_errors = hwstat->rx_crc_err;
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nstat->rx_frame_errors = hwstat->rx_pre_shrink + hwstat->rx_drib_nib;
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nstat->rx_packets = hwstat->rx_ok_pkt;
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nstat->tx_packets = (hwstat->tx_unicast +
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hwstat->tx_multicast + hwstat->tx_brdcast);
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nstat->rx_bytes = hwstat->rx_byte;
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nstat->tx_bytes = hwstat->tx_byte;
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nstat->multicast = hwstat->rx_multicast;
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nstat->rx_missed_errors = hwstat->rx_pkt_ignr;
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dnet_print_pretty_hwstats(hwstat);
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return nstat;
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}
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static void dnet_get_drvinfo(struct net_device *dev,
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struct ethtool_drvinfo *info)
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{
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strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
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strlcpy(info->bus_info, "0", sizeof(info->bus_info));
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}
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static const struct ethtool_ops dnet_ethtool_ops = {
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.get_drvinfo = dnet_get_drvinfo,
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.get_link = ethtool_op_get_link,
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.get_ts_info = ethtool_op_get_ts_info,
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.get_link_ksettings = phy_ethtool_get_link_ksettings,
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.set_link_ksettings = phy_ethtool_set_link_ksettings,
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};
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static const struct net_device_ops dnet_netdev_ops = {
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.ndo_open = dnet_open,
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.ndo_stop = dnet_close,
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.ndo_get_stats = dnet_get_stats,
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.ndo_start_xmit = dnet_start_xmit,
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.ndo_eth_ioctl = phy_do_ioctl_running,
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.ndo_set_mac_address = eth_mac_addr,
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.ndo_validate_addr = eth_validate_addr,
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};
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static int dnet_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct net_device *dev;
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struct dnet *bp;
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struct phy_device *phydev;
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int err;
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unsigned int irq;
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irq = platform_get_irq(pdev, 0);
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dev = alloc_etherdev(sizeof(*bp));
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if (!dev)
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return -ENOMEM;
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/* TODO: Actually, we have some interesting features... */
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dev->features |= 0;
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bp = netdev_priv(dev);
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bp->dev = dev;
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platform_set_drvdata(pdev, dev);
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SET_NETDEV_DEV(dev, &pdev->dev);
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spin_lock_init(&bp->lock);
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bp->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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if (IS_ERR(bp->regs)) {
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err = PTR_ERR(bp->regs);
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goto err_out_free_dev;
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}
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dev->irq = irq;
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err = request_irq(dev->irq, dnet_interrupt, 0, DRV_NAME, dev);
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if (err) {
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dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
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irq, err);
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goto err_out_free_dev;
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}
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dev->netdev_ops = &dnet_netdev_ops;
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netif_napi_add(dev, &bp->napi, dnet_poll, 64);
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dev->ethtool_ops = &dnet_ethtool_ops;
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dev->base_addr = (unsigned long)bp->regs;
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bp->capabilities = dnet_readl(bp, VERCAPS) & DNET_CAPS_MASK;
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dnet_get_hwaddr(bp);
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if (!is_valid_ether_addr(dev->dev_addr)) {
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/* choose a random ethernet address */
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eth_hw_addr_random(dev);
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__dnet_set_hwaddr(bp);
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}
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err = register_netdev(dev);
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if (err) {
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dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
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goto err_out_free_irq;
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}
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/* register the PHY board fixup (for Marvell 88E1111) */
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err = phy_register_fixup_for_uid(0x01410cc0, 0xfffffff0,
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dnet_phy_marvell_fixup);
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/* we can live without it, so just issue a warning */
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if (err)
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dev_warn(&pdev->dev, "Cannot register PHY board fixup.\n");
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err = dnet_mii_init(bp);
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if (err)
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goto err_out_unregister_netdev;
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dev_info(&pdev->dev, "Dave DNET at 0x%p (0x%08x) irq %d %pM\n",
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bp->regs, (unsigned int)res->start, dev->irq, dev->dev_addr);
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dev_info(&pdev->dev, "has %smdio, %sirq, %sgigabit, %sdma\n",
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(bp->capabilities & DNET_HAS_MDIO) ? "" : "no ",
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(bp->capabilities & DNET_HAS_IRQ) ? "" : "no ",
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(bp->capabilities & DNET_HAS_GIGABIT) ? "" : "no ",
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(bp->capabilities & DNET_HAS_DMA) ? "" : "no ");
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phydev = dev->phydev;
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phy_attached_info(phydev);
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return 0;
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err_out_unregister_netdev:
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unregister_netdev(dev);
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err_out_free_irq:
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free_irq(dev->irq, dev);
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err_out_free_dev:
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free_netdev(dev);
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return err;
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}
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static int dnet_remove(struct platform_device *pdev)
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{
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struct net_device *dev;
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struct dnet *bp;
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dev = platform_get_drvdata(pdev);
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if (dev) {
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bp = netdev_priv(dev);
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if (dev->phydev)
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phy_disconnect(dev->phydev);
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mdiobus_unregister(bp->mii_bus);
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mdiobus_free(bp->mii_bus);
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unregister_netdev(dev);
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free_irq(dev->irq, dev);
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free_netdev(dev);
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}
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return 0;
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}
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static struct platform_driver dnet_driver = {
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.probe = dnet_probe,
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.remove = dnet_remove,
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.driver = {
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.name = "dnet",
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},
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};
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module_platform_driver(dnet_driver);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("Dave DNET Ethernet driver");
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MODULE_AUTHOR("Ilya Yanok <yanok@emcraft.com>, "
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"Matteo Vit <matteo.vit@dave.eu>");
|