1329 строки
32 KiB
C
1329 строки
32 KiB
C
/*
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* x86 SMP booting functions
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*
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* (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
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* (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
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*
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* Much of the core SMP work is based on previous work by Thomas Radke, to
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* whom a great many thanks are extended.
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*
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* Thanks to Intel for making available several different Pentium,
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* Pentium Pro and Pentium-II/Xeon MP machines.
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* Original development of Linux SMP code supported by Caldera.
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*
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* This code is released under the GNU General Public License version 2 or
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* later.
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*
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* Fixes
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* Felix Koop : NR_CPUS used properly
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* Jose Renau : Handle single CPU case.
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* Alan Cox : By repeated request 8) - Total BogoMIPS report.
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* Greg Wright : Fix for kernel stacks panic.
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* Erich Boleyn : MP v1.4 and additional changes.
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* Matthias Sattler : Changes for 2.1 kernel map.
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* Michel Lespinasse : Changes for 2.1 kernel map.
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* Michael Chastain : Change trampoline.S to gnu as.
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* Alan Cox : Dumb bug: 'B' step PPro's are fine
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* Ingo Molnar : Added APIC timers, based on code
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* from Jose Renau
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* Ingo Molnar : various cleanups and rewrites
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* Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
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* Maciej W. Rozycki : Bits for genuine 82489DX APICs
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* Martin J. Bligh : Added support for multi-quad systems
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* Dave Jones : Report invalid combinations of Athlon CPUs.
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* Rusty Russell : Hacked into shape for new "hotplug" boot process. */
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/kernel_stat.h>
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#include <linux/bootmem.h>
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#include <linux/notifier.h>
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#include <linux/cpu.h>
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#include <linux/percpu.h>
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#include <linux/nmi.h>
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#include <linux/delay.h>
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#include <linux/mc146818rtc.h>
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#include <asm/tlbflush.h>
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#include <asm/desc.h>
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#include <asm/arch_hooks.h>
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#include <asm/nmi.h>
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#include <mach_apic.h>
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#include <mach_wakecpu.h>
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#include <smpboot_hooks.h>
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#include <asm/vmi.h>
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#include <asm/mtrr.h>
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/* Set if we find a B stepping CPU */
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static int __devinitdata smp_b_stepping;
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/* Number of siblings per CPU package */
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int smp_num_siblings = 1;
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EXPORT_SYMBOL(smp_num_siblings);
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/* Last level cache ID of each logical CPU */
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int cpu_llc_id[NR_CPUS] __cpuinitdata = {[0 ... NR_CPUS-1] = BAD_APICID};
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/* representing HT siblings of each logical CPU */
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DEFINE_PER_CPU(cpumask_t, cpu_sibling_map);
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EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
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/* representing HT and core siblings of each logical CPU */
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DEFINE_PER_CPU(cpumask_t, cpu_core_map);
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EXPORT_PER_CPU_SYMBOL(cpu_core_map);
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/* bitmap of online cpus */
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cpumask_t cpu_online_map __read_mostly;
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EXPORT_SYMBOL(cpu_online_map);
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cpumask_t cpu_callin_map;
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cpumask_t cpu_callout_map;
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EXPORT_SYMBOL(cpu_callout_map);
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cpumask_t cpu_possible_map;
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EXPORT_SYMBOL(cpu_possible_map);
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static cpumask_t smp_commenced_mask;
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/* Per CPU bogomips and other parameters */
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struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
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EXPORT_SYMBOL(cpu_data);
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u8 x86_cpu_to_apicid[NR_CPUS] __read_mostly =
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{ [0 ... NR_CPUS-1] = 0xff };
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EXPORT_SYMBOL(x86_cpu_to_apicid);
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u8 apicid_2_node[MAX_APICID];
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/*
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* Trampoline 80x86 program as an array.
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*/
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extern unsigned char trampoline_data [];
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extern unsigned char trampoline_end [];
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static unsigned char *trampoline_base;
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static int trampoline_exec;
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static void map_cpu_to_logical_apicid(void);
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/* State of each CPU. */
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DEFINE_PER_CPU(int, cpu_state) = { 0 };
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/*
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* Currently trivial. Write the real->protected mode
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* bootstrap into the page concerned. The caller
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* has made sure it's suitably aligned.
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*/
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static unsigned long __cpuinit setup_trampoline(void)
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{
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memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data);
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return virt_to_phys(trampoline_base);
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}
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/*
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* We are called very early to get the low memory for the
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* SMP bootup trampoline page.
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*/
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void __init smp_alloc_memory(void)
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{
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trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE);
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/*
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* Has to be in very low memory so we can execute
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* real-mode AP code.
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*/
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if (__pa(trampoline_base) >= 0x9F000)
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BUG();
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/*
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* Make the SMP trampoline executable:
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*/
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trampoline_exec = set_kernel_exec((unsigned long)trampoline_base, 1);
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}
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/*
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* The bootstrap kernel entry code has set these up. Save them for
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* a given CPU
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*/
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void __cpuinit smp_store_cpu_info(int id)
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{
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struct cpuinfo_x86 *c = cpu_data + id;
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*c = boot_cpu_data;
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if (id!=0)
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identify_secondary_cpu(c);
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/*
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* Mask B, Pentium, but not Pentium MMX
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*/
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if (c->x86_vendor == X86_VENDOR_INTEL &&
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c->x86 == 5 &&
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c->x86_mask >= 1 && c->x86_mask <= 4 &&
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c->x86_model <= 3)
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/*
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* Remember we have B step Pentia with bugs
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*/
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smp_b_stepping = 1;
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/*
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* Certain Athlons might work (for various values of 'work') in SMP
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* but they are not certified as MP capable.
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*/
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if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
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if (num_possible_cpus() == 1)
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goto valid_k7;
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/* Athlon 660/661 is valid. */
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if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)))
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goto valid_k7;
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/* Duron 670 is valid */
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if ((c->x86_model==7) && (c->x86_mask==0))
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goto valid_k7;
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/*
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* Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
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* It's worth noting that the A5 stepping (662) of some Athlon XP's
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* have the MP bit set.
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* See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
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*/
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if (((c->x86_model==6) && (c->x86_mask>=2)) ||
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((c->x86_model==7) && (c->x86_mask>=1)) ||
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(c->x86_model> 7))
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if (cpu_has_mp)
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goto valid_k7;
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/* If we get here, it's not a certified SMP capable AMD system. */
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add_taint(TAINT_UNSAFE_SMP);
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}
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valid_k7:
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;
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}
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extern void calibrate_delay(void);
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static atomic_t init_deasserted;
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static void __cpuinit smp_callin(void)
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{
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int cpuid, phys_id;
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unsigned long timeout;
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/*
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* If waken up by an INIT in an 82489DX configuration
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* we may get here before an INIT-deassert IPI reaches
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* our local APIC. We have to wait for the IPI or we'll
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* lock up on an APIC access.
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*/
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wait_for_init_deassert(&init_deasserted);
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/*
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* (This works even if the APIC is not enabled.)
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*/
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phys_id = GET_APIC_ID(apic_read(APIC_ID));
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cpuid = smp_processor_id();
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if (cpu_isset(cpuid, cpu_callin_map)) {
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printk("huh, phys CPU#%d, CPU#%d already present??\n",
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phys_id, cpuid);
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BUG();
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}
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Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
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/*
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* STARTUP IPIs are fragile beasts as they might sometimes
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* trigger some glue motherboard logic. Complete APIC bus
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* silence for 1 second, this overestimates the time the
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* boot CPU is spending to send the up to 2 STARTUP IPIs
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* by a factor of two. This should be enough.
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*/
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/*
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* Waiting 2s total for startup (udelay is not yet working)
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*/
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timeout = jiffies + 2*HZ;
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while (time_before(jiffies, timeout)) {
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/*
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* Has the boot CPU finished it's STARTUP sequence?
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*/
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if (cpu_isset(cpuid, cpu_callout_map))
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break;
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rep_nop();
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}
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if (!time_before(jiffies, timeout)) {
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printk("BUG: CPU%d started up but did not get a callout!\n",
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cpuid);
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BUG();
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}
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/*
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* the boot CPU has finished the init stage and is spinning
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* on callin_map until we finish. We are free to set up this
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* CPU, first the APIC. (this is probably redundant on most
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* boards)
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*/
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Dprintk("CALLIN, before setup_local_APIC().\n");
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smp_callin_clear_local_apic();
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setup_local_APIC();
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map_cpu_to_logical_apicid();
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/*
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* Get our bogomips.
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*/
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calibrate_delay();
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Dprintk("Stack at about %p\n",&cpuid);
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/*
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* Save our processor parameters
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*/
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smp_store_cpu_info(cpuid);
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/*
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* Allow the master to continue.
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*/
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cpu_set(cpuid, cpu_callin_map);
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}
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static int cpucount;
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/* maps the cpu to the sched domain representing multi-core */
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cpumask_t cpu_coregroup_map(int cpu)
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{
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struct cpuinfo_x86 *c = cpu_data + cpu;
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/*
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* For perf, we return last level cache shared map.
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* And for power savings, we return cpu_core_map
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*/
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if (sched_mc_power_savings || sched_smt_power_savings)
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return per_cpu(cpu_core_map, cpu);
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else
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return c->llc_shared_map;
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}
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/* representing cpus for which sibling maps can be computed */
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static cpumask_t cpu_sibling_setup_map;
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void __cpuinit set_cpu_sibling_map(int cpu)
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{
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int i;
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struct cpuinfo_x86 *c = cpu_data;
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cpu_set(cpu, cpu_sibling_setup_map);
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if (smp_num_siblings > 1) {
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for_each_cpu_mask(i, cpu_sibling_setup_map) {
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if (c[cpu].phys_proc_id == c[i].phys_proc_id &&
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c[cpu].cpu_core_id == c[i].cpu_core_id) {
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cpu_set(i, per_cpu(cpu_sibling_map, cpu));
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cpu_set(cpu, per_cpu(cpu_sibling_map, i));
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cpu_set(i, per_cpu(cpu_core_map, cpu));
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cpu_set(cpu, per_cpu(cpu_core_map, i));
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cpu_set(i, c[cpu].llc_shared_map);
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cpu_set(cpu, c[i].llc_shared_map);
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}
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}
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} else {
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cpu_set(cpu, per_cpu(cpu_sibling_map, cpu));
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}
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cpu_set(cpu, c[cpu].llc_shared_map);
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if (current_cpu_data.x86_max_cores == 1) {
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per_cpu(cpu_core_map, cpu) = per_cpu(cpu_sibling_map, cpu);
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c[cpu].booted_cores = 1;
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return;
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}
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for_each_cpu_mask(i, cpu_sibling_setup_map) {
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if (cpu_llc_id[cpu] != BAD_APICID &&
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cpu_llc_id[cpu] == cpu_llc_id[i]) {
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cpu_set(i, c[cpu].llc_shared_map);
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cpu_set(cpu, c[i].llc_shared_map);
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}
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if (c[cpu].phys_proc_id == c[i].phys_proc_id) {
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cpu_set(i, per_cpu(cpu_core_map, cpu));
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cpu_set(cpu, per_cpu(cpu_core_map, i));
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/*
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* Does this new cpu bringup a new core?
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*/
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if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) {
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/*
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* for each core in package, increment
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* the booted_cores for this new cpu
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*/
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if (first_cpu(per_cpu(cpu_sibling_map, i)) == i)
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c[cpu].booted_cores++;
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/*
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* increment the core count for all
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* the other cpus in this package
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*/
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if (i != cpu)
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c[i].booted_cores++;
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} else if (i != cpu && !c[cpu].booted_cores)
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c[cpu].booted_cores = c[i].booted_cores;
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}
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}
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}
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/*
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* Activate a secondary processor.
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*/
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static void __cpuinit start_secondary(void *unused)
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{
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/*
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* Don't put *anything* before cpu_init(), SMP booting is too
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* fragile that we want to limit the things done here to the
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* most necessary things.
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*/
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#ifdef CONFIG_VMI
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vmi_bringup();
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#endif
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cpu_init();
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preempt_disable();
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smp_callin();
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while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
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rep_nop();
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/*
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* Check TSC synchronization with the BP:
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*/
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check_tsc_sync_target();
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setup_secondary_clock();
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if (nmi_watchdog == NMI_IO_APIC) {
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disable_8259A_irq(0);
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enable_NMI_through_LVT0(NULL);
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enable_8259A_irq(0);
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}
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/*
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* low-memory mappings have been cleared, flush them from
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* the local TLBs too.
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*/
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local_flush_tlb();
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/* This must be done before setting cpu_online_map */
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set_cpu_sibling_map(raw_smp_processor_id());
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wmb();
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/*
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* We need to hold call_lock, so there is no inconsistency
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* between the time smp_call_function() determines number of
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* IPI receipients, and the time when the determination is made
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* for which cpus receive the IPI. Holding this
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* lock helps us to not include this cpu in a currently in progress
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* smp_call_function().
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*/
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lock_ipi_call_lock();
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cpu_set(smp_processor_id(), cpu_online_map);
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unlock_ipi_call_lock();
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per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
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/* We can take interrupts now: we're officially "up". */
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local_irq_enable();
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wmb();
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cpu_idle();
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}
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/*
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* Everything has been set up for the secondary
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* CPUs - they just need to reload everything
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* from the task structure
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* This function must not return.
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*/
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void __devinit initialize_secondary(void)
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{
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/*
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* We don't actually need to load the full TSS,
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* basically just the stack pointer and the eip.
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*/
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asm volatile(
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"movl %0,%%esp\n\t"
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"jmp *%1"
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:
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:"m" (current->thread.esp),"m" (current->thread.eip));
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}
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/* Static state in head.S used to set up a CPU */
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extern struct {
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void * esp;
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unsigned short ss;
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} stack_start;
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#ifdef CONFIG_NUMA
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/* which logical CPUs are on which nodes */
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cpumask_t node_2_cpu_mask[MAX_NUMNODES] __read_mostly =
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{ [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE };
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EXPORT_SYMBOL(node_2_cpu_mask);
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/* which node each logical CPU is on */
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int cpu_2_node[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
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EXPORT_SYMBOL(cpu_2_node);
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/* set up a mapping between cpu and node. */
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static inline void map_cpu_to_node(int cpu, int node)
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{
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printk("Mapping cpu %d to node %d\n", cpu, node);
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cpu_set(cpu, node_2_cpu_mask[node]);
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cpu_2_node[cpu] = node;
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}
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/* undo a mapping between cpu and node. */
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static inline void unmap_cpu_to_node(int cpu)
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{
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int node;
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printk("Unmapping cpu %d from all nodes\n", cpu);
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for (node = 0; node < MAX_NUMNODES; node ++)
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cpu_clear(cpu, node_2_cpu_mask[node]);
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cpu_2_node[cpu] = 0;
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}
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#else /* !CONFIG_NUMA */
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#define map_cpu_to_node(cpu, node) ({})
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#define unmap_cpu_to_node(cpu) ({})
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#endif /* CONFIG_NUMA */
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u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID };
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static void map_cpu_to_logical_apicid(void)
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{
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int cpu = smp_processor_id();
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int apicid = logical_smp_processor_id();
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int node = apicid_to_node(apicid);
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if (!node_online(node))
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node = first_online_node;
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cpu_2_logical_apicid[cpu] = apicid;
|
|
map_cpu_to_node(cpu, node);
|
|
}
|
|
|
|
static void unmap_cpu_to_logical_apicid(int cpu)
|
|
{
|
|
cpu_2_logical_apicid[cpu] = BAD_APICID;
|
|
unmap_cpu_to_node(cpu);
|
|
}
|
|
|
|
static inline void __inquire_remote_apic(int apicid)
|
|
{
|
|
int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
|
|
char *names[] = { "ID", "VERSION", "SPIV" };
|
|
int timeout;
|
|
unsigned long status;
|
|
|
|
printk("Inquiring remote APIC #%d...\n", apicid);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(regs); i++) {
|
|
printk("... APIC #%d %s: ", apicid, names[i]);
|
|
|
|
/*
|
|
* Wait for idle.
|
|
*/
|
|
status = safe_apic_wait_icr_idle();
|
|
if (status)
|
|
printk("a previous APIC delivery may have failed\n");
|
|
|
|
apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
|
|
apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
|
|
|
|
timeout = 0;
|
|
do {
|
|
udelay(100);
|
|
status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
|
|
} while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
|
|
|
|
switch (status) {
|
|
case APIC_ICR_RR_VALID:
|
|
status = apic_read(APIC_RRR);
|
|
printk("%lx\n", status);
|
|
break;
|
|
default:
|
|
printk("failed\n");
|
|
}
|
|
}
|
|
}
|
|
|
|
#ifdef WAKE_SECONDARY_VIA_NMI
|
|
/*
|
|
* Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
|
|
* INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
|
|
* won't ... remember to clear down the APIC, etc later.
|
|
*/
|
|
static int __devinit
|
|
wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
|
|
{
|
|
unsigned long send_status, accept_status = 0;
|
|
int maxlvt;
|
|
|
|
/* Target chip */
|
|
apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid));
|
|
|
|
/* Boot on the stack */
|
|
/* Kick the second */
|
|
apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
|
|
|
|
Dprintk("Waiting for send to finish...\n");
|
|
send_status = safe_apic_wait_icr_idle();
|
|
|
|
/*
|
|
* Give the other CPU some time to accept the IPI.
|
|
*/
|
|
udelay(200);
|
|
/*
|
|
* Due to the Pentium erratum 3AP.
|
|
*/
|
|
maxlvt = lapic_get_maxlvt();
|
|
if (maxlvt > 3) {
|
|
apic_read_around(APIC_SPIV);
|
|
apic_write(APIC_ESR, 0);
|
|
}
|
|
accept_status = (apic_read(APIC_ESR) & 0xEF);
|
|
Dprintk("NMI sent.\n");
|
|
|
|
if (send_status)
|
|
printk("APIC never delivered???\n");
|
|
if (accept_status)
|
|
printk("APIC delivery error (%lx).\n", accept_status);
|
|
|
|
return (send_status | accept_status);
|
|
}
|
|
#endif /* WAKE_SECONDARY_VIA_NMI */
|
|
|
|
#ifdef WAKE_SECONDARY_VIA_INIT
|
|
static int __devinit
|
|
wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
|
|
{
|
|
unsigned long send_status, accept_status = 0;
|
|
int maxlvt, num_starts, j;
|
|
|
|
/*
|
|
* Be paranoid about clearing APIC errors.
|
|
*/
|
|
if (APIC_INTEGRATED(apic_version[phys_apicid])) {
|
|
apic_read_around(APIC_SPIV);
|
|
apic_write(APIC_ESR, 0);
|
|
apic_read(APIC_ESR);
|
|
}
|
|
|
|
Dprintk("Asserting INIT.\n");
|
|
|
|
/*
|
|
* Turn INIT on target chip
|
|
*/
|
|
apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
|
|
|
|
/*
|
|
* Send IPI
|
|
*/
|
|
apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
|
|
| APIC_DM_INIT);
|
|
|
|
Dprintk("Waiting for send to finish...\n");
|
|
send_status = safe_apic_wait_icr_idle();
|
|
|
|
mdelay(10);
|
|
|
|
Dprintk("Deasserting INIT.\n");
|
|
|
|
/* Target chip */
|
|
apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
|
|
|
|
/* Send IPI */
|
|
apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
|
|
|
|
Dprintk("Waiting for send to finish...\n");
|
|
send_status = safe_apic_wait_icr_idle();
|
|
|
|
atomic_set(&init_deasserted, 1);
|
|
|
|
/*
|
|
* Should we send STARTUP IPIs ?
|
|
*
|
|
* Determine this based on the APIC version.
|
|
* If we don't have an integrated APIC, don't send the STARTUP IPIs.
|
|
*/
|
|
if (APIC_INTEGRATED(apic_version[phys_apicid]))
|
|
num_starts = 2;
|
|
else
|
|
num_starts = 0;
|
|
|
|
/*
|
|
* Paravirt / VMI wants a startup IPI hook here to set up the
|
|
* target processor state.
|
|
*/
|
|
startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
|
|
(unsigned long) stack_start.esp);
|
|
|
|
/*
|
|
* Run STARTUP IPI loop.
|
|
*/
|
|
Dprintk("#startup loops: %d.\n", num_starts);
|
|
|
|
maxlvt = lapic_get_maxlvt();
|
|
|
|
for (j = 1; j <= num_starts; j++) {
|
|
Dprintk("Sending STARTUP #%d.\n",j);
|
|
apic_read_around(APIC_SPIV);
|
|
apic_write(APIC_ESR, 0);
|
|
apic_read(APIC_ESR);
|
|
Dprintk("After apic_write.\n");
|
|
|
|
/*
|
|
* STARTUP IPI
|
|
*/
|
|
|
|
/* Target chip */
|
|
apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
|
|
|
|
/* Boot on the stack */
|
|
/* Kick the second */
|
|
apic_write_around(APIC_ICR, APIC_DM_STARTUP
|
|
| (start_eip >> 12));
|
|
|
|
/*
|
|
* Give the other CPU some time to accept the IPI.
|
|
*/
|
|
udelay(300);
|
|
|
|
Dprintk("Startup point 1.\n");
|
|
|
|
Dprintk("Waiting for send to finish...\n");
|
|
send_status = safe_apic_wait_icr_idle();
|
|
|
|
/*
|
|
* Give the other CPU some time to accept the IPI.
|
|
*/
|
|
udelay(200);
|
|
/*
|
|
* Due to the Pentium erratum 3AP.
|
|
*/
|
|
if (maxlvt > 3) {
|
|
apic_read_around(APIC_SPIV);
|
|
apic_write(APIC_ESR, 0);
|
|
}
|
|
accept_status = (apic_read(APIC_ESR) & 0xEF);
|
|
if (send_status || accept_status)
|
|
break;
|
|
}
|
|
Dprintk("After Startup.\n");
|
|
|
|
if (send_status)
|
|
printk("APIC never delivered???\n");
|
|
if (accept_status)
|
|
printk("APIC delivery error (%lx).\n", accept_status);
|
|
|
|
return (send_status | accept_status);
|
|
}
|
|
#endif /* WAKE_SECONDARY_VIA_INIT */
|
|
|
|
extern cpumask_t cpu_initialized;
|
|
static inline int alloc_cpu_id(void)
|
|
{
|
|
cpumask_t tmp_map;
|
|
int cpu;
|
|
cpus_complement(tmp_map, cpu_present_map);
|
|
cpu = first_cpu(tmp_map);
|
|
if (cpu >= NR_CPUS)
|
|
return -ENODEV;
|
|
return cpu;
|
|
}
|
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
static struct task_struct * __devinitdata cpu_idle_tasks[NR_CPUS];
|
|
static inline struct task_struct * alloc_idle_task(int cpu)
|
|
{
|
|
struct task_struct *idle;
|
|
|
|
if ((idle = cpu_idle_tasks[cpu]) != NULL) {
|
|
/* initialize thread_struct. we really want to avoid destroy
|
|
* idle tread
|
|
*/
|
|
idle->thread.esp = (unsigned long)task_pt_regs(idle);
|
|
init_idle(idle, cpu);
|
|
return idle;
|
|
}
|
|
idle = fork_idle(cpu);
|
|
|
|
if (!IS_ERR(idle))
|
|
cpu_idle_tasks[cpu] = idle;
|
|
return idle;
|
|
}
|
|
#else
|
|
#define alloc_idle_task(cpu) fork_idle(cpu)
|
|
#endif
|
|
|
|
static int __cpuinit do_boot_cpu(int apicid, int cpu)
|
|
/*
|
|
* NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
|
|
* (ie clustered apic addressing mode), this is a LOGICAL apic ID.
|
|
* Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
|
|
*/
|
|
{
|
|
struct task_struct *idle;
|
|
unsigned long boot_error;
|
|
int timeout;
|
|
unsigned long start_eip;
|
|
unsigned short nmi_high = 0, nmi_low = 0;
|
|
|
|
/*
|
|
* Save current MTRR state in case it was changed since early boot
|
|
* (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
|
|
*/
|
|
mtrr_save_state();
|
|
|
|
/*
|
|
* We can't use kernel_thread since we must avoid to
|
|
* reschedule the child.
|
|
*/
|
|
idle = alloc_idle_task(cpu);
|
|
if (IS_ERR(idle))
|
|
panic("failed fork for CPU %d", cpu);
|
|
|
|
init_gdt(cpu);
|
|
per_cpu(current_task, cpu) = idle;
|
|
early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
|
|
|
|
idle->thread.eip = (unsigned long) start_secondary;
|
|
/* start_eip had better be page-aligned! */
|
|
start_eip = setup_trampoline();
|
|
|
|
++cpucount;
|
|
alternatives_smp_switch(1);
|
|
|
|
/* So we see what's up */
|
|
printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip);
|
|
/* Stack for startup_32 can be just as for start_secondary onwards */
|
|
stack_start.esp = (void *) idle->thread.esp;
|
|
|
|
irq_ctx_init(cpu);
|
|
|
|
x86_cpu_to_apicid[cpu] = apicid;
|
|
/*
|
|
* This grunge runs the startup process for
|
|
* the targeted processor.
|
|
*/
|
|
|
|
atomic_set(&init_deasserted, 0);
|
|
|
|
Dprintk("Setting warm reset code and vector.\n");
|
|
|
|
store_NMI_vector(&nmi_high, &nmi_low);
|
|
|
|
smpboot_setup_warm_reset_vector(start_eip);
|
|
|
|
/*
|
|
* Starting actual IPI sequence...
|
|
*/
|
|
boot_error = wakeup_secondary_cpu(apicid, start_eip);
|
|
|
|
if (!boot_error) {
|
|
/*
|
|
* allow APs to start initializing.
|
|
*/
|
|
Dprintk("Before Callout %d.\n", cpu);
|
|
cpu_set(cpu, cpu_callout_map);
|
|
Dprintk("After Callout %d.\n", cpu);
|
|
|
|
/*
|
|
* Wait 5s total for a response
|
|
*/
|
|
for (timeout = 0; timeout < 50000; timeout++) {
|
|
if (cpu_isset(cpu, cpu_callin_map))
|
|
break; /* It has booted */
|
|
udelay(100);
|
|
}
|
|
|
|
if (cpu_isset(cpu, cpu_callin_map)) {
|
|
/* number CPUs logically, starting from 1 (BSP is 0) */
|
|
Dprintk("OK.\n");
|
|
printk("CPU%d: ", cpu);
|
|
print_cpu_info(&cpu_data[cpu]);
|
|
Dprintk("CPU has booted.\n");
|
|
} else {
|
|
boot_error= 1;
|
|
if (*((volatile unsigned char *)trampoline_base)
|
|
== 0xA5)
|
|
/* trampoline started but...? */
|
|
printk("Stuck ??\n");
|
|
else
|
|
/* trampoline code not run */
|
|
printk("Not responding.\n");
|
|
inquire_remote_apic(apicid);
|
|
}
|
|
}
|
|
|
|
if (boot_error) {
|
|
/* Try to put things back the way they were before ... */
|
|
unmap_cpu_to_logical_apicid(cpu);
|
|
cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
|
|
cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
|
|
cpucount--;
|
|
} else {
|
|
x86_cpu_to_apicid[cpu] = apicid;
|
|
cpu_set(cpu, cpu_present_map);
|
|
}
|
|
|
|
/* mark "stuck" area as not stuck */
|
|
*((volatile unsigned long *)trampoline_base) = 0;
|
|
|
|
return boot_error;
|
|
}
|
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
void cpu_exit_clear(void)
|
|
{
|
|
int cpu = raw_smp_processor_id();
|
|
|
|
idle_task_exit();
|
|
|
|
cpucount --;
|
|
cpu_uninit();
|
|
irq_ctx_exit(cpu);
|
|
|
|
cpu_clear(cpu, cpu_callout_map);
|
|
cpu_clear(cpu, cpu_callin_map);
|
|
|
|
cpu_clear(cpu, smp_commenced_mask);
|
|
unmap_cpu_to_logical_apicid(cpu);
|
|
}
|
|
|
|
struct warm_boot_cpu_info {
|
|
struct completion *complete;
|
|
struct work_struct task;
|
|
int apicid;
|
|
int cpu;
|
|
};
|
|
|
|
static void __cpuinit do_warm_boot_cpu(struct work_struct *work)
|
|
{
|
|
struct warm_boot_cpu_info *info =
|
|
container_of(work, struct warm_boot_cpu_info, task);
|
|
do_boot_cpu(info->apicid, info->cpu);
|
|
complete(info->complete);
|
|
}
|
|
|
|
static int __cpuinit __smp_prepare_cpu(int cpu)
|
|
{
|
|
DECLARE_COMPLETION_ONSTACK(done);
|
|
struct warm_boot_cpu_info info;
|
|
int apicid, ret;
|
|
|
|
apicid = x86_cpu_to_apicid[cpu];
|
|
if (apicid == BAD_APICID) {
|
|
ret = -ENODEV;
|
|
goto exit;
|
|
}
|
|
|
|
info.complete = &done;
|
|
info.apicid = apicid;
|
|
info.cpu = cpu;
|
|
INIT_WORK(&info.task, do_warm_boot_cpu);
|
|
|
|
/* init low mem mapping */
|
|
clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS,
|
|
min_t(unsigned long, KERNEL_PGD_PTRS, USER_PGD_PTRS));
|
|
flush_tlb_all();
|
|
schedule_work(&info.task);
|
|
wait_for_completion(&done);
|
|
|
|
zap_low_mappings();
|
|
ret = 0;
|
|
exit:
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Cycle through the processors sending APIC IPIs to boot each.
|
|
*/
|
|
|
|
static int boot_cpu_logical_apicid;
|
|
/* Where the IO area was mapped on multiquad, always 0 otherwise */
|
|
void *xquad_portio;
|
|
#ifdef CONFIG_X86_NUMAQ
|
|
EXPORT_SYMBOL(xquad_portio);
|
|
#endif
|
|
|
|
static void __init smp_boot_cpus(unsigned int max_cpus)
|
|
{
|
|
int apicid, cpu, bit, kicked;
|
|
unsigned long bogosum = 0;
|
|
|
|
/*
|
|
* Setup boot CPU information
|
|
*/
|
|
smp_store_cpu_info(0); /* Final full version of the data */
|
|
printk("CPU%d: ", 0);
|
|
print_cpu_info(&cpu_data[0]);
|
|
|
|
boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
|
|
boot_cpu_logical_apicid = logical_smp_processor_id();
|
|
x86_cpu_to_apicid[0] = boot_cpu_physical_apicid;
|
|
|
|
current_thread_info()->cpu = 0;
|
|
|
|
set_cpu_sibling_map(0);
|
|
|
|
/*
|
|
* If we couldn't find an SMP configuration at boot time,
|
|
* get out of here now!
|
|
*/
|
|
if (!smp_found_config && !acpi_lapic) {
|
|
printk(KERN_NOTICE "SMP motherboard not detected.\n");
|
|
smpboot_clear_io_apic_irqs();
|
|
phys_cpu_present_map = physid_mask_of_physid(0);
|
|
if (APIC_init_uniprocessor())
|
|
printk(KERN_NOTICE "Local APIC not detected."
|
|
" Using dummy APIC emulation.\n");
|
|
map_cpu_to_logical_apicid();
|
|
cpu_set(0, per_cpu(cpu_sibling_map, 0));
|
|
cpu_set(0, per_cpu(cpu_core_map, 0));
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Should not be necessary because the MP table should list the boot
|
|
* CPU too, but we do it for the sake of robustness anyway.
|
|
* Makes no sense to do this check in clustered apic mode, so skip it
|
|
*/
|
|
if (!check_phys_apicid_present(boot_cpu_physical_apicid)) {
|
|
printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
|
|
boot_cpu_physical_apicid);
|
|
physid_set(hard_smp_processor_id(), phys_cpu_present_map);
|
|
}
|
|
|
|
/*
|
|
* If we couldn't find a local APIC, then get out of here now!
|
|
*/
|
|
if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) {
|
|
printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
|
|
boot_cpu_physical_apicid);
|
|
printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
|
|
smpboot_clear_io_apic_irqs();
|
|
phys_cpu_present_map = physid_mask_of_physid(0);
|
|
cpu_set(0, per_cpu(cpu_sibling_map, 0));
|
|
cpu_set(0, per_cpu(cpu_core_map, 0));
|
|
return;
|
|
}
|
|
|
|
verify_local_APIC();
|
|
|
|
/*
|
|
* If SMP should be disabled, then really disable it!
|
|
*/
|
|
if (!max_cpus) {
|
|
smp_found_config = 0;
|
|
printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
|
|
|
|
if (nmi_watchdog == NMI_LOCAL_APIC) {
|
|
printk(KERN_INFO "activating minimal APIC for NMI watchdog use.\n");
|
|
connect_bsp_APIC();
|
|
setup_local_APIC();
|
|
}
|
|
smpboot_clear_io_apic_irqs();
|
|
phys_cpu_present_map = physid_mask_of_physid(0);
|
|
cpu_set(0, per_cpu(cpu_sibling_map, 0));
|
|
cpu_set(0, per_cpu(cpu_core_map, 0));
|
|
return;
|
|
}
|
|
|
|
connect_bsp_APIC();
|
|
setup_local_APIC();
|
|
map_cpu_to_logical_apicid();
|
|
|
|
|
|
setup_portio_remap();
|
|
|
|
/*
|
|
* Scan the CPU present map and fire up the other CPUs via do_boot_cpu
|
|
*
|
|
* In clustered apic mode, phys_cpu_present_map is a constructed thus:
|
|
* bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
|
|
* clustered apic ID.
|
|
*/
|
|
Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
|
|
|
|
kicked = 1;
|
|
for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) {
|
|
apicid = cpu_present_to_apicid(bit);
|
|
/*
|
|
* Don't even attempt to start the boot CPU!
|
|
*/
|
|
if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID))
|
|
continue;
|
|
|
|
if (!check_apicid_present(bit))
|
|
continue;
|
|
if (max_cpus <= cpucount+1)
|
|
continue;
|
|
|
|
if (((cpu = alloc_cpu_id()) <= 0) || do_boot_cpu(apicid, cpu))
|
|
printk("CPU #%d not responding - cannot use it.\n",
|
|
apicid);
|
|
else
|
|
++kicked;
|
|
}
|
|
|
|
/*
|
|
* Cleanup possible dangling ends...
|
|
*/
|
|
smpboot_restore_warm_reset_vector();
|
|
|
|
/*
|
|
* Allow the user to impress friends.
|
|
*/
|
|
Dprintk("Before bogomips.\n");
|
|
for (cpu = 0; cpu < NR_CPUS; cpu++)
|
|
if (cpu_isset(cpu, cpu_callout_map))
|
|
bogosum += cpu_data[cpu].loops_per_jiffy;
|
|
printk(KERN_INFO
|
|
"Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
|
|
cpucount+1,
|
|
bogosum/(500000/HZ),
|
|
(bogosum/(5000/HZ))%100);
|
|
|
|
Dprintk("Before bogocount - setting activated=1.\n");
|
|
|
|
if (smp_b_stepping)
|
|
printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n");
|
|
|
|
/*
|
|
* Don't taint if we are running SMP kernel on a single non-MP
|
|
* approved Athlon
|
|
*/
|
|
if (tainted & TAINT_UNSAFE_SMP) {
|
|
if (cpucount)
|
|
printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n");
|
|
else
|
|
tainted &= ~TAINT_UNSAFE_SMP;
|
|
}
|
|
|
|
Dprintk("Boot done.\n");
|
|
|
|
/*
|
|
* construct cpu_sibling_map, so that we can tell sibling CPUs
|
|
* efficiently.
|
|
*/
|
|
for (cpu = 0; cpu < NR_CPUS; cpu++) {
|
|
cpus_clear(per_cpu(cpu_sibling_map, cpu));
|
|
cpus_clear(per_cpu(cpu_core_map, cpu));
|
|
}
|
|
|
|
cpu_set(0, per_cpu(cpu_sibling_map, 0));
|
|
cpu_set(0, per_cpu(cpu_core_map, 0));
|
|
|
|
smpboot_setup_io_apic();
|
|
|
|
setup_boot_clock();
|
|
}
|
|
|
|
/* These are wrappers to interface to the new boot process. Someone
|
|
who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
|
|
void __init native_smp_prepare_cpus(unsigned int max_cpus)
|
|
{
|
|
smp_commenced_mask = cpumask_of_cpu(0);
|
|
cpu_callin_map = cpumask_of_cpu(0);
|
|
mb();
|
|
smp_boot_cpus(max_cpus);
|
|
}
|
|
|
|
void __init native_smp_prepare_boot_cpu(void)
|
|
{
|
|
unsigned int cpu = smp_processor_id();
|
|
|
|
init_gdt(cpu);
|
|
switch_to_new_gdt();
|
|
|
|
cpu_set(cpu, cpu_online_map);
|
|
cpu_set(cpu, cpu_callout_map);
|
|
cpu_set(cpu, cpu_present_map);
|
|
cpu_set(cpu, cpu_possible_map);
|
|
__get_cpu_var(cpu_state) = CPU_ONLINE;
|
|
}
|
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
void remove_siblinginfo(int cpu)
|
|
{
|
|
int sibling;
|
|
struct cpuinfo_x86 *c = cpu_data;
|
|
|
|
for_each_cpu_mask(sibling, per_cpu(cpu_core_map, cpu)) {
|
|
cpu_clear(cpu, per_cpu(cpu_core_map, sibling));
|
|
/*/
|
|
* last thread sibling in this cpu core going down
|
|
*/
|
|
if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1)
|
|
c[sibling].booted_cores--;
|
|
}
|
|
|
|
for_each_cpu_mask(sibling, per_cpu(cpu_sibling_map, cpu))
|
|
cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling));
|
|
cpus_clear(per_cpu(cpu_sibling_map, cpu));
|
|
cpus_clear(per_cpu(cpu_core_map, cpu));
|
|
c[cpu].phys_proc_id = 0;
|
|
c[cpu].cpu_core_id = 0;
|
|
cpu_clear(cpu, cpu_sibling_setup_map);
|
|
}
|
|
|
|
int __cpu_disable(void)
|
|
{
|
|
cpumask_t map = cpu_online_map;
|
|
int cpu = smp_processor_id();
|
|
|
|
/*
|
|
* Perhaps use cpufreq to drop frequency, but that could go
|
|
* into generic code.
|
|
*
|
|
* We won't take down the boot processor on i386 due to some
|
|
* interrupts only being able to be serviced by the BSP.
|
|
* Especially so if we're not using an IOAPIC -zwane
|
|
*/
|
|
if (cpu == 0)
|
|
return -EBUSY;
|
|
if (nmi_watchdog == NMI_LOCAL_APIC)
|
|
stop_apic_nmi_watchdog(NULL);
|
|
clear_local_APIC();
|
|
/* Allow any queued timer interrupts to get serviced */
|
|
local_irq_enable();
|
|
mdelay(1);
|
|
local_irq_disable();
|
|
|
|
remove_siblinginfo(cpu);
|
|
|
|
cpu_clear(cpu, map);
|
|
fixup_irqs(map);
|
|
/* It's now safe to remove this processor from the online map */
|
|
cpu_clear(cpu, cpu_online_map);
|
|
return 0;
|
|
}
|
|
|
|
void __cpu_die(unsigned int cpu)
|
|
{
|
|
/* We don't do anything here: idle task is faking death itself. */
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < 10; i++) {
|
|
/* They ack this in play_dead by setting CPU_DEAD */
|
|
if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
|
|
printk ("CPU %d is now offline\n", cpu);
|
|
if (1 == num_online_cpus())
|
|
alternatives_smp_switch(0);
|
|
return;
|
|
}
|
|
msleep(100);
|
|
}
|
|
printk(KERN_ERR "CPU %u didn't die...\n", cpu);
|
|
}
|
|
#else /* ... !CONFIG_HOTPLUG_CPU */
|
|
int __cpu_disable(void)
|
|
{
|
|
return -ENOSYS;
|
|
}
|
|
|
|
void __cpu_die(unsigned int cpu)
|
|
{
|
|
/* We said "no" in __cpu_disable */
|
|
BUG();
|
|
}
|
|
#endif /* CONFIG_HOTPLUG_CPU */
|
|
|
|
int __cpuinit native_cpu_up(unsigned int cpu)
|
|
{
|
|
unsigned long flags;
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
int ret = 0;
|
|
|
|
/*
|
|
* We do warm boot only on cpus that had booted earlier
|
|
* Otherwise cold boot is all handled from smp_boot_cpus().
|
|
* cpu_callin_map is set during AP kickstart process. Its reset
|
|
* when a cpu is taken offline from cpu_exit_clear().
|
|
*/
|
|
if (!cpu_isset(cpu, cpu_callin_map))
|
|
ret = __smp_prepare_cpu(cpu);
|
|
|
|
if (ret)
|
|
return -EIO;
|
|
#endif
|
|
|
|
/* In case one didn't come up */
|
|
if (!cpu_isset(cpu, cpu_callin_map)) {
|
|
printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu);
|
|
return -EIO;
|
|
}
|
|
|
|
per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
|
|
/* Unleash the CPU! */
|
|
cpu_set(cpu, smp_commenced_mask);
|
|
|
|
/*
|
|
* Check TSC synchronization with the AP (keep irqs disabled
|
|
* while doing so):
|
|
*/
|
|
local_irq_save(flags);
|
|
check_tsc_sync_source(cpu);
|
|
local_irq_restore(flags);
|
|
|
|
while (!cpu_isset(cpu, cpu_online_map)) {
|
|
cpu_relax();
|
|
touch_nmi_watchdog();
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void __init native_smp_cpus_done(unsigned int max_cpus)
|
|
{
|
|
#ifdef CONFIG_X86_IO_APIC
|
|
setup_ioapic_dest();
|
|
#endif
|
|
zap_low_mappings();
|
|
#ifndef CONFIG_HOTPLUG_CPU
|
|
/*
|
|
* Disable executability of the SMP trampoline:
|
|
*/
|
|
set_kernel_exec((unsigned long)trampoline_base, trampoline_exec);
|
|
#endif
|
|
}
|
|
|
|
void __init smp_intr_init(void)
|
|
{
|
|
/*
|
|
* IRQ0 must be given a fixed assignment and initialized,
|
|
* because it's used before the IO-APIC is set up.
|
|
*/
|
|
set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
|
|
|
|
/*
|
|
* The reschedule interrupt is a CPU-to-CPU reschedule-helper
|
|
* IPI, driven by wakeup.
|
|
*/
|
|
set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
|
|
|
|
/* IPI for invalidation */
|
|
set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
|
|
|
|
/* IPI for generic function call */
|
|
set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
|
|
}
|
|
|
|
/*
|
|
* If the BIOS enumerates physical processors before logical,
|
|
* maxcpus=N at enumeration-time can be used to disable HT.
|
|
*/
|
|
static int __init parse_maxcpus(char *arg)
|
|
{
|
|
extern unsigned int maxcpus;
|
|
|
|
maxcpus = simple_strtoul(arg, NULL, 0);
|
|
return 0;
|
|
}
|
|
early_param("maxcpus", parse_maxcpus);
|