340 строки
8.0 KiB
C
340 строки
8.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Universal Flash Storage Host controller PCI glue driver
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*
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* This code is based on drivers/scsi/ufs/ufshcd-pci.c
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* Copyright (C) 2011-2013 Samsung India Software Operations
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*
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* Authors:
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* Santosh Yaraganavi <santosh.sy@samsung.com>
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* Vinayak Holikatti <h.vinayak@samsung.com>
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*/
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#include "ufshcd.h"
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#include <linux/pci.h>
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#include <linux/pm_runtime.h>
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#include <linux/pm_qos.h>
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#include <linux/debugfs.h>
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struct intel_host {
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u32 active_ltr;
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u32 idle_ltr;
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struct dentry *debugfs_root;
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};
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static int ufs_intel_disable_lcc(struct ufs_hba *hba)
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{
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u32 attr = UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE);
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u32 lcc_enable = 0;
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ufshcd_dme_get(hba, attr, &lcc_enable);
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if (lcc_enable)
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ufshcd_disable_host_tx_lcc(hba);
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return 0;
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}
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static int ufs_intel_link_startup_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status status)
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{
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int err = 0;
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switch (status) {
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case PRE_CHANGE:
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err = ufs_intel_disable_lcc(hba);
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break;
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case POST_CHANGE:
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break;
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default:
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break;
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}
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return err;
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}
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#define INTEL_ACTIVELTR 0x804
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#define INTEL_IDLELTR 0x808
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#define INTEL_LTR_REQ BIT(15)
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#define INTEL_LTR_SCALE_MASK GENMASK(11, 10)
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#define INTEL_LTR_SCALE_1US (2 << 10)
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#define INTEL_LTR_SCALE_32US (3 << 10)
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#define INTEL_LTR_VALUE_MASK GENMASK(9, 0)
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static void intel_cache_ltr(struct ufs_hba *hba)
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{
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struct intel_host *host = ufshcd_get_variant(hba);
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host->active_ltr = readl(hba->mmio_base + INTEL_ACTIVELTR);
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host->idle_ltr = readl(hba->mmio_base + INTEL_IDLELTR);
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}
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static void intel_ltr_set(struct device *dev, s32 val)
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{
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struct ufs_hba *hba = dev_get_drvdata(dev);
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struct intel_host *host = ufshcd_get_variant(hba);
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u32 ltr;
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pm_runtime_get_sync(dev);
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/*
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* Program latency tolerance (LTR) accordingly what has been asked
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* by the PM QoS layer or disable it in case we were passed
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* negative value or PM_QOS_LATENCY_ANY.
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*/
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ltr = readl(hba->mmio_base + INTEL_ACTIVELTR);
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if (val == PM_QOS_LATENCY_ANY || val < 0) {
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ltr &= ~INTEL_LTR_REQ;
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} else {
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ltr |= INTEL_LTR_REQ;
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ltr &= ~INTEL_LTR_SCALE_MASK;
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ltr &= ~INTEL_LTR_VALUE_MASK;
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if (val > INTEL_LTR_VALUE_MASK) {
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val >>= 5;
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if (val > INTEL_LTR_VALUE_MASK)
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val = INTEL_LTR_VALUE_MASK;
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ltr |= INTEL_LTR_SCALE_32US | val;
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} else {
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ltr |= INTEL_LTR_SCALE_1US | val;
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}
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}
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if (ltr == host->active_ltr)
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goto out;
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writel(ltr, hba->mmio_base + INTEL_ACTIVELTR);
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writel(ltr, hba->mmio_base + INTEL_IDLELTR);
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/* Cache the values into intel_host structure */
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intel_cache_ltr(hba);
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out:
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pm_runtime_put(dev);
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}
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static void intel_ltr_expose(struct device *dev)
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{
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dev->power.set_latency_tolerance = intel_ltr_set;
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dev_pm_qos_expose_latency_tolerance(dev);
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}
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static void intel_ltr_hide(struct device *dev)
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{
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dev_pm_qos_hide_latency_tolerance(dev);
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dev->power.set_latency_tolerance = NULL;
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}
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static void intel_add_debugfs(struct ufs_hba *hba)
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{
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struct dentry *dir = debugfs_create_dir(dev_name(hba->dev), NULL);
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struct intel_host *host = ufshcd_get_variant(hba);
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intel_cache_ltr(hba);
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host->debugfs_root = dir;
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debugfs_create_x32("active_ltr", 0444, dir, &host->active_ltr);
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debugfs_create_x32("idle_ltr", 0444, dir, &host->idle_ltr);
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}
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static void intel_remove_debugfs(struct ufs_hba *hba)
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{
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struct intel_host *host = ufshcd_get_variant(hba);
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debugfs_remove_recursive(host->debugfs_root);
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}
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static int ufs_intel_common_init(struct ufs_hba *hba)
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{
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struct intel_host *host;
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host = devm_kzalloc(hba->dev, sizeof(*host), GFP_KERNEL);
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if (!host)
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return -ENOMEM;
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ufshcd_set_variant(hba, host);
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intel_ltr_expose(hba->dev);
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intel_add_debugfs(hba);
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return 0;
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}
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static void ufs_intel_common_exit(struct ufs_hba *hba)
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{
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intel_remove_debugfs(hba);
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intel_ltr_hide(hba->dev);
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}
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static int ufs_intel_ehl_init(struct ufs_hba *hba)
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{
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hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8;
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return ufs_intel_common_init(hba);
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}
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static struct ufs_hba_variant_ops ufs_intel_cnl_hba_vops = {
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.name = "intel-pci",
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.init = ufs_intel_common_init,
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.exit = ufs_intel_common_exit,
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.link_startup_notify = ufs_intel_link_startup_notify,
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};
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static struct ufs_hba_variant_ops ufs_intel_ehl_hba_vops = {
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.name = "intel-pci",
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.init = ufs_intel_ehl_init,
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.exit = ufs_intel_common_exit,
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.link_startup_notify = ufs_intel_link_startup_notify,
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};
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#ifdef CONFIG_PM_SLEEP
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/**
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* ufshcd_pci_suspend - suspend power management function
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* @dev: pointer to PCI device handle
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*
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* Returns 0 if successful
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* Returns non-zero otherwise
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*/
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static int ufshcd_pci_suspend(struct device *dev)
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{
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return ufshcd_system_suspend(dev_get_drvdata(dev));
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}
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/**
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* ufshcd_pci_resume - resume power management function
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* @dev: pointer to PCI device handle
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*
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* Returns 0 if successful
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* Returns non-zero otherwise
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*/
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static int ufshcd_pci_resume(struct device *dev)
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{
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return ufshcd_system_resume(dev_get_drvdata(dev));
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}
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#endif /* !CONFIG_PM_SLEEP */
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#ifdef CONFIG_PM
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static int ufshcd_pci_runtime_suspend(struct device *dev)
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{
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return ufshcd_runtime_suspend(dev_get_drvdata(dev));
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}
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static int ufshcd_pci_runtime_resume(struct device *dev)
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{
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return ufshcd_runtime_resume(dev_get_drvdata(dev));
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}
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static int ufshcd_pci_runtime_idle(struct device *dev)
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{
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return ufshcd_runtime_idle(dev_get_drvdata(dev));
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}
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#endif /* !CONFIG_PM */
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/**
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* ufshcd_pci_shutdown - main function to put the controller in reset state
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* @pdev: pointer to PCI device handle
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*/
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static void ufshcd_pci_shutdown(struct pci_dev *pdev)
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{
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ufshcd_shutdown((struct ufs_hba *)pci_get_drvdata(pdev));
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}
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/**
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* ufshcd_pci_remove - de-allocate PCI/SCSI host and host memory space
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* data structure memory
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* @pdev: pointer to PCI handle
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*/
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static void ufshcd_pci_remove(struct pci_dev *pdev)
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{
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struct ufs_hba *hba = pci_get_drvdata(pdev);
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pm_runtime_forbid(&pdev->dev);
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pm_runtime_get_noresume(&pdev->dev);
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ufshcd_remove(hba);
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ufshcd_dealloc_host(hba);
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}
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/**
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* ufshcd_pci_probe - probe routine of the driver
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* @pdev: pointer to PCI device handle
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* @id: PCI device id
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*
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* Returns 0 on success, non-zero value on failure
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*/
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static int
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ufshcd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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struct ufs_hba *hba;
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void __iomem *mmio_base;
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int err;
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err = pcim_enable_device(pdev);
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if (err) {
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dev_err(&pdev->dev, "pcim_enable_device failed\n");
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return err;
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}
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pci_set_master(pdev);
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err = pcim_iomap_regions(pdev, 1 << 0, UFSHCD);
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if (err < 0) {
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dev_err(&pdev->dev, "request and iomap failed\n");
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return err;
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}
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mmio_base = pcim_iomap_table(pdev)[0];
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err = ufshcd_alloc_host(&pdev->dev, &hba);
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if (err) {
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dev_err(&pdev->dev, "Allocation failed\n");
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return err;
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}
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pci_set_drvdata(pdev, hba);
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hba->vops = (struct ufs_hba_variant_ops *)id->driver_data;
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err = ufshcd_init(hba, mmio_base, pdev->irq);
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if (err) {
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dev_err(&pdev->dev, "Initialization failed\n");
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ufshcd_dealloc_host(hba);
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return err;
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}
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pm_runtime_put_noidle(&pdev->dev);
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pm_runtime_allow(&pdev->dev);
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return 0;
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}
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static const struct dev_pm_ops ufshcd_pci_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(ufshcd_pci_suspend,
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ufshcd_pci_resume)
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SET_RUNTIME_PM_OPS(ufshcd_pci_runtime_suspend,
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ufshcd_pci_runtime_resume,
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ufshcd_pci_runtime_idle)
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};
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static const struct pci_device_id ufshcd_pci_tbl[] = {
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{ PCI_VENDOR_ID_SAMSUNG, 0xC00C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
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{ PCI_VDEVICE(INTEL, 0x9DFA), (kernel_ulong_t)&ufs_intel_cnl_hba_vops },
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{ PCI_VDEVICE(INTEL, 0x4B41), (kernel_ulong_t)&ufs_intel_ehl_hba_vops },
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{ PCI_VDEVICE(INTEL, 0x4B43), (kernel_ulong_t)&ufs_intel_ehl_hba_vops },
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{ } /* terminate list */
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};
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MODULE_DEVICE_TABLE(pci, ufshcd_pci_tbl);
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static struct pci_driver ufshcd_pci_driver = {
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.name = UFSHCD,
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.id_table = ufshcd_pci_tbl,
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.probe = ufshcd_pci_probe,
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.remove = ufshcd_pci_remove,
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.shutdown = ufshcd_pci_shutdown,
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.driver = {
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.pm = &ufshcd_pci_pm_ops
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},
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};
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module_pci_driver(ufshcd_pci_driver);
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MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
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MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
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MODULE_DESCRIPTION("UFS host controller PCI glue driver");
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MODULE_LICENSE("GPL");
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MODULE_VERSION(UFSHCD_DRIVER_VERSION);
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