517 строки
13 KiB
C
517 строки
13 KiB
C
/*
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* IMG I2S input controller driver
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*
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* Copyright (C) 2015 Imagination Technologies Ltd.
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*
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* Author: Damien Horsley <Damien.Horsley@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <sound/core.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/initval.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#define IMG_I2S_IN_RX_FIFO 0x0
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#define IMG_I2S_IN_CTL 0x4
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#define IMG_I2S_IN_CTL_ACTIVE_CHAN_MASK 0xfffffffc
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#define IMG_I2S_IN_CTL_ACTIVE_CH_SHIFT 2
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#define IMG_I2S_IN_CTL_16PACK_MASK BIT(1)
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#define IMG_I2S_IN_CTL_ME_MASK BIT(0)
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#define IMG_I2S_IN_CH_CTL 0x4
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#define IMG_I2S_IN_CH_CTL_CCDEL_MASK 0x38000
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#define IMG_I2S_IN_CH_CTL_CCDEL_SHIFT 15
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#define IMG_I2S_IN_CH_CTL_FEN_MASK BIT(14)
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#define IMG_I2S_IN_CH_CTL_FMODE_MASK BIT(13)
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#define IMG_I2S_IN_CH_CTL_16PACK_MASK BIT(12)
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#define IMG_I2S_IN_CH_CTL_JUST_MASK BIT(10)
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#define IMG_I2S_IN_CH_CTL_PACKH_MASK BIT(9)
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#define IMG_I2S_IN_CH_CTL_CLK_TRANS_MASK BIT(8)
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#define IMG_I2S_IN_CH_CTL_BLKP_MASK BIT(7)
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#define IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK BIT(6)
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#define IMG_I2S_IN_CH_CTL_LRD_MASK BIT(3)
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#define IMG_I2S_IN_CH_CTL_FW_MASK BIT(2)
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#define IMG_I2S_IN_CH_CTL_SW_MASK BIT(1)
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#define IMG_I2S_IN_CH_CTL_ME_MASK BIT(0)
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#define IMG_I2S_IN_CH_STRIDE 0x20
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struct img_i2s_in {
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void __iomem *base;
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struct clk *clk_sys;
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struct snd_dmaengine_dai_dma_data dma_data;
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struct device *dev;
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unsigned int max_i2s_chan;
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void __iomem *channel_base;
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unsigned int active_channels;
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struct snd_soc_dai_driver dai_driver;
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};
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static inline void img_i2s_in_writel(struct img_i2s_in *i2s, u32 val, u32 reg)
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{
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writel(val, i2s->base + reg);
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}
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static inline u32 img_i2s_in_readl(struct img_i2s_in *i2s, u32 reg)
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{
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return readl(i2s->base + reg);
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}
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static inline void img_i2s_in_ch_writel(struct img_i2s_in *i2s, u32 chan,
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u32 val, u32 reg)
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{
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writel(val, i2s->channel_base + (chan * IMG_I2S_IN_CH_STRIDE) + reg);
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}
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static inline u32 img_i2s_in_ch_readl(struct img_i2s_in *i2s, u32 chan,
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u32 reg)
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{
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return readl(i2s->channel_base + (chan * IMG_I2S_IN_CH_STRIDE) + reg);
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}
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static inline void img_i2s_in_ch_disable(struct img_i2s_in *i2s, u32 chan)
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{
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u32 reg;
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reg = img_i2s_in_ch_readl(i2s, chan, IMG_I2S_IN_CH_CTL);
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reg &= ~IMG_I2S_IN_CH_CTL_ME_MASK;
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img_i2s_in_ch_writel(i2s, chan, reg, IMG_I2S_IN_CH_CTL);
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}
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static inline void img_i2s_in_ch_enable(struct img_i2s_in *i2s, u32 chan)
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{
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u32 reg;
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reg = img_i2s_in_ch_readl(i2s, chan, IMG_I2S_IN_CH_CTL);
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reg |= IMG_I2S_IN_CH_CTL_ME_MASK;
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img_i2s_in_ch_writel(i2s, chan, reg, IMG_I2S_IN_CH_CTL);
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}
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static inline void img_i2s_in_disable(struct img_i2s_in *i2s)
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{
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u32 reg;
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reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
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reg &= ~IMG_I2S_IN_CTL_ME_MASK;
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img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL);
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}
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static inline void img_i2s_in_enable(struct img_i2s_in *i2s)
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{
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u32 reg;
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reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
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reg |= IMG_I2S_IN_CTL_ME_MASK;
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img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL);
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}
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static inline void img_i2s_in_flush(struct img_i2s_in *i2s)
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{
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int i;
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u32 reg;
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for (i = 0; i < i2s->active_channels; i++) {
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reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
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reg |= IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK;
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img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
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reg &= ~IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK;
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img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
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}
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}
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static int img_i2s_in_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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img_i2s_in_enable(i2s);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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img_i2s_in_disable(i2s);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int img_i2s_in_check_rate(struct img_i2s_in *i2s,
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unsigned int sample_rate, unsigned int frame_size,
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unsigned int *bclk_filter_enable,
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unsigned int *bclk_filter_value)
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{
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unsigned int bclk_freq, cur_freq;
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bclk_freq = sample_rate * frame_size;
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cur_freq = clk_get_rate(i2s->clk_sys);
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if (cur_freq >= bclk_freq * 8) {
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*bclk_filter_enable = 1;
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*bclk_filter_value = 0;
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} else if (cur_freq >= bclk_freq * 7) {
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*bclk_filter_enable = 1;
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*bclk_filter_value = 1;
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} else if (cur_freq >= bclk_freq * 6) {
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*bclk_filter_enable = 0;
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*bclk_filter_value = 0;
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} else {
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dev_err(i2s->dev,
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"Sys clock rate %u insufficient for sample rate %u\n",
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cur_freq, sample_rate);
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return -EINVAL;
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}
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return 0;
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}
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static int img_i2s_in_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
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{
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struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
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unsigned int rate, channels, i2s_channels, frame_size;
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unsigned int bclk_filter_enable, bclk_filter_value;
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int i, ret = 0;
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u32 reg, control_mask, chan_control_mask;
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u32 control_set = 0, chan_control_set = 0;
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snd_pcm_format_t format;
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rate = params_rate(params);
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format = params_format(params);
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channels = params_channels(params);
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i2s_channels = channels / 2;
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switch (format) {
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case SNDRV_PCM_FORMAT_S32_LE:
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frame_size = 64;
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chan_control_set |= IMG_I2S_IN_CH_CTL_SW_MASK;
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chan_control_set |= IMG_I2S_IN_CH_CTL_FW_MASK;
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chan_control_set |= IMG_I2S_IN_CH_CTL_PACKH_MASK;
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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frame_size = 64;
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chan_control_set |= IMG_I2S_IN_CH_CTL_SW_MASK;
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chan_control_set |= IMG_I2S_IN_CH_CTL_FW_MASK;
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break;
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case SNDRV_PCM_FORMAT_S16_LE:
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frame_size = 32;
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control_set |= IMG_I2S_IN_CTL_16PACK_MASK;
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chan_control_set |= IMG_I2S_IN_CH_CTL_16PACK_MASK;
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break;
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default:
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return -EINVAL;
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}
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if ((channels < 2) ||
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(channels > (i2s->max_i2s_chan * 2)) ||
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(channels % 2))
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return -EINVAL;
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control_set |= ((i2s_channels - 1) << IMG_I2S_IN_CTL_ACTIVE_CH_SHIFT);
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ret = img_i2s_in_check_rate(i2s, rate, frame_size,
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&bclk_filter_enable, &bclk_filter_value);
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if (ret < 0)
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return ret;
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if (bclk_filter_enable)
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chan_control_set |= IMG_I2S_IN_CH_CTL_FEN_MASK;
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if (bclk_filter_value)
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chan_control_set |= IMG_I2S_IN_CH_CTL_FMODE_MASK;
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control_mask = IMG_I2S_IN_CTL_16PACK_MASK |
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IMG_I2S_IN_CTL_ACTIVE_CHAN_MASK;
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chan_control_mask = IMG_I2S_IN_CH_CTL_16PACK_MASK |
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IMG_I2S_IN_CH_CTL_FEN_MASK |
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IMG_I2S_IN_CH_CTL_FMODE_MASK |
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IMG_I2S_IN_CH_CTL_SW_MASK |
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IMG_I2S_IN_CH_CTL_FW_MASK |
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IMG_I2S_IN_CH_CTL_PACKH_MASK;
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reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
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reg = (reg & ~control_mask) | control_set;
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img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL);
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for (i = 0; i < i2s->active_channels; i++)
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img_i2s_in_ch_disable(i2s, i);
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for (i = 0; i < i2s->max_i2s_chan; i++) {
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reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
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reg = (reg & ~chan_control_mask) | chan_control_set;
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img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
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}
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i2s->active_channels = i2s_channels;
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img_i2s_in_flush(i2s);
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for (i = 0; i < i2s->active_channels; i++)
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img_i2s_in_ch_enable(i2s, i);
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return 0;
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}
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static int img_i2s_in_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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{
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struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
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int i;
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u32 chan_control_mask, lrd_set = 0, blkp_set = 0, chan_control_set = 0;
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u32 reg;
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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lrd_set |= IMG_I2S_IN_CH_CTL_LRD_MASK;
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break;
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case SND_SOC_DAIFMT_NB_IF:
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break;
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case SND_SOC_DAIFMT_IB_NF:
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lrd_set |= IMG_I2S_IN_CH_CTL_LRD_MASK;
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blkp_set |= IMG_I2S_IN_CH_CTL_BLKP_MASK;
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break;
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case SND_SOC_DAIFMT_IB_IF:
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blkp_set |= IMG_I2S_IN_CH_CTL_BLKP_MASK;
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break;
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default:
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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chan_control_set |= IMG_I2S_IN_CH_CTL_CLK_TRANS_MASK;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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break;
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default:
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBM_CFM:
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break;
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default:
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return -EINVAL;
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}
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chan_control_mask = IMG_I2S_IN_CH_CTL_CLK_TRANS_MASK;
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for (i = 0; i < i2s->active_channels; i++)
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img_i2s_in_ch_disable(i2s, i);
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/*
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* BLKP and LRD must be set during separate register writes
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*/
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for (i = 0; i < i2s->max_i2s_chan; i++) {
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reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
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reg = (reg & ~chan_control_mask) | chan_control_set;
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img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
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reg = (reg & ~IMG_I2S_IN_CH_CTL_BLKP_MASK) | blkp_set;
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img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
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reg = (reg & ~IMG_I2S_IN_CH_CTL_LRD_MASK) | lrd_set;
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img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
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}
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for (i = 0; i < i2s->active_channels; i++)
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img_i2s_in_ch_enable(i2s, i);
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return 0;
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}
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static const struct snd_soc_dai_ops img_i2s_in_dai_ops = {
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.trigger = img_i2s_in_trigger,
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.hw_params = img_i2s_in_hw_params,
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.set_fmt = img_i2s_in_set_fmt
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};
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static int img_i2s_in_dai_probe(struct snd_soc_dai *dai)
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{
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struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
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snd_soc_dai_init_dma_data(dai, NULL, &i2s->dma_data);
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return 0;
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}
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static const struct snd_soc_component_driver img_i2s_in_component = {
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.name = "img-i2s-in"
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};
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static int img_i2s_in_dma_prepare_slave_config(struct snd_pcm_substream *st,
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struct snd_pcm_hw_params *params, struct dma_slave_config *sc)
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{
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unsigned int i2s_channels = params_channels(params) / 2;
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struct snd_soc_pcm_runtime *rtd = st->private_data;
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struct snd_dmaengine_dai_dma_data *dma_data;
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int ret;
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dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, st);
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ret = snd_hwparams_to_dma_slave_config(st, params, sc);
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if (ret)
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return ret;
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sc->src_addr = dma_data->addr;
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sc->src_addr_width = dma_data->addr_width;
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sc->src_maxburst = 4 * i2s_channels;
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return 0;
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}
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static const struct snd_dmaengine_pcm_config img_i2s_in_dma_config = {
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.prepare_slave_config = img_i2s_in_dma_prepare_slave_config
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};
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static int img_i2s_in_probe(struct platform_device *pdev)
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{
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struct img_i2s_in *i2s;
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struct resource *res;
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void __iomem *base;
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int ret, i;
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struct reset_control *rst;
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unsigned int max_i2s_chan_pow_2;
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struct device *dev = &pdev->dev;
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i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
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if (!i2s)
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return -ENOMEM;
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platform_set_drvdata(pdev, i2s);
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i2s->dev = dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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i2s->base = base;
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if (of_property_read_u32(pdev->dev.of_node, "img,i2s-channels",
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&i2s->max_i2s_chan)) {
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dev_err(dev, "No img,i2s-channels property\n");
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return -EINVAL;
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}
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max_i2s_chan_pow_2 = 1 << get_count_order(i2s->max_i2s_chan);
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i2s->channel_base = base + (max_i2s_chan_pow_2 * 0x20);
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i2s->clk_sys = devm_clk_get(dev, "sys");
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if (IS_ERR(i2s->clk_sys)) {
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if (PTR_ERR(i2s->clk_sys) != -EPROBE_DEFER)
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dev_err(dev, "Failed to acquire clock 'sys'\n");
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return PTR_ERR(i2s->clk_sys);
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}
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ret = clk_prepare_enable(i2s->clk_sys);
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if (ret)
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return ret;
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i2s->active_channels = 1;
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i2s->dma_data.addr = res->start + IMG_I2S_IN_RX_FIFO;
|
|
i2s->dma_data.addr_width = 4;
|
|
|
|
i2s->dai_driver.probe = img_i2s_in_dai_probe;
|
|
i2s->dai_driver.capture.channels_min = 2;
|
|
i2s->dai_driver.capture.channels_max = i2s->max_i2s_chan * 2;
|
|
i2s->dai_driver.capture.rates = SNDRV_PCM_RATE_8000_192000;
|
|
i2s->dai_driver.capture.formats = SNDRV_PCM_FMTBIT_S32_LE |
|
|
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE;
|
|
i2s->dai_driver.ops = &img_i2s_in_dai_ops;
|
|
|
|
rst = devm_reset_control_get(dev, "rst");
|
|
if (IS_ERR(rst)) {
|
|
if (PTR_ERR(rst) == -EPROBE_DEFER) {
|
|
ret = -EPROBE_DEFER;
|
|
goto err_clk_disable;
|
|
}
|
|
|
|
dev_dbg(dev, "No top level reset found\n");
|
|
|
|
img_i2s_in_disable(i2s);
|
|
|
|
for (i = 0; i < i2s->max_i2s_chan; i++)
|
|
img_i2s_in_ch_disable(i2s, i);
|
|
} else {
|
|
reset_control_assert(rst);
|
|
reset_control_deassert(rst);
|
|
}
|
|
|
|
img_i2s_in_writel(i2s, 0, IMG_I2S_IN_CTL);
|
|
|
|
for (i = 0; i < i2s->max_i2s_chan; i++)
|
|
img_i2s_in_ch_writel(i2s, i,
|
|
(4 << IMG_I2S_IN_CH_CTL_CCDEL_SHIFT) |
|
|
IMG_I2S_IN_CH_CTL_JUST_MASK |
|
|
IMG_I2S_IN_CH_CTL_FW_MASK, IMG_I2S_IN_CH_CTL);
|
|
|
|
ret = devm_snd_soc_register_component(dev, &img_i2s_in_component,
|
|
&i2s->dai_driver, 1);
|
|
if (ret)
|
|
goto err_clk_disable;
|
|
|
|
ret = devm_snd_dmaengine_pcm_register(dev, &img_i2s_in_dma_config, 0);
|
|
if (ret)
|
|
goto err_clk_disable;
|
|
|
|
return 0;
|
|
|
|
err_clk_disable:
|
|
clk_disable_unprepare(i2s->clk_sys);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int img_i2s_in_dev_remove(struct platform_device *pdev)
|
|
{
|
|
struct img_i2s_in *i2s = platform_get_drvdata(pdev);
|
|
|
|
clk_disable_unprepare(i2s->clk_sys);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id img_i2s_in_of_match[] = {
|
|
{ .compatible = "img,i2s-in" },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, img_i2s_in_of_match);
|
|
|
|
static struct platform_driver img_i2s_in_driver = {
|
|
.driver = {
|
|
.name = "img-i2s-in",
|
|
.of_match_table = img_i2s_in_of_match
|
|
},
|
|
.probe = img_i2s_in_probe,
|
|
.remove = img_i2s_in_dev_remove
|
|
};
|
|
module_platform_driver(img_i2s_in_driver);
|
|
|
|
MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
|
|
MODULE_DESCRIPTION("IMG I2S Input Driver");
|
|
MODULE_LICENSE("GPL v2");
|