332 строки
8.4 KiB
C
332 строки
8.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/interconnect-provider.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/interconnect/qcom,osm-l3.h>
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#include "sc7180.h"
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#include "sdm845.h"
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#include "sm8150.h"
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#include "sm8250.h"
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#define LUT_MAX_ENTRIES 40U
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#define LUT_SRC GENMASK(31, 30)
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#define LUT_L_VAL GENMASK(7, 0)
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#define CLK_HW_DIV 2
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/* OSM Register offsets */
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#define REG_ENABLE 0x0
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#define OSM_LUT_ROW_SIZE 32
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#define OSM_REG_FREQ_LUT 0x110
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#define OSM_REG_PERF_STATE 0x920
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/* EPSS Register offsets */
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#define EPSS_LUT_ROW_SIZE 4
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#define EPSS_REG_FREQ_LUT 0x100
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#define EPSS_REG_PERF_STATE 0x320
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#define OSM_L3_MAX_LINKS 1
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#define to_qcom_provider(_provider) \
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container_of(_provider, struct qcom_osm_l3_icc_provider, provider)
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struct qcom_osm_l3_icc_provider {
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void __iomem *base;
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unsigned int max_state;
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unsigned int reg_perf_state;
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unsigned long lut_tables[LUT_MAX_ENTRIES];
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struct icc_provider provider;
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};
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/**
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* struct qcom_icc_node - Qualcomm specific interconnect nodes
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* @name: the node name used in debugfs
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* @links: an array of nodes where we can go next while traversing
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* @id: a unique node identifier
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* @num_links: the total number of @links
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* @buswidth: width of the interconnect between a node and the bus
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*/
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struct qcom_icc_node {
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const char *name;
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u16 links[OSM_L3_MAX_LINKS];
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u16 id;
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u16 num_links;
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u16 buswidth;
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};
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struct qcom_icc_desc {
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const struct qcom_icc_node **nodes;
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size_t num_nodes;
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unsigned int lut_row_size;
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unsigned int reg_freq_lut;
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unsigned int reg_perf_state;
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};
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#define DEFINE_QNODE(_name, _id, _buswidth, ...) \
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static const struct qcom_icc_node _name = { \
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.name = #_name, \
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.id = _id, \
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.buswidth = _buswidth, \
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.num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \
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.links = { __VA_ARGS__ }, \
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}
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DEFINE_QNODE(sdm845_osm_apps_l3, SDM845_MASTER_OSM_L3_APPS, 16, SDM845_SLAVE_OSM_L3);
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DEFINE_QNODE(sdm845_osm_l3, SDM845_SLAVE_OSM_L3, 16);
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static const struct qcom_icc_node *sdm845_osm_l3_nodes[] = {
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[MASTER_OSM_L3_APPS] = &sdm845_osm_apps_l3,
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[SLAVE_OSM_L3] = &sdm845_osm_l3,
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};
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static const struct qcom_icc_desc sdm845_icc_osm_l3 = {
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.nodes = sdm845_osm_l3_nodes,
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.num_nodes = ARRAY_SIZE(sdm845_osm_l3_nodes),
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.lut_row_size = OSM_LUT_ROW_SIZE,
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.reg_freq_lut = OSM_REG_FREQ_LUT,
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.reg_perf_state = OSM_REG_PERF_STATE,
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};
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DEFINE_QNODE(sc7180_osm_apps_l3, SC7180_MASTER_OSM_L3_APPS, 16, SC7180_SLAVE_OSM_L3);
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DEFINE_QNODE(sc7180_osm_l3, SC7180_SLAVE_OSM_L3, 16);
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static const struct qcom_icc_node *sc7180_osm_l3_nodes[] = {
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[MASTER_OSM_L3_APPS] = &sc7180_osm_apps_l3,
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[SLAVE_OSM_L3] = &sc7180_osm_l3,
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};
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static const struct qcom_icc_desc sc7180_icc_osm_l3 = {
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.nodes = sc7180_osm_l3_nodes,
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.num_nodes = ARRAY_SIZE(sc7180_osm_l3_nodes),
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.lut_row_size = OSM_LUT_ROW_SIZE,
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.reg_freq_lut = OSM_REG_FREQ_LUT,
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.reg_perf_state = OSM_REG_PERF_STATE,
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};
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DEFINE_QNODE(sm8150_osm_apps_l3, SM8150_MASTER_OSM_L3_APPS, 32, SM8150_SLAVE_OSM_L3);
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DEFINE_QNODE(sm8150_osm_l3, SM8150_SLAVE_OSM_L3, 32);
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static const struct qcom_icc_node *sm8150_osm_l3_nodes[] = {
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[MASTER_OSM_L3_APPS] = &sm8150_osm_apps_l3,
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[SLAVE_OSM_L3] = &sm8150_osm_l3,
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};
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static const struct qcom_icc_desc sm8150_icc_osm_l3 = {
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.nodes = sm8150_osm_l3_nodes,
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.num_nodes = ARRAY_SIZE(sm8150_osm_l3_nodes),
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.lut_row_size = OSM_LUT_ROW_SIZE,
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.reg_freq_lut = OSM_REG_FREQ_LUT,
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.reg_perf_state = OSM_REG_PERF_STATE,
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};
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DEFINE_QNODE(sm8250_epss_apps_l3, SM8250_MASTER_EPSS_L3_APPS, 32, SM8250_SLAVE_EPSS_L3);
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DEFINE_QNODE(sm8250_epss_l3, SM8250_SLAVE_EPSS_L3, 32);
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static const struct qcom_icc_node *sm8250_epss_l3_nodes[] = {
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[MASTER_EPSS_L3_APPS] = &sm8250_epss_apps_l3,
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[SLAVE_EPSS_L3_SHARED] = &sm8250_epss_l3,
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};
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static const struct qcom_icc_desc sm8250_icc_epss_l3 = {
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.nodes = sm8250_epss_l3_nodes,
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.num_nodes = ARRAY_SIZE(sm8250_epss_l3_nodes),
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.lut_row_size = EPSS_LUT_ROW_SIZE,
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.reg_freq_lut = EPSS_REG_FREQ_LUT,
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.reg_perf_state = EPSS_REG_PERF_STATE,
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};
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static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
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{
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struct qcom_osm_l3_icc_provider *qp;
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struct icc_provider *provider;
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const struct qcom_icc_node *qn;
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struct icc_node *n;
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unsigned int index;
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u32 agg_peak = 0;
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u32 agg_avg = 0;
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u64 rate;
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qn = src->data;
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provider = src->provider;
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qp = to_qcom_provider(provider);
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list_for_each_entry(n, &provider->nodes, node_list)
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provider->aggregate(n, 0, n->avg_bw, n->peak_bw,
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&agg_avg, &agg_peak);
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rate = max(agg_avg, agg_peak);
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rate = icc_units_to_bps(rate);
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do_div(rate, qn->buswidth);
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for (index = 0; index < qp->max_state - 1; index++) {
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if (qp->lut_tables[index] >= rate)
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break;
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}
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writel_relaxed(index, qp->base + qp->reg_perf_state);
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return 0;
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}
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static int qcom_osm_l3_remove(struct platform_device *pdev)
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{
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struct qcom_osm_l3_icc_provider *qp = platform_get_drvdata(pdev);
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icc_nodes_remove(&qp->provider);
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return icc_provider_del(&qp->provider);
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}
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static int qcom_osm_l3_probe(struct platform_device *pdev)
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{
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u32 info, src, lval, i, prev_freq = 0, freq;
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static unsigned long hw_rate, xo_rate;
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struct qcom_osm_l3_icc_provider *qp;
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const struct qcom_icc_desc *desc;
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struct icc_onecell_data *data;
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struct icc_provider *provider;
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const struct qcom_icc_node **qnodes;
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struct icc_node *node;
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size_t num_nodes;
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struct clk *clk;
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int ret;
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clk = clk_get(&pdev->dev, "xo");
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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xo_rate = clk_get_rate(clk);
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clk_put(clk);
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clk = clk_get(&pdev->dev, "alternate");
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
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clk_put(clk);
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qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
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if (!qp)
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return -ENOMEM;
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qp->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(qp->base))
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return PTR_ERR(qp->base);
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/* HW should be in enabled state to proceed */
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if (!(readl_relaxed(qp->base + REG_ENABLE) & 0x1)) {
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dev_err(&pdev->dev, "error hardware not enabled\n");
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return -ENODEV;
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}
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desc = device_get_match_data(&pdev->dev);
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if (!desc)
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return -EINVAL;
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qp->reg_perf_state = desc->reg_perf_state;
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for (i = 0; i < LUT_MAX_ENTRIES; i++) {
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info = readl_relaxed(qp->base + desc->reg_freq_lut +
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i * desc->lut_row_size);
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src = FIELD_GET(LUT_SRC, info);
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lval = FIELD_GET(LUT_L_VAL, info);
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if (src)
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freq = xo_rate * lval;
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else
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freq = hw_rate;
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/* Two of the same frequencies signify end of table */
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if (i > 0 && prev_freq == freq)
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break;
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dev_dbg(&pdev->dev, "index=%d freq=%d\n", i, freq);
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qp->lut_tables[i] = freq;
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prev_freq = freq;
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}
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qp->max_state = i;
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qnodes = desc->nodes;
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num_nodes = desc->num_nodes;
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data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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provider = &qp->provider;
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provider->dev = &pdev->dev;
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provider->set = qcom_icc_set;
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provider->aggregate = icc_std_aggregate;
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provider->xlate = of_icc_xlate_onecell;
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INIT_LIST_HEAD(&provider->nodes);
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provider->data = data;
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ret = icc_provider_add(provider);
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if (ret) {
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dev_err(&pdev->dev, "error adding interconnect provider\n");
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return ret;
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}
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for (i = 0; i < num_nodes; i++) {
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size_t j;
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node = icc_node_create(qnodes[i]->id);
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if (IS_ERR(node)) {
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ret = PTR_ERR(node);
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goto err;
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}
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node->name = qnodes[i]->name;
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/* Cast away const and add it back in qcom_icc_set() */
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node->data = (void *)qnodes[i];
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icc_node_add(node, provider);
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for (j = 0; j < qnodes[i]->num_links; j++)
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icc_link_create(node, qnodes[i]->links[j]);
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data->nodes[i] = node;
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}
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data->num_nodes = num_nodes;
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platform_set_drvdata(pdev, qp);
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return 0;
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err:
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icc_nodes_remove(provider);
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icc_provider_del(provider);
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return ret;
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}
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static const struct of_device_id osm_l3_of_match[] = {
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{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
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{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
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{ .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },
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{ .compatible = "qcom,sm8250-epss-l3", .data = &sm8250_icc_epss_l3 },
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{ }
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};
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MODULE_DEVICE_TABLE(of, osm_l3_of_match);
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static struct platform_driver osm_l3_driver = {
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.probe = qcom_osm_l3_probe,
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.remove = qcom_osm_l3_remove,
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.driver = {
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.name = "osm-l3",
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.of_match_table = osm_l3_of_match,
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.sync_state = icc_sync_state,
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},
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};
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module_platform_driver(osm_l3_driver);
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MODULE_DESCRIPTION("Qualcomm OSM L3 interconnect driver");
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MODULE_LICENSE("GPL v2");
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