503 строки
15 KiB
C
503 строки
15 KiB
C
/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __TEGRA_CLK_H
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#define __TEGRA_CLK_H
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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/**
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* struct tegra_clk_sync_source - external clock source from codec
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*
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* @hw: handle between common and hardware-specific interfaces
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* @rate: input frequency from source
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* @max_rate: max rate allowed
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*/
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struct tegra_clk_sync_source {
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struct clk_hw hw;
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unsigned long rate;
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unsigned long max_rate;
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};
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#define to_clk_sync_source(_hw) \
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container_of(_hw, struct tegra_clk_sync_source, hw)
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extern const struct clk_ops tegra_clk_sync_source_ops;
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struct clk *tegra_clk_register_sync_source(const char *name,
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unsigned long fixed_rate, unsigned long max_rate);
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/**
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* struct tegra_clk_frac_div - fractional divider clock
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*
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* @hw: handle between common and hardware-specific interfaces
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* @reg: register containing divider
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* @flags: hardware-specific flags
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* @shift: shift to the divider bit field
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* @width: width of the divider bit field
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* @frac_width: width of the fractional bit field
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* @lock: register lock
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*
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* Flags:
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* TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
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* TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
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* flag indicates that this divider is for fixed rate PLL.
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* TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when
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* fraction bit is set. This flags indicates to calculate divider for which
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* fracton bit will be zero.
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* TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is
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* set when divider value is not 0. This flags indicates that the divider
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* is for UART module.
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*/
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struct tegra_clk_frac_div {
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struct clk_hw hw;
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void __iomem *reg;
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u8 flags;
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u8 shift;
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u8 width;
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u8 frac_width;
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spinlock_t *lock;
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};
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#define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw)
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#define TEGRA_DIVIDER_ROUND_UP BIT(0)
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#define TEGRA_DIVIDER_FIXED BIT(1)
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#define TEGRA_DIVIDER_INT BIT(2)
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#define TEGRA_DIVIDER_UART BIT(3)
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extern const struct clk_ops tegra_clk_frac_div_ops;
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struct clk *tegra_clk_register_divider(const char *name,
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const char *parent_name, void __iomem *reg,
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unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width,
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u8 frac_width, spinlock_t *lock);
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/*
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* Tegra PLL:
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*
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* In general, there are 3 requirements for each PLL
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* that SW needs to be comply with.
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* (1) Input frequency range (REF).
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* (2) Comparison frequency range (CF). CF = REF/DIVM.
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* (3) VCO frequency range (VCO). VCO = CF * DIVN.
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*
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* The final PLL output frequency (FO) = VCO >> DIVP.
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*/
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/**
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* struct tegra_clk_pll_freq_table - PLL frequecy table
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*
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* @input_rate: input rate from source
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* @output_rate: output rate from PLL for the input rate
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* @n: feedback divider
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* @m: input divider
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* @p: post divider
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* @cpcon: charge pump current
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*/
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struct tegra_clk_pll_freq_table {
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unsigned long input_rate;
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unsigned long output_rate;
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u16 n;
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u16 m;
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u8 p;
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u8 cpcon;
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};
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/**
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* struct clk_pll_params - PLL parameters
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*
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* @input_min: Minimum input frequency
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* @input_max: Maximum input frequency
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* @cf_min: Minimum comparison frequency
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* @cf_max: Maximum comparison frequency
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* @vco_min: Minimum VCO frequency
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* @vco_max: Maximum VCO frequency
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* @base_reg: PLL base reg offset
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* @misc_reg: PLL misc reg offset
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* @lock_reg: PLL lock reg offset
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* @lock_bit_idx: Bit index for PLL lock status
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* @lock_enable_bit_idx: Bit index to enable PLL lock
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* @lock_delay: Delay in us if PLL lock is not used
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*/
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struct tegra_clk_pll_params {
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unsigned long input_min;
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unsigned long input_max;
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unsigned long cf_min;
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unsigned long cf_max;
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unsigned long vco_min;
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unsigned long vco_max;
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u32 base_reg;
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u32 misc_reg;
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u32 lock_reg;
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u32 lock_bit_idx;
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u32 lock_enable_bit_idx;
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int lock_delay;
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};
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/**
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* struct tegra_clk_pll - Tegra PLL clock
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*
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* @hw: handle between common and hardware-specifix interfaces
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* @clk_base: address of CAR controller
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* @pmc: address of PMC, required to read override bits
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* @freq_table: array of frequencies supported by PLL
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* @params: PLL parameters
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* @flags: PLL flags
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* @fixed_rate: PLL rate if it is fixed
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* @lock: register lock
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* @divn_shift: shift to the feedback divider bit field
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* @divn_width: width of the feedback divider bit field
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* @divm_shift: shift to the input divider bit field
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* @divm_width: width of the input divider bit field
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* @divp_shift: shift to the post divider bit field
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* @divp_width: width of the post divider bit field
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*
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* Flags:
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* TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
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* PLL locking. If not set it will use lock_delay value to wait.
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* TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs
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* to be programmed to change output frequency of the PLL.
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* TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs
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* to be programmed to change output frequency of the PLL.
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* TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs
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* to be programmed to change output frequency of the PLL.
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* TEGRA_PLLU - PLLU has inverted post divider. This flags indicated
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* that it is PLLU and invert post divider value.
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* TEGRA_PLLM - PLLM has additional override settings in PMC. This
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* flag indicates that it is PLLM and use override settings.
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* TEGRA_PLL_FIXED - We are not supposed to change output frequency
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* of some plls.
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* TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
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*/
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struct tegra_clk_pll {
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struct clk_hw hw;
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void __iomem *clk_base;
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void __iomem *pmc;
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u8 flags;
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unsigned long fixed_rate;
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spinlock_t *lock;
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u8 divn_shift;
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u8 divn_width;
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u8 divm_shift;
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u8 divm_width;
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u8 divp_shift;
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u8 divp_width;
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struct tegra_clk_pll_freq_table *freq_table;
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struct tegra_clk_pll_params *params;
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};
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#define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw)
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#define TEGRA_PLL_USE_LOCK BIT(0)
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#define TEGRA_PLL_HAS_CPCON BIT(1)
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#define TEGRA_PLL_SET_LFCON BIT(2)
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#define TEGRA_PLL_SET_DCCON BIT(3)
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#define TEGRA_PLLU BIT(4)
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#define TEGRA_PLLM BIT(5)
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#define TEGRA_PLL_FIXED BIT(6)
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#define TEGRA_PLLE_CONFIGURE BIT(7)
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extern const struct clk_ops tegra_clk_pll_ops;
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extern const struct clk_ops tegra_clk_plle_ops;
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struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
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void __iomem *clk_base, void __iomem *pmc,
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unsigned long flags, unsigned long fixed_rate,
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struct tegra_clk_pll_params *pll_params, u8 pll_flags,
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struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
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struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
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void __iomem *clk_base, void __iomem *pmc,
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unsigned long flags, unsigned long fixed_rate,
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struct tegra_clk_pll_params *pll_params, u8 pll_flags,
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struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
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/**
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* struct tegra_clk_pll_out - PLL divider down clock
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*
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* @hw: handle between common and hardware-specific interfaces
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* @reg: register containing the PLL divider
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* @enb_bit_idx: bit to enable/disable PLL divider
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* @rst_bit_idx: bit to reset PLL divider
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* @lock: register lock
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* @flags: hardware-specific flags
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*/
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struct tegra_clk_pll_out {
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struct clk_hw hw;
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void __iomem *reg;
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u8 enb_bit_idx;
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u8 rst_bit_idx;
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spinlock_t *lock;
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u8 flags;
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};
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#define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw)
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extern const struct clk_ops tegra_clk_pll_out_ops;
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struct clk *tegra_clk_register_pll_out(const char *name,
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const char *parent_name, void __iomem *reg, u8 enb_bit_idx,
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u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags,
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spinlock_t *lock);
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/**
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* struct tegra_clk_periph_regs - Registers controlling peripheral clock
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*
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* @enb_reg: read the enable status
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* @enb_set_reg: write 1 to enable clock
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* @enb_clr_reg: write 1 to disable clock
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* @rst_reg: read the reset status
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* @rst_set_reg: write 1 to assert the reset of peripheral
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* @rst_clr_reg: write 1 to deassert the reset of peripheral
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*/
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struct tegra_clk_periph_regs {
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u32 enb_reg;
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u32 enb_set_reg;
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u32 enb_clr_reg;
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u32 rst_reg;
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u32 rst_set_reg;
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u32 rst_clr_reg;
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};
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/**
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* struct tegra_clk_periph_gate - peripheral gate clock
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*
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* @magic: magic number to validate type
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* @hw: handle between common and hardware-specific interfaces
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* @clk_base: address of CAR controller
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* @regs: Registers to control the peripheral
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* @flags: hardware-specific flags
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* @clk_num: Clock number
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* @enable_refcnt: array to maintain reference count of the clock
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*
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* Flags:
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* TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed
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* for this module.
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* TEGRA_PERIPH_MANUAL_RESET - This flag indicates not to reset module
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* after clock enable and driver for the module is responsible for
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* doing reset.
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* TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
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* bus to flush the write operation in apb bus. This flag indicates
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* that this peripheral is in apb bus.
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*/
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struct tegra_clk_periph_gate {
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u32 magic;
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struct clk_hw hw;
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void __iomem *clk_base;
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u8 flags;
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int clk_num;
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int *enable_refcnt;
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struct tegra_clk_periph_regs *regs;
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};
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#define to_clk_periph_gate(_hw) \
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container_of(_hw, struct tegra_clk_periph_gate, hw)
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#define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309
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#define TEGRA_PERIPH_NO_RESET BIT(0)
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#define TEGRA_PERIPH_MANUAL_RESET BIT(1)
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#define TEGRA_PERIPH_ON_APB BIT(2)
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void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
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extern const struct clk_ops tegra_clk_periph_gate_ops;
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struct clk *tegra_clk_register_periph_gate(const char *name,
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const char *parent_name, u8 gate_flags, void __iomem *clk_base,
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unsigned long flags, int clk_num,
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struct tegra_clk_periph_regs *pregs, int *enable_refcnt);
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/**
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* struct clk-periph - peripheral clock
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*
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* @magic: magic number to validate type
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* @hw: handle between common and hardware-specific interfaces
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* @mux: mux clock
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* @divider: divider clock
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* @gate: gate clock
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* @mux_ops: mux clock ops
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* @div_ops: divider clock ops
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* @gate_ops: gate clock ops
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*/
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struct tegra_clk_periph {
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u32 magic;
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struct clk_hw hw;
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struct clk_mux mux;
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struct tegra_clk_frac_div divider;
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struct tegra_clk_periph_gate gate;
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const struct clk_ops *mux_ops;
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const struct clk_ops *div_ops;
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const struct clk_ops *gate_ops;
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};
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#define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw)
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#define TEGRA_CLK_PERIPH_MAGIC 0x18221223
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extern const struct clk_ops tegra_clk_periph_ops;
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struct clk *tegra_clk_register_periph(const char *name,
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const char **parent_names, int num_parents,
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struct tegra_clk_periph *periph, void __iomem *clk_base,
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u32 offset);
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struct clk *tegra_clk_register_periph_nodiv(const char *name,
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const char **parent_names, int num_parents,
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struct tegra_clk_periph *periph, void __iomem *clk_base,
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u32 offset);
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#define TEGRA_CLK_PERIPH(_mux_shift, _mux_width, _mux_flags, \
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_div_shift, _div_width, _div_frac_width, \
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_div_flags, _clk_num, _enb_refcnt, _regs, \
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_gate_flags) \
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{ \
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.mux = { \
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.flags = _mux_flags, \
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.shift = _mux_shift, \
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.width = _mux_width, \
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}, \
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.divider = { \
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.flags = _div_flags, \
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.shift = _div_shift, \
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.width = _div_width, \
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.frac_width = _div_frac_width, \
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}, \
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.gate = { \
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.flags = _gate_flags, \
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.clk_num = _clk_num, \
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.enable_refcnt = _enb_refcnt, \
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.regs = _regs, \
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}, \
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.mux_ops = &clk_mux_ops, \
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.div_ops = &tegra_clk_frac_div_ops, \
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.gate_ops = &tegra_clk_periph_gate_ops, \
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}
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struct tegra_periph_init_data {
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const char *name;
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int clk_id;
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const char **parent_names;
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int num_parents;
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struct tegra_clk_periph periph;
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u32 offset;
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const char *con_id;
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const char *dev_id;
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};
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#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset, \
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_mux_shift, _mux_width, _mux_flags, _div_shift, \
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_div_width, _div_frac_width, _div_flags, _regs, \
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_clk_num, _enb_refcnt, _gate_flags, _clk_id) \
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{ \
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.name = _name, \
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.clk_id = _clk_id, \
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.parent_names = _parent_names, \
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.num_parents = ARRAY_SIZE(_parent_names), \
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.periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_width, \
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_mux_flags, _div_shift, \
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_div_width, _div_frac_width, \
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_div_flags, _clk_num, \
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_enb_refcnt, _regs, \
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_gate_flags), \
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.offset = _offset, \
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.con_id = _con_id, \
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.dev_id = _dev_id, \
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}
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/**
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* struct clk_super_mux - super clock
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*
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* @hw: handle between common and hardware-specific interfaces
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* @reg: register controlling multiplexer
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* @width: width of the multiplexer bit field
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* @flags: hardware-specific flags
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* @div2_index: bit controlling divide-by-2
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* @pllx_index: PLLX index in the parent list
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* @lock: register lock
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*
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* Flags:
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* TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates
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* that this is LP cluster clock.
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*/
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struct tegra_clk_super_mux {
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struct clk_hw hw;
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void __iomem *reg;
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u8 width;
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u8 flags;
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u8 div2_index;
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u8 pllx_index;
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spinlock_t *lock;
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};
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#define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw)
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#define TEGRA_DIVIDER_2 BIT(0)
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extern const struct clk_ops tegra_clk_super_ops;
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struct clk *tegra_clk_register_super_mux(const char *name,
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const char **parent_names, u8 num_parents,
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unsigned long flags, void __iomem *reg, u8 clk_super_flags,
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u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock);
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/**
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* struct clk_init_tabel - clock initialization table
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* @clk_id: clock id as mentioned in device tree bindings
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* @parent_id: parent clock id as mentioned in device tree bindings
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* @rate: rate to set
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* @state: enable/disable
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*/
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struct tegra_clk_init_table {
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unsigned int clk_id;
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unsigned int parent_id;
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unsigned long rate;
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int state;
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};
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/**
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* struct clk_duplicate - duplicate clocks
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* @clk_id: clock id as mentioned in device tree bindings
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* @lookup: duplicate lookup entry for the clock
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*/
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struct tegra_clk_duplicate {
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int clk_id;
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struct clk_lookup lookup;
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};
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#define TEGRA_CLK_DUPLICATE(_clk_id, _dev, _con) \
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{ \
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.clk_id = _clk_id, \
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.lookup = { \
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.dev_id = _dev, \
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.con_id = _con, \
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}, \
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}
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void tegra_init_from_table(struct tegra_clk_init_table *tbl,
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struct clk *clks[], int clk_max);
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void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
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struct clk *clks[], int clk_max);
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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void tegra20_clock_init(struct device_node *np);
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#else
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static inline void tegra20_clock_init(struct device_node *np) {}
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#endif /* CONFIG_ARCH_TEGRA_2x_SOC */
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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void tegra30_clock_init(struct device_node *np);
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#else
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static inline void tegra30_clock_init(struct device_node *np) {}
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#endif /* CONFIG_ARCH_TEGRA_3x_SOC */
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#endif /* TEGRA_CLK_H */
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