172 строки
5.6 KiB
C
172 строки
5.6 KiB
C
#ifndef _ASM_POWERPC_PGTABLE_H
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#define _ASM_POWERPC_PGTABLE_H
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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#include <asm/processor.h> /* For TASK_SIZE */
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#include <asm/mmu.h>
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#include <asm/page.h>
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struct mm_struct;
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#ifdef CONFIG_DEBUG_VM
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extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
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#else /* CONFIG_DEBUG_VM */
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static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
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{
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}
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#endif /* !CONFIG_DEBUG_VM */
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#endif /* !__ASSEMBLY__ */
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#if defined(CONFIG_PPC64)
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# include <asm/pgtable-ppc64.h>
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#else
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# include <asm/pgtable-ppc32.h>
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#endif
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/* Special mapping for AGP */
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#define PAGE_AGP (PAGE_KERNEL_NC)
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#define HAVE_PAGE_AGP
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#ifndef __ASSEMBLY__
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/* Insert a PTE, top-level function is out of line. It uses an inline
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* low level function in the respective pgtable-* files
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*/
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extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
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pte_t pte);
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/* This low level function performs the actual PTE insertion
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* Setting the PTE depends on the MMU type and other factors. It's
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* an horrible mess that I'm not going to try to clean up now but
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* I'm keeping it in one place rather than spread around
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*/
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static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, pte_t pte, int percpu)
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{
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#if defined(CONFIG_PPC_STD_MMU_32) && defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT)
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/* First case is 32-bit Hash MMU in SMP mode with 32-bit PTEs. We use the
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* helper pte_update() which does an atomic update. We need to do that
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* because a concurrent invalidation can clear _PAGE_HASHPTE. If it's a
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* per-CPU PTE such as a kmap_atomic, we do a simple update preserving
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* the hash bits instead (ie, same as the non-SMP case)
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*/
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if (percpu)
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*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
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| (pte_val(pte) & ~_PAGE_HASHPTE));
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else
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pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte));
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#elif defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT) && defined(CONFIG_SMP)
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/* Second case is 32-bit with 64-bit PTE in SMP mode. In this case, we
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* can just store as long as we do the two halves in the right order
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* with a barrier in between. This is possible because we take care,
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* in the hash code, to pre-invalidate if the PTE was already hashed,
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* which synchronizes us with any concurrent invalidation.
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* In the percpu case, we also fallback to the simple update preserving
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* the hash bits
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*/
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if (percpu) {
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*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
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| (pte_val(pte) & ~_PAGE_HASHPTE));
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return;
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}
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#if _PAGE_HASHPTE != 0
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if (pte_val(*ptep) & _PAGE_HASHPTE)
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flush_hash_entry(mm, ptep, addr);
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#endif
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__asm__ __volatile__("\
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stw%U0%X0 %2,%0\n\
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eieio\n\
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stw%U0%X0 %L2,%1"
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: "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
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: "r" (pte) : "memory");
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#elif defined(CONFIG_PPC_STD_MMU_32)
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/* Third case is 32-bit hash table in UP mode, we need to preserve
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* the _PAGE_HASHPTE bit since we may not have invalidated the previous
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* translation in the hash yet (done in a subsequent flush_tlb_xxx())
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* and see we need to keep track that this PTE needs invalidating
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*/
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*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
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| (pte_val(pte) & ~_PAGE_HASHPTE));
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#else
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/* Anything else just stores the PTE normally. That covers all 64-bit
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* cases, and 32-bit non-hash with 64-bit PTEs in UP mode
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*/
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*ptep = pte;
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#endif
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}
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#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
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extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
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pte_t *ptep, pte_t entry, int dirty);
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/*
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* Macro to mark a page protection value as "uncacheable".
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*/
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#define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \
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_PAGE_WRITETHRU)
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#define pgprot_noncached(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
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_PAGE_NO_CACHE | _PAGE_GUARDED))
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#define pgprot_noncached_wc(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
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_PAGE_NO_CACHE))
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#define pgprot_cached(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
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_PAGE_COHERENT))
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#define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
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_PAGE_COHERENT | _PAGE_WRITETHRU))
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struct file;
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extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
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unsigned long size, pgprot_t vma_prot);
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#define __HAVE_PHYS_MEM_ACCESS_PROT
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/*
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* ZERO_PAGE is a global shared page that is always zero: used
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* for zero-mapped memory areas etc..
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*/
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extern unsigned long empty_zero_page[];
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#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
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extern pgd_t swapper_pg_dir[];
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extern void paging_init(void);
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/*
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* kern_addr_valid is intended to indicate whether an address is a valid
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* kernel address. Most 32-bit archs define it as always true (like this)
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* but most 64-bit archs actually perform a test. What should we do here?
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*/
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#define kern_addr_valid(addr) (1)
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#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
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remap_pfn_range(vma, vaddr, pfn, size, prot)
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#include <asm-generic/pgtable.h>
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/*
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* This gets called at the end of handling a page fault, when
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* the kernel has put a new PTE into the page table for the process.
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* We use it to ensure coherency between the i-cache and d-cache
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* for the page which has just been mapped in.
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* On machines which use an MMU hash table, we use this to put a
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* corresponding HPTE into the hash table ahead of time, instead of
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* waiting for the inevitable extra hash-table miss exception.
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*/
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extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_PGTABLE_H */
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