195 строки
6.5 KiB
C
195 строки
6.5 KiB
C
/*********************************************************************
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* $Id: smsc-ircc2.h,v 1.12.2.1 2002/10/27 10:52:37 dip Exp $
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*
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* Description: Definitions for the SMC IrCC chipset
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* Status: Experimental.
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* Author: Daniele Peri (peri@csai.unipa.it)
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*
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* Copyright (c) 2002 Daniele Peri
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* All Rights Reserved.
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*
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* Based on smc-ircc.h:
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*
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* Copyright (c) 1999-2000, Dag Brattli <dagb@cs.uit.no>
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* Copyright (c) 1998-1999, Thomas Davis (tadavis@jps.net>
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* All Rights Reserved
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*
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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********************************************************************/
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#ifndef SMSC_IRCC2_H
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#define SMSC_IRCC2_H
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/* DMA modes needed */
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#define DMA_TX_MODE 0x08 /* Mem to I/O, ++, demand. */
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#define DMA_RX_MODE 0x04 /* I/O to mem, ++, demand. */
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/* Master Control Register */
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#define IRCC_MASTER 0x07
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#define IRCC_MASTER_POWERDOWN 0x80
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#define IRCC_MASTER_RESET 0x40
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#define IRCC_MASTER_INT_EN 0x20
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#define IRCC_MASTER_ERROR_RESET 0x10
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/* Register block 0 */
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/* Interrupt Identification */
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#define IRCC_IIR 0x01
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#define IRCC_IIR_ACTIVE_FRAME 0x80
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#define IRCC_IIR_EOM 0x40
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#define IRCC_IIR_RAW_MODE 0x20
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#define IRCC_IIR_FIFO 0x10
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/* Interrupt Enable */
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#define IRCC_IER 0x02
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#define IRCC_IER_ACTIVE_FRAME 0x80
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#define IRCC_IER_EOM 0x40
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#define IRCC_IER_RAW_MODE 0x20
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#define IRCC_IER_FIFO 0x10
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/* Line Status Register */
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#define IRCC_LSR 0x03
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#define IRCC_LSR_UNDERRUN 0x80
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#define IRCC_LSR_OVERRUN 0x40
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#define IRCC_LSR_FRAME_ERROR 0x20
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#define IRCC_LSR_SIZE_ERROR 0x10
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#define IRCC_LSR_CRC_ERROR 0x80
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#define IRCC_LSR_FRAME_ABORT 0x40
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/* Line Status Address Register */
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#define IRCC_LSAR 0x03
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#define IRCC_LSAR_ADDRESS_MASK 0x07
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/* Line Control Register A */
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#define IRCC_LCR_A 0x04
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#define IRCC_LCR_A_FIFO_RESET 0x80
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#define IRCC_LCR_A_FAST 0x40
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#define IRCC_LCR_A_GP_DATA 0x20
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#define IRCC_LCR_A_RAW_TX 0x10
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#define IRCC_LCR_A_RAW_RX 0x08
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#define IRCC_LCR_A_ABORT 0x04
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#define IRCC_LCR_A_DATA_DONE 0x02
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/* Line Control Register B */
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#define IRCC_LCR_B 0x05
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#define IRCC_LCR_B_SCE_DISABLED 0x00
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#define IRCC_LCR_B_SCE_TRANSMIT 0x40
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#define IRCC_LCR_B_SCE_RECEIVE 0x80
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#define IRCC_LCR_B_SCE_UNDEFINED 0xc0
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#define IRCC_LCR_B_SIP_ENABLE 0x20
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#define IRCC_LCR_B_BRICK_WALL 0x10
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/* Bus Status Register */
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#define IRCC_BSR 0x06
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#define IRCC_BSR_NOT_EMPTY 0x80
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#define IRCC_BSR_FIFO_FULL 0x40
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#define IRCC_BSR_TIMEOUT 0x20
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/* Register block 1 */
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#define IRCC_FIFO_THRESHOLD 0x02
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#define IRCC_SCE_CFGA 0x00
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#define IRCC_CFGA_AUX_IR 0x80
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#define IRCC_CFGA_HALF_DUPLEX 0x04
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#define IRCC_CFGA_TX_POLARITY 0x02
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#define IRCC_CFGA_RX_POLARITY 0x01
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#define IRCC_CFGA_COM 0x00
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#define IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK 0x87
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#define IRCC_CFGA_IRDA_SIR_A 0x08
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#define IRCC_CFGA_ASK_SIR 0x10
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#define IRCC_CFGA_IRDA_SIR_B 0x18
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#define IRCC_CFGA_IRDA_HDLC 0x20
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#define IRCC_CFGA_IRDA_4PPM 0x28
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#define IRCC_CFGA_CONSUMER 0x30
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#define IRCC_CFGA_RAW_IR 0x38
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#define IRCC_CFGA_OTHER 0x40
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#define IRCC_IR_HDLC 0x04
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#define IRCC_IR_4PPM 0x01
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#define IRCC_IR_CONSUMER 0x02
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#define IRCC_SCE_CFGB 0x01
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#define IRCC_CFGB_LOOPBACK 0x20
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#define IRCC_CFGB_LPBCK_TX_CRC 0x10
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#define IRCC_CFGB_NOWAIT 0x08
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#define IRCC_CFGB_STRING_MOVE 0x04
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#define IRCC_CFGB_DMA_BURST 0x02
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#define IRCC_CFGB_DMA_ENABLE 0x01
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#define IRCC_CFGB_MUX_COM 0x00
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#define IRCC_CFGB_MUX_IR 0x40
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#define IRCC_CFGB_MUX_AUX 0x80
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#define IRCC_CFGB_MUX_INACTIVE 0xc0
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/* Register block 3 - Identification Registers! */
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#define IRCC_ID_HIGH 0x00 /* 0x10 */
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#define IRCC_ID_LOW 0x01 /* 0xB8 */
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#define IRCC_CHIP_ID 0x02 /* 0xF1 */
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#define IRCC_VERSION 0x03 /* 0x01 */
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#define IRCC_INTERFACE 0x04 /* low 4 = DMA, high 4 = IRQ */
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#define IRCC_INTERFACE_DMA_MASK 0x0F /* low 4 = DMA, high 4 = IRQ */
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#define IRCC_INTERFACE_IRQ_MASK 0xF0 /* low 4 = DMA, high 4 = IRQ */
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/* Register block 4 - IrDA */
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#define IRCC_CONTROL 0x00
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#define IRCC_BOF_COUNT_LO 0x01 /* Low byte */
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#define IRCC_BOF_COUNT_HI 0x00 /* High nibble (bit 0-3) */
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#define IRCC_BRICKWALL_CNT_LO 0x02 /* Low byte */
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#define IRCC_BRICKWALL_CNT_HI 0x03 /* High nibble (bit 4-7) */
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#define IRCC_TX_SIZE_LO 0x04 /* Low byte */
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#define IRCC_TX_SIZE_HI 0x03 /* High nibble (bit 0-3) */
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#define IRCC_RX_SIZE_HI 0x05 /* High nibble (bit 0-3) */
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#define IRCC_RX_SIZE_LO 0x06 /* Low byte */
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#define IRCC_1152 0x80
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#define IRCC_CRC 0x40
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/* Register block 5 - IrDA */
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#define IRCC_ATC 0x00
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#define IRCC_ATC_nPROGREADY 0x80
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#define IRCC_ATC_SPEED 0x40
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#define IRCC_ATC_ENABLE 0x20
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#define IRCC_ATC_MASK 0xE0
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#define IRCC_IRHALFDUPLEX_TIMEOUT 0x01
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#define IRCC_SCE_TX_DELAY_TIMER 0x02
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/*
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* Other definitions
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*/
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#define SMSC_IRCC2_MAX_SIR_SPEED 115200
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#define SMSC_IRCC2_FIR_CHIP_IO_EXTENT 8
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#define SMSC_IRCC2_SIR_CHIP_IO_EXTENT 8
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#define SMSC_IRCC2_FIFO_SIZE 16
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#define SMSC_IRCC2_FIFO_THRESHOLD 64
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/* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
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#define SMSC_IRCC2_RX_BUFF_TRUESIZE 14384
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#define SMSC_IRCC2_TX_BUFF_TRUESIZE 14384
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#define SMSC_IRCC2_MIN_TURN_TIME 0x07
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#define SMSC_IRCC2_WINDOW_SIZE 0x07
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/* Maximum wait for hw transmitter to finish */
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#define SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US 1000 /* 1 ms */
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/* Maximum wait for ATC transceiver programming to finish */
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#define SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES 1
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#endif /* SMSC_IRCC2_H */
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