538 строки
13 KiB
C
538 строки
13 KiB
C
#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/timer.h>
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#include <linux/acpi_pmtmr.h>
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#include <linux/cpufreq.h>
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#include <linux/dmi.h>
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#include <linux/delay.h>
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#include <linux/clocksource.h>
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#include <linux/percpu.h>
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#include <asm/hpet.h>
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#include <asm/timer.h>
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#include <asm/vgtod.h>
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#include <asm/time.h>
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#include <asm/delay.h>
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unsigned int cpu_khz; /* TSC clocks / usec, not used here */
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EXPORT_SYMBOL(cpu_khz);
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unsigned int tsc_khz;
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EXPORT_SYMBOL(tsc_khz);
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/*
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* TSC can be unstable due to cpufreq or due to unsynced TSCs
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*/
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static int tsc_unstable;
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/* native_sched_clock() is called before tsc_init(), so
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we must start with the TSC soft disabled to prevent
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erroneous rdtsc usage on !cpu_has_tsc processors */
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static int tsc_disabled = -1;
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/*
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* Scheduler clock - returns current time in nanosec units.
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*/
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u64 native_sched_clock(void)
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{
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u64 this_offset;
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/*
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* Fall back to jiffies if there's no TSC available:
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* ( But note that we still use it if the TSC is marked
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* unstable. We do this because unlike Time Of Day,
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* the scheduler clock tolerates small errors and it's
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* very important for it to be as fast as the platform
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* can achive it. )
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*/
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if (unlikely(tsc_disabled)) {
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/* No locking but a rare wrong value is not a big deal: */
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return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
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}
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/* read the Time Stamp Counter: */
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rdtscll(this_offset);
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/* return the value in ns */
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return cycles_2_ns(this_offset);
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}
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/* We need to define a real function for sched_clock, to override the
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weak default version */
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#ifdef CONFIG_PARAVIRT
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unsigned long long sched_clock(void)
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{
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return paravirt_sched_clock();
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}
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#else
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unsigned long long
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sched_clock(void) __attribute__((alias("native_sched_clock")));
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#endif
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int check_tsc_unstable(void)
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{
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return tsc_unstable;
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}
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EXPORT_SYMBOL_GPL(check_tsc_unstable);
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#ifdef CONFIG_X86_TSC
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int __init notsc_setup(char *str)
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{
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printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
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"cannot disable TSC completely.\n");
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tsc_disabled = 1;
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return 1;
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}
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#else
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/*
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* disable flag for tsc. Takes effect by clearing the TSC cpu flag
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* in cpu/common.c
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*/
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int __init notsc_setup(char *str)
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{
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setup_clear_cpu_cap(X86_FEATURE_TSC);
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return 1;
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}
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#endif
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__setup("notsc", notsc_setup);
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#define MAX_RETRIES 5
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#define SMI_TRESHOLD 50000
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/*
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* Read TSC and the reference counters. Take care of SMI disturbance
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*/
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static u64 __init tsc_read_refs(u64 *pm, u64 *hpet)
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{
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u64 t1, t2;
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int i;
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for (i = 0; i < MAX_RETRIES; i++) {
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t1 = get_cycles();
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if (hpet)
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*hpet = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
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else
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*pm = acpi_pm_read_early();
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t2 = get_cycles();
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if ((t2 - t1) < SMI_TRESHOLD)
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return t2;
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}
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return ULLONG_MAX;
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}
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/**
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* tsc_calibrate - calibrate the tsc on boot
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*/
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static unsigned int __init tsc_calibrate(void)
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{
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unsigned long flags;
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u64 tsc1, tsc2, tr1, tr2, delta, pm1, pm2, hpet1, hpet2;
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int hpet = is_hpet_enabled();
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unsigned int tsc_khz_val = 0;
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local_irq_save(flags);
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tsc1 = tsc_read_refs(&pm1, hpet ? &hpet1 : NULL);
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outb((inb(0x61) & ~0x02) | 0x01, 0x61);
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outb(0xb0, 0x43);
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outb((CLOCK_TICK_RATE / (1000 / 50)) & 0xff, 0x42);
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outb((CLOCK_TICK_RATE / (1000 / 50)) >> 8, 0x42);
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tr1 = get_cycles();
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while ((inb(0x61) & 0x20) == 0);
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tr2 = get_cycles();
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tsc2 = tsc_read_refs(&pm2, hpet ? &hpet2 : NULL);
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local_irq_restore(flags);
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/*
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* Preset the result with the raw and inaccurate PIT
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* calibration value
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*/
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delta = (tr2 - tr1);
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do_div(delta, 50);
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tsc_khz_val = delta;
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/* hpet or pmtimer available ? */
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if (!hpet && !pm1 && !pm2) {
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printk(KERN_INFO "TSC calibrated against PIT\n");
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goto out;
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}
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/* Check, whether the sampling was disturbed by an SMI */
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if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX) {
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printk(KERN_WARNING "TSC calibration disturbed by SMI, "
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"using PIT calibration result\n");
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goto out;
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}
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tsc2 = (tsc2 - tsc1) * 1000000LL;
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if (hpet) {
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printk(KERN_INFO "TSC calibrated against HPET\n");
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if (hpet2 < hpet1)
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hpet2 += 0x100000000ULL;
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hpet2 -= hpet1;
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tsc1 = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
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do_div(tsc1, 1000000);
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} else {
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printk(KERN_INFO "TSC calibrated against PM_TIMER\n");
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if (pm2 < pm1)
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pm2 += (u64)ACPI_PM_OVRRUN;
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pm2 -= pm1;
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tsc1 = pm2 * 1000000000LL;
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do_div(tsc1, PMTMR_TICKS_PER_SEC);
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}
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do_div(tsc2, tsc1);
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tsc_khz_val = tsc2;
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out:
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return tsc_khz_val;
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}
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unsigned long native_calculate_cpu_khz(void)
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{
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return tsc_calibrate();
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}
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#ifdef CONFIG_X86_32
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/* Only called from the Powernow K7 cpu freq driver */
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int recalibrate_cpu_khz(void)
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{
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#ifndef CONFIG_SMP
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unsigned long cpu_khz_old = cpu_khz;
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if (cpu_has_tsc) {
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cpu_khz = calculate_cpu_khz();
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tsc_khz = cpu_khz;
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cpu_data(0).loops_per_jiffy =
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cpufreq_scale(cpu_data(0).loops_per_jiffy,
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cpu_khz_old, cpu_khz);
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return 0;
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} else
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return -ENODEV;
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#else
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return -ENODEV;
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#endif
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}
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EXPORT_SYMBOL(recalibrate_cpu_khz);
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#endif /* CONFIG_X86_32 */
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/* Accelerators for sched_clock()
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* convert from cycles(64bits) => nanoseconds (64bits)
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* basic equation:
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* ns = cycles / (freq / ns_per_sec)
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* ns = cycles * (ns_per_sec / freq)
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* ns = cycles * (10^9 / (cpu_khz * 10^3))
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* ns = cycles * (10^6 / cpu_khz)
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*
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* Then we use scaling math (suggested by george@mvista.com) to get:
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* ns = cycles * (10^6 * SC / cpu_khz) / SC
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* ns = cycles * cyc2ns_scale / SC
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*
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* And since SC is a constant power of two, we can convert the div
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* into a shift.
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*
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* We can use khz divisor instead of mhz to keep a better precision, since
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* cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
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* (mathieu.desnoyers@polymtl.ca)
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*
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* -johnstul@us.ibm.com "math is hard, lets go shopping!"
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*/
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DEFINE_PER_CPU(unsigned long, cyc2ns);
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static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
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{
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unsigned long long tsc_now, ns_now;
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unsigned long flags, *scale;
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local_irq_save(flags);
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sched_clock_idle_sleep_event();
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scale = &per_cpu(cyc2ns, cpu);
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rdtscll(tsc_now);
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ns_now = __cycles_2_ns(tsc_now);
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if (cpu_khz)
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*scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
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sched_clock_idle_wakeup_event(0);
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local_irq_restore(flags);
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}
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#ifdef CONFIG_CPU_FREQ
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/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
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* changes.
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*
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* RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
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* not that important because current Opteron setups do not support
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* scaling on SMP anyroads.
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*
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* Should fix up last_tsc too. Currently gettimeofday in the
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* first tick after the change will be slightly wrong.
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*/
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static unsigned int ref_freq;
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static unsigned long loops_per_jiffy_ref;
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static unsigned long tsc_khz_ref;
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static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
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void *data)
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{
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struct cpufreq_freqs *freq = data;
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unsigned long *lpj, dummy;
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if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
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return 0;
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lpj = &dummy;
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if (!(freq->flags & CPUFREQ_CONST_LOOPS))
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#ifdef CONFIG_SMP
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lpj = &cpu_data(freq->cpu).loops_per_jiffy;
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#else
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lpj = &boot_cpu_data.loops_per_jiffy;
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#endif
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if (!ref_freq) {
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ref_freq = freq->old;
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loops_per_jiffy_ref = *lpj;
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tsc_khz_ref = tsc_khz;
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}
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if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
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(val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
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(val == CPUFREQ_RESUMECHANGE)) {
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*lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
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tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
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if (!(freq->flags & CPUFREQ_CONST_LOOPS))
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mark_tsc_unstable("cpufreq changes");
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}
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set_cyc2ns_scale(tsc_khz_ref, freq->cpu);
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return 0;
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}
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static struct notifier_block time_cpufreq_notifier_block = {
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.notifier_call = time_cpufreq_notifier
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};
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static int __init cpufreq_tsc(void)
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{
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cpufreq_register_notifier(&time_cpufreq_notifier_block,
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CPUFREQ_TRANSITION_NOTIFIER);
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return 0;
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}
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core_initcall(cpufreq_tsc);
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#endif /* CONFIG_CPU_FREQ */
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/* clocksource code */
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static struct clocksource clocksource_tsc;
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/*
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* We compare the TSC to the cycle_last value in the clocksource
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* structure to avoid a nasty time-warp. This can be observed in a
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* very small window right after one CPU updated cycle_last under
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* xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
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* is smaller than the cycle_last reference value due to a TSC which
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* is slighty behind. This delta is nowhere else observable, but in
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* that case it results in a forward time jump in the range of hours
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* due to the unsigned delta calculation of the time keeping core
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* code, which is necessary to support wrapping clocksources like pm
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* timer.
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*/
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static cycle_t read_tsc(void)
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{
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cycle_t ret = (cycle_t)get_cycles();
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return ret >= clocksource_tsc.cycle_last ?
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ret : clocksource_tsc.cycle_last;
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}
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static cycle_t __vsyscall_fn vread_tsc(void)
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{
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cycle_t ret = (cycle_t)vget_cycles();
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return ret >= __vsyscall_gtod_data.clock.cycle_last ?
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ret : __vsyscall_gtod_data.clock.cycle_last;
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}
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static struct clocksource clocksource_tsc = {
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.name = "tsc",
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.rating = 300,
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.read = read_tsc,
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.mask = CLOCKSOURCE_MASK(64),
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.shift = 22,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS |
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CLOCK_SOURCE_MUST_VERIFY,
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#ifdef CONFIG_X86_64
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.vread = vread_tsc,
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#endif
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};
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void mark_tsc_unstable(char *reason)
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{
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if (!tsc_unstable) {
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tsc_unstable = 1;
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printk("Marking TSC unstable due to %s\n", reason);
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/* Change only the rating, when not registered */
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if (clocksource_tsc.mult)
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clocksource_change_rating(&clocksource_tsc, 0);
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else
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clocksource_tsc.rating = 0;
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}
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}
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EXPORT_SYMBOL_GPL(mark_tsc_unstable);
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static int __init dmi_mark_tsc_unstable(const struct dmi_system_id *d)
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{
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printk(KERN_NOTICE "%s detected: marking TSC unstable.\n",
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d->ident);
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tsc_unstable = 1;
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return 0;
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}
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/* List of systems that have known TSC problems */
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static struct dmi_system_id __initdata bad_tsc_dmi_table[] = {
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{
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.callback = dmi_mark_tsc_unstable,
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.ident = "IBM Thinkpad 380XD",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
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DMI_MATCH(DMI_BOARD_NAME, "2635FA0"),
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},
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},
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{}
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};
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/*
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* Geode_LX - the OLPC CPU has a possibly a very reliable TSC
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*/
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#ifdef CONFIG_MGEODE_LX
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/* RTSC counts during suspend */
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#define RTSC_SUSP 0x100
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static void __init check_geode_tsc_reliable(void)
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{
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unsigned long res_low, res_high;
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rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
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if (res_low & RTSC_SUSP)
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clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
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}
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#else
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static inline void check_geode_tsc_reliable(void) { }
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#endif
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/*
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* Make an educated guess if the TSC is trustworthy and synchronized
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* over all CPUs.
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*/
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__cpuinit int unsynchronized_tsc(void)
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{
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if (!cpu_has_tsc || tsc_unstable)
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return 1;
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#ifdef CONFIG_SMP
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if (apic_is_clustered_box())
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return 1;
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#endif
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if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
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return 0;
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/*
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* Intel systems are normally all synchronized.
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* Exceptions must mark TSC as unstable:
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*/
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if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
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/* assume multi socket systems are not synchronized: */
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if (num_possible_cpus() > 1)
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tsc_unstable = 1;
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}
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return tsc_unstable;
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}
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static void __init init_tsc_clocksource(void)
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{
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clocksource_tsc.mult = clocksource_khz2mult(tsc_khz,
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clocksource_tsc.shift);
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/* lower the rating if we already know its unstable: */
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if (check_tsc_unstable()) {
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clocksource_tsc.rating = 0;
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clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
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}
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clocksource_register(&clocksource_tsc);
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}
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void __init tsc_init(void)
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{
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u64 lpj;
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int cpu;
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if (!cpu_has_tsc)
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return;
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cpu_khz = calculate_cpu_khz();
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tsc_khz = cpu_khz;
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if (!cpu_khz) {
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mark_tsc_unstable("could not calculate TSC khz");
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return;
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}
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#ifdef CONFIG_X86_64
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if (cpu_has(&boot_cpu_data, X86_FEATURE_CONSTANT_TSC) &&
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(boot_cpu_data.x86_vendor == X86_VENDOR_AMD))
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cpu_khz = calibrate_cpu();
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#endif
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lpj = ((u64)tsc_khz * 1000);
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do_div(lpj, HZ);
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lpj_fine = lpj;
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printk("Detected %lu.%03lu MHz processor.\n",
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(unsigned long)cpu_khz / 1000,
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(unsigned long)cpu_khz % 1000);
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/*
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* Secondary CPUs do not run through tsc_init(), so set up
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* all the scale factors for all CPUs, assuming the same
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* speed as the bootup CPU. (cpufreq notifiers will fix this
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* up if their speed diverges)
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*/
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for_each_possible_cpu(cpu)
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set_cyc2ns_scale(cpu_khz, cpu);
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if (tsc_disabled > 0)
|
|
return;
|
|
|
|
/* now allow native_sched_clock() to use rdtsc */
|
|
tsc_disabled = 0;
|
|
|
|
use_tsc_delay();
|
|
/* Check and install the TSC clocksource */
|
|
dmi_check_system(bad_tsc_dmi_table);
|
|
|
|
if (unsynchronized_tsc())
|
|
mark_tsc_unstable("TSCs unsynchronized");
|
|
|
|
check_geode_tsc_reliable();
|
|
init_tsc_clocksource();
|
|
}
|
|
|