600 строки
15 KiB
C
600 строки
15 KiB
C
/*
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* Copyright 2011 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "nouveau_drm.h"
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#include "nouveau_bios.h"
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#include "nouveau_pm.h"
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#include <subdev/bios/pll.h>
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#include <subdev/bios.h>
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#include <subdev/clock.h>
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#include <subdev/timer.h>
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#include <subdev/fb.h>
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static u32 read_div(struct drm_device *, int, u32, u32);
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static u32 read_pll(struct drm_device *, u32);
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static u32
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read_vco(struct drm_device *dev, u32 dsrc)
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{
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struct nouveau_device *device = nouveau_dev(dev);
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u32 ssrc = nv_rd32(device, dsrc);
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if (!(ssrc & 0x00000100))
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return read_pll(dev, 0x00e800);
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return read_pll(dev, 0x00e820);
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}
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static u32
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read_pll(struct drm_device *dev, u32 pll)
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{
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struct nouveau_device *device = nouveau_dev(dev);
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u32 ctrl = nv_rd32(device, pll + 0);
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u32 coef = nv_rd32(device, pll + 4);
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u32 P = (coef & 0x003f0000) >> 16;
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u32 N = (coef & 0x0000ff00) >> 8;
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u32 M = (coef & 0x000000ff) >> 0;
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u32 sclk, doff;
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if (!(ctrl & 0x00000001))
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return 0;
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switch (pll & 0xfff000) {
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case 0x00e000:
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sclk = 27000;
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P = 1;
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break;
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case 0x137000:
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doff = (pll - 0x137000) / 0x20;
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sclk = read_div(dev, doff, 0x137120, 0x137140);
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break;
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case 0x132000:
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switch (pll) {
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case 0x132000:
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sclk = read_pll(dev, 0x132020);
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break;
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case 0x132020:
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sclk = read_div(dev, 0, 0x137320, 0x137330);
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break;
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default:
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return 0;
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}
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break;
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default:
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return 0;
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}
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return sclk * N / M / P;
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}
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static u32
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read_div(struct drm_device *dev, int doff, u32 dsrc, u32 dctl)
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{
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struct nouveau_device *device = nouveau_dev(dev);
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u32 ssrc = nv_rd32(device, dsrc + (doff * 4));
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u32 sctl = nv_rd32(device, dctl + (doff * 4));
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switch (ssrc & 0x00000003) {
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case 0:
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if ((ssrc & 0x00030000) != 0x00030000)
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return 27000;
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return 108000;
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case 2:
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return 100000;
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case 3:
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if (sctl & 0x80000000) {
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u32 sclk = read_vco(dev, dsrc + (doff * 4));
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u32 sdiv = (sctl & 0x0000003f) + 2;
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return (sclk * 2) / sdiv;
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}
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return read_vco(dev, dsrc + (doff * 4));
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default:
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return 0;
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}
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}
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static u32
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read_mem(struct drm_device *dev)
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{
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struct nouveau_device *device = nouveau_dev(dev);
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u32 ssel = nv_rd32(device, 0x1373f0);
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if (ssel & 0x00000001)
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return read_div(dev, 0, 0x137300, 0x137310);
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return read_pll(dev, 0x132000);
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}
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static u32
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read_clk(struct drm_device *dev, int clk)
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{
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struct nouveau_device *device = nouveau_dev(dev);
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u32 sctl = nv_rd32(device, 0x137250 + (clk * 4));
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u32 ssel = nv_rd32(device, 0x137100);
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u32 sclk, sdiv;
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if (ssel & (1 << clk)) {
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if (clk < 7)
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sclk = read_pll(dev, 0x137000 + (clk * 0x20));
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else
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sclk = read_pll(dev, 0x1370e0);
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sdiv = ((sctl & 0x00003f00) >> 8) + 2;
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} else {
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sclk = read_div(dev, clk, 0x137160, 0x1371d0);
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sdiv = ((sctl & 0x0000003f) >> 0) + 2;
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}
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if (sctl & 0x80000000)
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return (sclk * 2) / sdiv;
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return sclk;
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}
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int
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nvc0_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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{
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perflvl->shader = read_clk(dev, 0x00);
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perflvl->core = perflvl->shader / 2;
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perflvl->memory = read_mem(dev);
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perflvl->rop = read_clk(dev, 0x01);
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perflvl->hub07 = read_clk(dev, 0x02);
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perflvl->hub06 = read_clk(dev, 0x07);
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perflvl->hub01 = read_clk(dev, 0x08);
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perflvl->copy = read_clk(dev, 0x09);
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perflvl->daemon = read_clk(dev, 0x0c);
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perflvl->vdec = read_clk(dev, 0x0e);
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return 0;
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}
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struct nvc0_pm_clock {
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u32 freq;
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u32 ssel;
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u32 mdiv;
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u32 dsrc;
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u32 ddiv;
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u32 coef;
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};
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struct nvc0_pm_state {
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struct nouveau_pm_level *perflvl;
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struct nvc0_pm_clock eng[16];
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struct nvc0_pm_clock mem;
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};
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static u32
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calc_div(struct drm_device *dev, int clk, u32 ref, u32 freq, u32 *ddiv)
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{
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u32 div = min((ref * 2) / freq, (u32)65);
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if (div < 2)
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div = 2;
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*ddiv = div - 2;
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return (ref * 2) / div;
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}
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static u32
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calc_src(struct drm_device *dev, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
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{
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u32 sclk;
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/* use one of the fixed frequencies if possible */
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*ddiv = 0x00000000;
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switch (freq) {
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case 27000:
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case 108000:
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*dsrc = 0x00000000;
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if (freq == 108000)
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*dsrc |= 0x00030000;
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return freq;
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case 100000:
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*dsrc = 0x00000002;
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return freq;
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default:
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*dsrc = 0x00000003;
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break;
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}
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/* otherwise, calculate the closest divider */
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sclk = read_vco(dev, clk);
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if (clk < 7)
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sclk = calc_div(dev, clk, sclk, freq, ddiv);
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return sclk;
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}
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static u32
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calc_pll(struct drm_device *dev, int clk, u32 freq, u32 *coef)
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{
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struct nouveau_device *device = nouveau_dev(dev);
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struct nouveau_bios *bios = nouveau_bios(device);
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struct nvbios_pll limits;
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int N, M, P, ret;
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ret = nvbios_pll_parse(bios, 0x137000 + (clk * 0x20), &limits);
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if (ret)
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return 0;
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limits.refclk = read_div(dev, clk, 0x137120, 0x137140);
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if (!limits.refclk)
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return 0;
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ret = nva3_calc_pll(dev, &limits, freq, &N, NULL, &M, &P);
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if (ret <= 0)
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return 0;
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*coef = (P << 16) | (N << 8) | M;
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return ret;
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}
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/* A (likely rather simplified and incomplete) view of the clock tree
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*
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* Key:
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*
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* S: source select
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* D: divider
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* P: pll
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* F: switch
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*
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* Engine clocks:
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*
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* 137250(D) ---- 137100(F0) ---- 137160(S)/1371d0(D) ------------------- ref
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* (F1) ---- 1370X0(P) ---- 137120(S)/137140(D) ---- ref
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*
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* Not all registers exist for all clocks. For example: clocks >= 8 don't
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* have their own PLL (all tied to clock 7's PLL when in PLL mode), nor do
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* they have the divider at 1371d0, though the source selection at 137160
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* still exists. You must use the divider at 137250 for these instead.
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*
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* Memory clock:
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*
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* TBD, read_mem() above is likely very wrong...
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*
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*/
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static int
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calc_clk(struct drm_device *dev, int clk, struct nvc0_pm_clock *info, u32 freq)
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{
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u32 src0, div0, div1D, div1P = 0;
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u32 clk0, clk1 = 0;
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/* invalid clock domain */
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if (!freq)
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return 0;
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/* first possible path, using only dividers */
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clk0 = calc_src(dev, clk, freq, &src0, &div0);
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clk0 = calc_div(dev, clk, clk0, freq, &div1D);
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/* see if we can get any closer using PLLs */
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if (clk0 != freq && (0x00004387 & (1 << clk))) {
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if (clk < 7)
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clk1 = calc_pll(dev, clk, freq, &info->coef);
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else
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clk1 = read_pll(dev, 0x1370e0);
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clk1 = calc_div(dev, clk, clk1, freq, &div1P);
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}
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/* select the method which gets closest to target freq */
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if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
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info->dsrc = src0;
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if (div0) {
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info->ddiv |= 0x80000000;
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info->ddiv |= div0 << 8;
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info->ddiv |= div0;
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}
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if (div1D) {
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info->mdiv |= 0x80000000;
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info->mdiv |= div1D;
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}
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info->ssel = 0;
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info->freq = clk0;
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} else {
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if (div1P) {
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info->mdiv |= 0x80000000;
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info->mdiv |= div1P << 8;
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}
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info->ssel = (1 << clk);
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info->freq = clk1;
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}
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return 0;
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}
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static int
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calc_mem(struct drm_device *dev, struct nvc0_pm_clock *info, u32 freq)
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{
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struct nouveau_device *device = nouveau_dev(dev);
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struct nouveau_bios *bios = nouveau_bios(device);
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struct nvbios_pll pll;
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int N, M, P, ret;
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u32 ctrl;
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/* mclk pll input freq comes from another pll, make sure it's on */
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ctrl = nv_rd32(device, 0x132020);
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if (!(ctrl & 0x00000001)) {
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/* if not, program it to 567MHz. nfi where this value comes
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* from - it looks like it's in the pll limits table for
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* 132000 but the binary driver ignores all my attempts to
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* change this value.
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*/
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nv_wr32(device, 0x137320, 0x00000103);
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nv_wr32(device, 0x137330, 0x81200606);
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nv_wait(device, 0x132020, 0x00010000, 0x00010000);
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nv_wr32(device, 0x132024, 0x0001150f);
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nv_mask(device, 0x132020, 0x00000001, 0x00000001);
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nv_wait(device, 0x137390, 0x00020000, 0x00020000);
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nv_mask(device, 0x132020, 0x00000004, 0x00000004);
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}
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/* for the moment, until the clock tree is better understood, use
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* pll mode for all clock frequencies
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*/
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ret = nvbios_pll_parse(bios, 0x132000, &pll);
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if (ret == 0) {
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pll.refclk = read_pll(dev, 0x132020);
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if (pll.refclk) {
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ret = nva3_calc_pll(dev, &pll, freq, &N, NULL, &M, &P);
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if (ret > 0) {
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info->coef = (P << 16) | (N << 8) | M;
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return 0;
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}
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}
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}
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return -EINVAL;
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}
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void *
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nvc0_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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{
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struct nouveau_device *device = nouveau_dev(dev);
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struct nvc0_pm_state *info;
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int ret;
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info = kzalloc(sizeof(*info), GFP_KERNEL);
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if (!info)
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return ERR_PTR(-ENOMEM);
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/* NFI why this is still in the performance table, the ROPCs appear
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* to get their clock from clock 2 ("hub07", actually hub05 on this
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* chip, but, anyway...) as well. nvatiming confirms hub05 and ROP
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* are always the same freq with the binary driver even when the
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* performance table says they should differ.
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*/
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if (device->chipset == 0xd9)
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perflvl->rop = 0;
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if ((ret = calc_clk(dev, 0x00, &info->eng[0x00], perflvl->shader)) ||
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(ret = calc_clk(dev, 0x01, &info->eng[0x01], perflvl->rop)) ||
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(ret = calc_clk(dev, 0x02, &info->eng[0x02], perflvl->hub07)) ||
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(ret = calc_clk(dev, 0x07, &info->eng[0x07], perflvl->hub06)) ||
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(ret = calc_clk(dev, 0x08, &info->eng[0x08], perflvl->hub01)) ||
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(ret = calc_clk(dev, 0x09, &info->eng[0x09], perflvl->copy)) ||
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(ret = calc_clk(dev, 0x0c, &info->eng[0x0c], perflvl->daemon)) ||
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(ret = calc_clk(dev, 0x0e, &info->eng[0x0e], perflvl->vdec))) {
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kfree(info);
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return ERR_PTR(ret);
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}
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if (perflvl->memory) {
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ret = calc_mem(dev, &info->mem, perflvl->memory);
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if (ret) {
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kfree(info);
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return ERR_PTR(ret);
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}
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}
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info->perflvl = perflvl;
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return info;
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}
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static void
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prog_clk(struct drm_device *dev, int clk, struct nvc0_pm_clock *info)
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{
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struct nouveau_device *device = nouveau_dev(dev);
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/* program dividers at 137160/1371d0 first */
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if (clk < 7 && !info->ssel) {
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nv_mask(device, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv);
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nv_wr32(device, 0x137160 + (clk * 0x04), info->dsrc);
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}
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/* switch clock to non-pll mode */
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nv_mask(device, 0x137100, (1 << clk), 0x00000000);
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nv_wait(device, 0x137100, (1 << clk), 0x00000000);
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/* reprogram pll */
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if (clk < 7) {
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/* make sure it's disabled first... */
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u32 base = 0x137000 + (clk * 0x20);
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u32 ctrl = nv_rd32(device, base + 0x00);
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if (ctrl & 0x00000001) {
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nv_mask(device, base + 0x00, 0x00000004, 0x00000000);
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nv_mask(device, base + 0x00, 0x00000001, 0x00000000);
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}
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/* program it to new values, if necessary */
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if (info->ssel) {
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nv_wr32(device, base + 0x04, info->coef);
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nv_mask(device, base + 0x00, 0x00000001, 0x00000001);
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nv_wait(device, base + 0x00, 0x00020000, 0x00020000);
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nv_mask(device, base + 0x00, 0x00020004, 0x00000004);
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}
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}
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/* select pll/non-pll mode, and program final clock divider */
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nv_mask(device, 0x137100, (1 << clk), info->ssel);
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nv_wait(device, 0x137100, (1 << clk), info->ssel);
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nv_mask(device, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv);
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}
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static void
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mclk_precharge(struct nouveau_mem_exec_func *exec)
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{
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}
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static void
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mclk_refresh(struct nouveau_mem_exec_func *exec)
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{
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}
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static void
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mclk_refresh_auto(struct nouveau_mem_exec_func *exec, bool enable)
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{
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struct nouveau_device *device = nouveau_dev(exec->dev);
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nv_wr32(device, 0x10f210, enable ? 0x80000000 : 0x00000000);
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}
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static void
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mclk_refresh_self(struct nouveau_mem_exec_func *exec, bool enable)
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{
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}
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static void
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mclk_wait(struct nouveau_mem_exec_func *exec, u32 nsec)
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{
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udelay((nsec + 500) / 1000);
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}
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static u32
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mclk_mrg(struct nouveau_mem_exec_func *exec, int mr)
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{
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struct nouveau_device *device = nouveau_dev(exec->dev);
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struct nouveau_fb *pfb = nouveau_fb(device);
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if (pfb->ram.type != NV_MEM_TYPE_GDDR5) {
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if (mr <= 1)
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return nv_rd32(device, 0x10f300 + ((mr - 0) * 4));
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return nv_rd32(device, 0x10f320 + ((mr - 2) * 4));
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} else {
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if (mr == 0)
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return nv_rd32(device, 0x10f300 + (mr * 4));
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else
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if (mr <= 7)
|
|
return nv_rd32(device, 0x10f32c + (mr * 4));
|
|
return nv_rd32(device, 0x10f34c);
|
|
}
|
|
}
|
|
|
|
static void
|
|
mclk_mrs(struct nouveau_mem_exec_func *exec, int mr, u32 data)
|
|
{
|
|
struct nouveau_device *device = nouveau_dev(exec->dev);
|
|
struct nouveau_fb *pfb = nouveau_fb(device);
|
|
if (pfb->ram.type != NV_MEM_TYPE_GDDR5) {
|
|
if (mr <= 1) {
|
|
nv_wr32(device, 0x10f300 + ((mr - 0) * 4), data);
|
|
if (pfb->ram.ranks > 1)
|
|
nv_wr32(device, 0x10f308 + ((mr - 0) * 4), data);
|
|
} else
|
|
if (mr <= 3) {
|
|
nv_wr32(device, 0x10f320 + ((mr - 2) * 4), data);
|
|
if (pfb->ram.ranks > 1)
|
|
nv_wr32(device, 0x10f328 + ((mr - 2) * 4), data);
|
|
}
|
|
} else {
|
|
if (mr == 0) nv_wr32(device, 0x10f300 + (mr * 4), data);
|
|
else if (mr <= 7) nv_wr32(device, 0x10f32c + (mr * 4), data);
|
|
else if (mr == 15) nv_wr32(device, 0x10f34c, data);
|
|
}
|
|
}
|
|
|
|
static void
|
|
mclk_clock_set(struct nouveau_mem_exec_func *exec)
|
|
{
|
|
struct nouveau_device *device = nouveau_dev(exec->dev);
|
|
struct nvc0_pm_state *info = exec->priv;
|
|
u32 ctrl = nv_rd32(device, 0x132000);
|
|
|
|
nv_wr32(device, 0x137360, 0x00000001);
|
|
nv_wr32(device, 0x137370, 0x00000000);
|
|
nv_wr32(device, 0x137380, 0x00000000);
|
|
if (ctrl & 0x00000001)
|
|
nv_wr32(device, 0x132000, (ctrl &= ~0x00000001));
|
|
|
|
nv_wr32(device, 0x132004, info->mem.coef);
|
|
nv_wr32(device, 0x132000, (ctrl |= 0x00000001));
|
|
nv_wait(device, 0x137390, 0x00000002, 0x00000002);
|
|
nv_wr32(device, 0x132018, 0x00005000);
|
|
|
|
nv_wr32(device, 0x137370, 0x00000001);
|
|
nv_wr32(device, 0x137380, 0x00000001);
|
|
nv_wr32(device, 0x137360, 0x00000000);
|
|
}
|
|
|
|
static void
|
|
mclk_timing_set(struct nouveau_mem_exec_func *exec)
|
|
{
|
|
struct nouveau_device *device = nouveau_dev(exec->dev);
|
|
struct nvc0_pm_state *info = exec->priv;
|
|
struct nouveau_pm_level *perflvl = info->perflvl;
|
|
int i;
|
|
|
|
for (i = 0; i < 5; i++)
|
|
nv_wr32(device, 0x10f290 + (i * 4), perflvl->timing.reg[i]);
|
|
}
|
|
|
|
static void
|
|
prog_mem(struct drm_device *dev, struct nvc0_pm_state *info)
|
|
{
|
|
struct nouveau_device *device = nouveau_dev(dev);
|
|
struct nouveau_mem_exec_func exec = {
|
|
.dev = dev,
|
|
.precharge = mclk_precharge,
|
|
.refresh = mclk_refresh,
|
|
.refresh_auto = mclk_refresh_auto,
|
|
.refresh_self = mclk_refresh_self,
|
|
.wait = mclk_wait,
|
|
.mrg = mclk_mrg,
|
|
.mrs = mclk_mrs,
|
|
.clock_set = mclk_clock_set,
|
|
.timing_set = mclk_timing_set,
|
|
.priv = info
|
|
};
|
|
|
|
if (device->chipset < 0xd0)
|
|
nv_wr32(device, 0x611200, 0x00003300);
|
|
else
|
|
nv_wr32(device, 0x62c000, 0x03030000);
|
|
|
|
nouveau_mem_exec(&exec, info->perflvl);
|
|
|
|
if (device->chipset < 0xd0)
|
|
nv_wr32(device, 0x611200, 0x00003330);
|
|
else
|
|
nv_wr32(device, 0x62c000, 0x03030300);
|
|
}
|
|
int
|
|
nvc0_pm_clocks_set(struct drm_device *dev, void *data)
|
|
{
|
|
struct nvc0_pm_state *info = data;
|
|
int i;
|
|
|
|
if (info->mem.coef)
|
|
prog_mem(dev, info);
|
|
|
|
for (i = 0; i < 16; i++) {
|
|
if (!info->eng[i].freq)
|
|
continue;
|
|
prog_clk(dev, i, &info->eng[i]);
|
|
}
|
|
|
|
kfree(info);
|
|
return 0;
|
|
}
|