986 строки
30 KiB
C
986 строки
30 KiB
C
/*
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This file is provided under a dual BSD/GPLv2 license. When using or
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redistributing this file, you may do so under either license.
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GPL LICENSE SUMMARY
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Copyright(c) 2014 Intel Corporation.
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This program is free software; you can redistribute it and/or modify
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it under the terms of version 2 of the GNU General Public License as
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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Contact Information:
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qat-linux@intel.com
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BSD LICENSE
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Copyright(c) 2014 Intel Corporation.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/crypto.h>
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#include <crypto/aead.h>
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#include <crypto/aes.h>
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#include <crypto/sha.h>
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#include <crypto/hash.h>
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#include <crypto/algapi.h>
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#include <crypto/authenc.h>
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#include <crypto/rng.h>
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#include <linux/dma-mapping.h>
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#include "adf_accel_devices.h"
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#include "adf_transport.h"
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#include "adf_common_drv.h"
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#include "qat_crypto.h"
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#include "icp_qat_hw.h"
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#include "icp_qat_fw.h"
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#include "icp_qat_fw_la.h"
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#define QAT_AES_HW_CONFIG_ENC(alg) \
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ICP_QAT_HW_CIPHER_CONFIG_BUILD(ICP_QAT_HW_CIPHER_CBC_MODE, alg, \
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ICP_QAT_HW_CIPHER_NO_CONVERT, \
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ICP_QAT_HW_CIPHER_ENCRYPT)
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#define QAT_AES_HW_CONFIG_DEC(alg) \
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ICP_QAT_HW_CIPHER_CONFIG_BUILD(ICP_QAT_HW_CIPHER_CBC_MODE, alg, \
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ICP_QAT_HW_CIPHER_KEY_CONVERT, \
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ICP_QAT_HW_CIPHER_DECRYPT)
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static atomic_t active_dev;
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struct qat_alg_buf {
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uint32_t len;
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uint32_t resrvd;
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uint64_t addr;
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} __packed;
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struct qat_alg_buf_list {
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uint64_t resrvd;
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uint32_t num_bufs;
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uint32_t num_mapped_bufs;
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struct qat_alg_buf bufers[];
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} __packed __aligned(64);
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/* Common content descriptor */
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struct qat_alg_cd {
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union {
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struct qat_enc { /* Encrypt content desc */
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struct icp_qat_hw_cipher_algo_blk cipher;
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struct icp_qat_hw_auth_algo_blk hash;
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} qat_enc_cd;
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struct qat_dec { /* Decrytp content desc */
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struct icp_qat_hw_auth_algo_blk hash;
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struct icp_qat_hw_cipher_algo_blk cipher;
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} qat_dec_cd;
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};
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} __aligned(64);
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#define MAX_AUTH_STATE_SIZE sizeof(struct icp_qat_hw_auth_algo_blk)
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struct qat_auth_state {
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uint8_t data[MAX_AUTH_STATE_SIZE + 64];
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} __aligned(64);
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struct qat_alg_session_ctx {
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struct qat_alg_cd *enc_cd;
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dma_addr_t enc_cd_paddr;
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struct qat_alg_cd *dec_cd;
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dma_addr_t dec_cd_paddr;
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struct icp_qat_fw_la_bulk_req enc_fw_req_tmpl;
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struct icp_qat_fw_la_bulk_req dec_fw_req_tmpl;
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struct qat_crypto_instance *inst;
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struct crypto_tfm *tfm;
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struct crypto_shash *hash_tfm;
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enum icp_qat_hw_auth_algo qat_hash_alg;
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uint8_t salt[AES_BLOCK_SIZE];
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spinlock_t lock; /* protects qat_alg_session_ctx struct */
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};
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static int get_current_node(void)
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{
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return cpu_data(current_thread_info()->cpu).phys_proc_id;
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}
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static int qat_get_inter_state_size(enum icp_qat_hw_auth_algo qat_hash_alg)
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{
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switch (qat_hash_alg) {
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case ICP_QAT_HW_AUTH_ALGO_SHA1:
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return ICP_QAT_HW_SHA1_STATE1_SZ;
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case ICP_QAT_HW_AUTH_ALGO_SHA256:
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return ICP_QAT_HW_SHA256_STATE1_SZ;
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case ICP_QAT_HW_AUTH_ALGO_SHA512:
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return ICP_QAT_HW_SHA512_STATE1_SZ;
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default:
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return -EFAULT;
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};
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return -EFAULT;
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}
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static int qat_alg_do_precomputes(struct icp_qat_hw_auth_algo_blk *hash,
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struct qat_alg_session_ctx *ctx,
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const uint8_t *auth_key,
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unsigned int auth_keylen)
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{
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struct qat_auth_state auth_state;
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SHASH_DESC_ON_STACK(shash, ctx->hash_tfm);
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struct sha1_state sha1;
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struct sha256_state sha256;
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struct sha512_state sha512;
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int block_size = crypto_shash_blocksize(ctx->hash_tfm);
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int digest_size = crypto_shash_digestsize(ctx->hash_tfm);
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uint8_t *ipad = auth_state.data;
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uint8_t *opad = ipad + block_size;
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__be32 *hash_state_out;
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__be64 *hash512_state_out;
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int i, offset;
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memset(auth_state.data, '\0', MAX_AUTH_STATE_SIZE + 64);
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shash->tfm = ctx->hash_tfm;
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shash->flags = 0x0;
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if (auth_keylen > block_size) {
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char buff[SHA512_BLOCK_SIZE];
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int ret = crypto_shash_digest(shash, auth_key,
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auth_keylen, buff);
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if (ret)
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return ret;
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memcpy(ipad, buff, digest_size);
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memcpy(opad, buff, digest_size);
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memset(ipad + digest_size, 0, block_size - digest_size);
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memset(opad + digest_size, 0, block_size - digest_size);
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} else {
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memcpy(ipad, auth_key, auth_keylen);
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memcpy(opad, auth_key, auth_keylen);
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memset(ipad + auth_keylen, 0, block_size - auth_keylen);
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memset(opad + auth_keylen, 0, block_size - auth_keylen);
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}
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for (i = 0; i < block_size; i++) {
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char *ipad_ptr = ipad + i;
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char *opad_ptr = opad + i;
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*ipad_ptr ^= 0x36;
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*opad_ptr ^= 0x5C;
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}
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if (crypto_shash_init(shash))
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return -EFAULT;
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if (crypto_shash_update(shash, ipad, block_size))
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return -EFAULT;
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hash_state_out = (__be32 *)hash->sha.state1;
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hash512_state_out = (__be64 *)hash_state_out;
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switch (ctx->qat_hash_alg) {
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case ICP_QAT_HW_AUTH_ALGO_SHA1:
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if (crypto_shash_export(shash, &sha1))
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return -EFAULT;
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for (i = 0; i < digest_size >> 2; i++, hash_state_out++)
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*hash_state_out = cpu_to_be32(*(sha1.state + i));
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break;
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case ICP_QAT_HW_AUTH_ALGO_SHA256:
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if (crypto_shash_export(shash, &sha256))
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return -EFAULT;
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for (i = 0; i < digest_size >> 2; i++, hash_state_out++)
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*hash_state_out = cpu_to_be32(*(sha256.state + i));
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break;
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case ICP_QAT_HW_AUTH_ALGO_SHA512:
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if (crypto_shash_export(shash, &sha512))
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return -EFAULT;
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for (i = 0; i < digest_size >> 3; i++, hash512_state_out++)
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*hash512_state_out = cpu_to_be64(*(sha512.state + i));
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break;
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default:
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return -EFAULT;
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}
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if (crypto_shash_init(shash))
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return -EFAULT;
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if (crypto_shash_update(shash, opad, block_size))
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return -EFAULT;
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offset = round_up(qat_get_inter_state_size(ctx->qat_hash_alg), 8);
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hash_state_out = (__be32 *)(hash->sha.state1 + offset);
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hash512_state_out = (__be64 *)hash_state_out;
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switch (ctx->qat_hash_alg) {
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case ICP_QAT_HW_AUTH_ALGO_SHA1:
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if (crypto_shash_export(shash, &sha1))
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return -EFAULT;
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for (i = 0; i < digest_size >> 2; i++, hash_state_out++)
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*hash_state_out = cpu_to_be32(*(sha1.state + i));
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break;
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case ICP_QAT_HW_AUTH_ALGO_SHA256:
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if (crypto_shash_export(shash, &sha256))
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return -EFAULT;
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for (i = 0; i < digest_size >> 2; i++, hash_state_out++)
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*hash_state_out = cpu_to_be32(*(sha256.state + i));
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break;
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case ICP_QAT_HW_AUTH_ALGO_SHA512:
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if (crypto_shash_export(shash, &sha512))
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return -EFAULT;
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for (i = 0; i < digest_size >> 3; i++, hash512_state_out++)
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*hash512_state_out = cpu_to_be64(*(sha512.state + i));
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break;
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default:
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return -EFAULT;
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}
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return 0;
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}
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static void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header)
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{
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header->hdr_flags =
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ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
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header->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_LA;
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header->comn_req_flags =
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ICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_CD_FLD_TYPE_64BIT_ADR,
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QAT_COMN_PTR_TYPE_SGL);
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ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(header->serv_specif_flags,
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ICP_QAT_FW_LA_DIGEST_IN_BUFFER);
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ICP_QAT_FW_LA_PARTIAL_SET(header->serv_specif_flags,
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ICP_QAT_FW_LA_PARTIAL_NONE);
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ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(header->serv_specif_flags,
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ICP_QAT_FW_CIPH_IV_16BYTE_DATA);
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ICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,
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ICP_QAT_FW_LA_NO_PROTO);
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ICP_QAT_FW_LA_UPDATE_STATE_SET(header->serv_specif_flags,
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ICP_QAT_FW_LA_NO_UPDATE_STATE);
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}
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static int qat_alg_init_enc_session(struct qat_alg_session_ctx *ctx,
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int alg, struct crypto_authenc_keys *keys)
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{
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struct crypto_aead *aead_tfm = __crypto_aead_cast(ctx->tfm);
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unsigned int digestsize = crypto_aead_crt(aead_tfm)->authsize;
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struct qat_enc *enc_ctx = &ctx->enc_cd->qat_enc_cd;
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struct icp_qat_hw_cipher_algo_blk *cipher = &enc_ctx->cipher;
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struct icp_qat_hw_auth_algo_blk *hash =
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(struct icp_qat_hw_auth_algo_blk *)((char *)enc_ctx +
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sizeof(struct icp_qat_hw_auth_setup) + keys->enckeylen);
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struct icp_qat_fw_la_bulk_req *req_tmpl = &ctx->enc_fw_req_tmpl;
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struct icp_qat_fw_comn_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
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struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
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void *ptr = &req_tmpl->cd_ctrl;
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struct icp_qat_fw_cipher_cd_ctrl_hdr *cipher_cd_ctrl = ptr;
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struct icp_qat_fw_auth_cd_ctrl_hdr *hash_cd_ctrl = ptr;
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/* CD setup */
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cipher->aes.cipher_config.val = QAT_AES_HW_CONFIG_ENC(alg);
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memcpy(cipher->aes.key, keys->enckey, keys->enckeylen);
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hash->sha.inner_setup.auth_config.config =
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ICP_QAT_HW_AUTH_CONFIG_BUILD(ICP_QAT_HW_AUTH_MODE1,
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ctx->qat_hash_alg, digestsize);
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hash->sha.inner_setup.auth_counter.counter =
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cpu_to_be32(crypto_shash_blocksize(ctx->hash_tfm));
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if (qat_alg_do_precomputes(hash, ctx, keys->authkey, keys->authkeylen))
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return -EFAULT;
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/* Request setup */
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qat_alg_init_common_hdr(header);
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header->service_cmd_id = ICP_QAT_FW_LA_CMD_CIPHER_HASH;
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ICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,
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ICP_QAT_FW_LA_RET_AUTH_RES);
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ICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,
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ICP_QAT_FW_LA_NO_CMP_AUTH_RES);
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cd_pars->u.s.content_desc_addr = ctx->enc_cd_paddr;
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cd_pars->u.s.content_desc_params_sz = sizeof(struct qat_alg_cd) >> 3;
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/* Cipher CD config setup */
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cipher_cd_ctrl->cipher_key_sz = keys->enckeylen >> 3;
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cipher_cd_ctrl->cipher_state_sz = AES_BLOCK_SIZE >> 3;
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cipher_cd_ctrl->cipher_cfg_offset = 0;
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ICP_QAT_FW_COMN_CURR_ID_SET(cipher_cd_ctrl, ICP_QAT_FW_SLICE_CIPHER);
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ICP_QAT_FW_COMN_NEXT_ID_SET(cipher_cd_ctrl, ICP_QAT_FW_SLICE_AUTH);
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/* Auth CD config setup */
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hash_cd_ctrl->hash_cfg_offset = ((char *)hash - (char *)cipher) >> 3;
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hash_cd_ctrl->hash_flags = ICP_QAT_FW_AUTH_HDR_FLAG_NO_NESTED;
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hash_cd_ctrl->inner_res_sz = digestsize;
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hash_cd_ctrl->final_sz = digestsize;
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switch (ctx->qat_hash_alg) {
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case ICP_QAT_HW_AUTH_ALGO_SHA1:
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hash_cd_ctrl->inner_state1_sz =
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round_up(ICP_QAT_HW_SHA1_STATE1_SZ, 8);
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hash_cd_ctrl->inner_state2_sz =
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round_up(ICP_QAT_HW_SHA1_STATE2_SZ, 8);
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break;
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case ICP_QAT_HW_AUTH_ALGO_SHA256:
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hash_cd_ctrl->inner_state1_sz = ICP_QAT_HW_SHA256_STATE1_SZ;
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hash_cd_ctrl->inner_state2_sz = ICP_QAT_HW_SHA256_STATE2_SZ;
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break;
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case ICP_QAT_HW_AUTH_ALGO_SHA512:
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hash_cd_ctrl->inner_state1_sz = ICP_QAT_HW_SHA512_STATE1_SZ;
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hash_cd_ctrl->inner_state2_sz = ICP_QAT_HW_SHA512_STATE2_SZ;
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break;
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default:
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break;
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}
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hash_cd_ctrl->inner_state2_offset = hash_cd_ctrl->hash_cfg_offset +
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((sizeof(struct icp_qat_hw_auth_setup) +
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round_up(hash_cd_ctrl->inner_state1_sz, 8)) >> 3);
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ICP_QAT_FW_COMN_CURR_ID_SET(hash_cd_ctrl, ICP_QAT_FW_SLICE_AUTH);
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ICP_QAT_FW_COMN_NEXT_ID_SET(hash_cd_ctrl, ICP_QAT_FW_SLICE_DRAM_WR);
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return 0;
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}
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static int qat_alg_init_dec_session(struct qat_alg_session_ctx *ctx,
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int alg, struct crypto_authenc_keys *keys)
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{
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struct crypto_aead *aead_tfm = __crypto_aead_cast(ctx->tfm);
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unsigned int digestsize = crypto_aead_crt(aead_tfm)->authsize;
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struct qat_dec *dec_ctx = &ctx->dec_cd->qat_dec_cd;
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struct icp_qat_hw_auth_algo_blk *hash = &dec_ctx->hash;
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struct icp_qat_hw_cipher_algo_blk *cipher =
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(struct icp_qat_hw_cipher_algo_blk *)((char *)dec_ctx +
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sizeof(struct icp_qat_hw_auth_setup) +
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roundup(crypto_shash_digestsize(ctx->hash_tfm), 8) * 2);
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struct icp_qat_fw_la_bulk_req *req_tmpl = &ctx->dec_fw_req_tmpl;
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struct icp_qat_fw_comn_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
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struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
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void *ptr = &req_tmpl->cd_ctrl;
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struct icp_qat_fw_cipher_cd_ctrl_hdr *cipher_cd_ctrl = ptr;
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struct icp_qat_fw_auth_cd_ctrl_hdr *hash_cd_ctrl = ptr;
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struct icp_qat_fw_la_auth_req_params *auth_param =
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(struct icp_qat_fw_la_auth_req_params *)
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((char *)&req_tmpl->serv_specif_rqpars +
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sizeof(struct icp_qat_fw_la_cipher_req_params));
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/* CD setup */
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cipher->aes.cipher_config.val = QAT_AES_HW_CONFIG_DEC(alg);
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memcpy(cipher->aes.key, keys->enckey, keys->enckeylen);
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hash->sha.inner_setup.auth_config.config =
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ICP_QAT_HW_AUTH_CONFIG_BUILD(ICP_QAT_HW_AUTH_MODE1,
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ctx->qat_hash_alg,
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digestsize);
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hash->sha.inner_setup.auth_counter.counter =
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cpu_to_be32(crypto_shash_blocksize(ctx->hash_tfm));
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if (qat_alg_do_precomputes(hash, ctx, keys->authkey, keys->authkeylen))
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return -EFAULT;
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/* Request setup */
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qat_alg_init_common_hdr(header);
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header->service_cmd_id = ICP_QAT_FW_LA_CMD_HASH_CIPHER;
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ICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,
|
|
ICP_QAT_FW_LA_NO_RET_AUTH_RES);
|
|
ICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,
|
|
ICP_QAT_FW_LA_CMP_AUTH_RES);
|
|
cd_pars->u.s.content_desc_addr = ctx->dec_cd_paddr;
|
|
cd_pars->u.s.content_desc_params_sz = sizeof(struct qat_alg_cd) >> 3;
|
|
|
|
/* Cipher CD config setup */
|
|
cipher_cd_ctrl->cipher_key_sz = keys->enckeylen >> 3;
|
|
cipher_cd_ctrl->cipher_state_sz = AES_BLOCK_SIZE >> 3;
|
|
cipher_cd_ctrl->cipher_cfg_offset =
|
|
(sizeof(struct icp_qat_hw_auth_setup) +
|
|
roundup(crypto_shash_digestsize(ctx->hash_tfm), 8) * 2) >> 3;
|
|
ICP_QAT_FW_COMN_CURR_ID_SET(cipher_cd_ctrl, ICP_QAT_FW_SLICE_CIPHER);
|
|
ICP_QAT_FW_COMN_NEXT_ID_SET(cipher_cd_ctrl, ICP_QAT_FW_SLICE_DRAM_WR);
|
|
|
|
/* Auth CD config setup */
|
|
hash_cd_ctrl->hash_cfg_offset = 0;
|
|
hash_cd_ctrl->hash_flags = ICP_QAT_FW_AUTH_HDR_FLAG_NO_NESTED;
|
|
hash_cd_ctrl->inner_res_sz = digestsize;
|
|
hash_cd_ctrl->final_sz = digestsize;
|
|
|
|
switch (ctx->qat_hash_alg) {
|
|
case ICP_QAT_HW_AUTH_ALGO_SHA1:
|
|
hash_cd_ctrl->inner_state1_sz =
|
|
round_up(ICP_QAT_HW_SHA1_STATE1_SZ, 8);
|
|
hash_cd_ctrl->inner_state2_sz =
|
|
round_up(ICP_QAT_HW_SHA1_STATE2_SZ, 8);
|
|
break;
|
|
case ICP_QAT_HW_AUTH_ALGO_SHA256:
|
|
hash_cd_ctrl->inner_state1_sz = ICP_QAT_HW_SHA256_STATE1_SZ;
|
|
hash_cd_ctrl->inner_state2_sz = ICP_QAT_HW_SHA256_STATE2_SZ;
|
|
break;
|
|
case ICP_QAT_HW_AUTH_ALGO_SHA512:
|
|
hash_cd_ctrl->inner_state1_sz = ICP_QAT_HW_SHA512_STATE1_SZ;
|
|
hash_cd_ctrl->inner_state2_sz = ICP_QAT_HW_SHA512_STATE2_SZ;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
hash_cd_ctrl->inner_state2_offset = hash_cd_ctrl->hash_cfg_offset +
|
|
((sizeof(struct icp_qat_hw_auth_setup) +
|
|
round_up(hash_cd_ctrl->inner_state1_sz, 8)) >> 3);
|
|
auth_param->auth_res_sz = digestsize;
|
|
ICP_QAT_FW_COMN_CURR_ID_SET(hash_cd_ctrl, ICP_QAT_FW_SLICE_AUTH);
|
|
ICP_QAT_FW_COMN_NEXT_ID_SET(hash_cd_ctrl, ICP_QAT_FW_SLICE_CIPHER);
|
|
return 0;
|
|
}
|
|
|
|
static int qat_alg_init_sessions(struct qat_alg_session_ctx *ctx,
|
|
const uint8_t *key, unsigned int keylen)
|
|
{
|
|
struct crypto_authenc_keys keys;
|
|
int alg;
|
|
|
|
if (crypto_rng_get_bytes(crypto_default_rng, ctx->salt, AES_BLOCK_SIZE))
|
|
return -EFAULT;
|
|
|
|
if (crypto_authenc_extractkeys(&keys, key, keylen))
|
|
goto bad_key;
|
|
|
|
switch (keys.enckeylen) {
|
|
case AES_KEYSIZE_128:
|
|
alg = ICP_QAT_HW_CIPHER_ALGO_AES128;
|
|
break;
|
|
case AES_KEYSIZE_192:
|
|
alg = ICP_QAT_HW_CIPHER_ALGO_AES192;
|
|
break;
|
|
case AES_KEYSIZE_256:
|
|
alg = ICP_QAT_HW_CIPHER_ALGO_AES256;
|
|
break;
|
|
default:
|
|
goto bad_key;
|
|
break;
|
|
}
|
|
|
|
if (qat_alg_init_enc_session(ctx, alg, &keys))
|
|
goto error;
|
|
|
|
if (qat_alg_init_dec_session(ctx, alg, &keys))
|
|
goto error;
|
|
|
|
return 0;
|
|
bad_key:
|
|
crypto_tfm_set_flags(ctx->tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
|
|
return -EINVAL;
|
|
error:
|
|
return -EFAULT;
|
|
}
|
|
|
|
static int qat_alg_setkey(struct crypto_aead *tfm, const uint8_t *key,
|
|
unsigned int keylen)
|
|
{
|
|
struct qat_alg_session_ctx *ctx = crypto_aead_ctx(tfm);
|
|
struct device *dev;
|
|
|
|
spin_lock(&ctx->lock);
|
|
if (ctx->enc_cd) {
|
|
/* rekeying */
|
|
dev = &GET_DEV(ctx->inst->accel_dev);
|
|
memset(ctx->enc_cd, 0, sizeof(struct qat_alg_cd));
|
|
memset(ctx->dec_cd, 0, sizeof(struct qat_alg_cd));
|
|
memset(&ctx->enc_fw_req_tmpl, 0,
|
|
sizeof(struct icp_qat_fw_la_bulk_req));
|
|
memset(&ctx->dec_fw_req_tmpl, 0,
|
|
sizeof(struct icp_qat_fw_la_bulk_req));
|
|
} else {
|
|
/* new key */
|
|
int node = get_current_node();
|
|
struct qat_crypto_instance *inst =
|
|
qat_crypto_get_instance_node(node);
|
|
if (!inst) {
|
|
spin_unlock(&ctx->lock);
|
|
return -EINVAL;
|
|
}
|
|
|
|
dev = &GET_DEV(inst->accel_dev);
|
|
ctx->inst = inst;
|
|
ctx->enc_cd = dma_zalloc_coherent(dev,
|
|
sizeof(struct qat_alg_cd),
|
|
&ctx->enc_cd_paddr,
|
|
GFP_ATOMIC);
|
|
if (!ctx->enc_cd) {
|
|
spin_unlock(&ctx->lock);
|
|
return -ENOMEM;
|
|
}
|
|
ctx->dec_cd = dma_zalloc_coherent(dev,
|
|
sizeof(struct qat_alg_cd),
|
|
&ctx->dec_cd_paddr,
|
|
GFP_ATOMIC);
|
|
if (!ctx->dec_cd) {
|
|
spin_unlock(&ctx->lock);
|
|
goto out_free_enc;
|
|
}
|
|
}
|
|
spin_unlock(&ctx->lock);
|
|
if (qat_alg_init_sessions(ctx, key, keylen))
|
|
goto out_free_all;
|
|
|
|
return 0;
|
|
|
|
out_free_all:
|
|
dma_free_coherent(dev, sizeof(struct qat_alg_cd),
|
|
ctx->dec_cd, ctx->dec_cd_paddr);
|
|
ctx->dec_cd = NULL;
|
|
out_free_enc:
|
|
dma_free_coherent(dev, sizeof(struct qat_alg_cd),
|
|
ctx->enc_cd, ctx->enc_cd_paddr);
|
|
ctx->enc_cd = NULL;
|
|
return -ENOMEM;
|
|
}
|
|
|
|
static void qat_alg_free_bufl(struct qat_crypto_instance *inst,
|
|
struct qat_crypto_request *qat_req)
|
|
{
|
|
struct device *dev = &GET_DEV(inst->accel_dev);
|
|
struct qat_alg_buf_list *bl = qat_req->buf.bl;
|
|
struct qat_alg_buf_list *blout = qat_req->buf.blout;
|
|
dma_addr_t blp = qat_req->buf.blp;
|
|
dma_addr_t blpout = qat_req->buf.bloutp;
|
|
size_t sz = qat_req->buf.sz;
|
|
int i, bufs = bl->num_bufs;
|
|
|
|
for (i = 0; i < bl->num_bufs; i++)
|
|
dma_unmap_single(dev, bl->bufers[i].addr,
|
|
bl->bufers[i].len, DMA_BIDIRECTIONAL);
|
|
|
|
dma_unmap_single(dev, blp, sz, DMA_TO_DEVICE);
|
|
kfree(bl);
|
|
if (blp != blpout) {
|
|
/* If out of place operation dma unmap only data */
|
|
int bufless = bufs - blout->num_mapped_bufs;
|
|
|
|
for (i = bufless; i < bufs; i++) {
|
|
dma_unmap_single(dev, blout->bufers[i].addr,
|
|
blout->bufers[i].len,
|
|
DMA_BIDIRECTIONAL);
|
|
}
|
|
dma_unmap_single(dev, blpout, sz, DMA_TO_DEVICE);
|
|
kfree(blout);
|
|
}
|
|
}
|
|
|
|
static int qat_alg_sgl_to_bufl(struct qat_crypto_instance *inst,
|
|
struct scatterlist *assoc,
|
|
struct scatterlist *sgl,
|
|
struct scatterlist *sglout, uint8_t *iv,
|
|
uint8_t ivlen,
|
|
struct qat_crypto_request *qat_req)
|
|
{
|
|
struct device *dev = &GET_DEV(inst->accel_dev);
|
|
int i, bufs = 0, n = sg_nents(sgl), assoc_n = sg_nents(assoc);
|
|
struct qat_alg_buf_list *bufl;
|
|
struct qat_alg_buf_list *buflout = NULL;
|
|
dma_addr_t blp;
|
|
dma_addr_t bloutp = 0;
|
|
struct scatterlist *sg;
|
|
size_t sz = sizeof(struct qat_alg_buf_list) +
|
|
((1 + n + assoc_n) * sizeof(struct qat_alg_buf));
|
|
|
|
if (unlikely(!n))
|
|
return -EINVAL;
|
|
|
|
bufl = kmalloc_node(sz, GFP_ATOMIC, inst->accel_dev->numa_node);
|
|
if (unlikely(!bufl))
|
|
return -ENOMEM;
|
|
|
|
blp = dma_map_single(dev, bufl, sz, DMA_TO_DEVICE);
|
|
if (unlikely(dma_mapping_error(dev, blp)))
|
|
goto err;
|
|
|
|
for_each_sg(assoc, sg, assoc_n, i) {
|
|
if (!sg->length)
|
|
continue;
|
|
bufl->bufers[bufs].addr = dma_map_single(dev,
|
|
sg_virt(sg),
|
|
sg->length,
|
|
DMA_BIDIRECTIONAL);
|
|
bufl->bufers[bufs].len = sg->length;
|
|
if (unlikely(dma_mapping_error(dev, bufl->bufers[bufs].addr)))
|
|
goto err;
|
|
bufs++;
|
|
}
|
|
bufl->bufers[bufs].addr = dma_map_single(dev, iv, ivlen,
|
|
DMA_BIDIRECTIONAL);
|
|
bufl->bufers[bufs].len = ivlen;
|
|
if (unlikely(dma_mapping_error(dev, bufl->bufers[bufs].addr)))
|
|
goto err;
|
|
bufs++;
|
|
|
|
for_each_sg(sgl, sg, n, i) {
|
|
int y = i + bufs;
|
|
|
|
bufl->bufers[y].addr = dma_map_single(dev, sg_virt(sg),
|
|
sg->length,
|
|
DMA_BIDIRECTIONAL);
|
|
bufl->bufers[y].len = sg->length;
|
|
if (unlikely(dma_mapping_error(dev, bufl->bufers[y].addr)))
|
|
goto err;
|
|
}
|
|
bufl->num_bufs = n + bufs;
|
|
qat_req->buf.bl = bufl;
|
|
qat_req->buf.blp = blp;
|
|
qat_req->buf.sz = sz;
|
|
/* Handle out of place operation */
|
|
if (sgl != sglout) {
|
|
struct qat_alg_buf *bufers;
|
|
|
|
buflout = kmalloc_node(sz, GFP_ATOMIC,
|
|
inst->accel_dev->numa_node);
|
|
if (unlikely(!buflout))
|
|
goto err;
|
|
bloutp = dma_map_single(dev, buflout, sz, DMA_TO_DEVICE);
|
|
if (unlikely(dma_mapping_error(dev, bloutp)))
|
|
goto err;
|
|
bufers = buflout->bufers;
|
|
/* For out of place operation dma map only data and
|
|
* reuse assoc mapping and iv */
|
|
for (i = 0; i < bufs; i++) {
|
|
bufers[i].len = bufl->bufers[i].len;
|
|
bufers[i].addr = bufl->bufers[i].addr;
|
|
}
|
|
for_each_sg(sglout, sg, n, i) {
|
|
int y = i + bufs;
|
|
|
|
bufers[y].addr = dma_map_single(dev, sg_virt(sg),
|
|
sg->length,
|
|
DMA_BIDIRECTIONAL);
|
|
buflout->bufers[y].len = sg->length;
|
|
if (unlikely(dma_mapping_error(dev, bufers[y].addr)))
|
|
goto err;
|
|
}
|
|
buflout->num_bufs = n + bufs;
|
|
buflout->num_mapped_bufs = n;
|
|
qat_req->buf.blout = buflout;
|
|
qat_req->buf.bloutp = bloutp;
|
|
} else {
|
|
/* Otherwise set the src and dst to the same address */
|
|
qat_req->buf.bloutp = qat_req->buf.blp;
|
|
}
|
|
return 0;
|
|
err:
|
|
dev_err(dev, "Failed to map buf for dma\n");
|
|
for_each_sg(sgl, sg, n + bufs, i) {
|
|
if (!dma_mapping_error(dev, bufl->bufers[i].addr)) {
|
|
dma_unmap_single(dev, bufl->bufers[i].addr,
|
|
bufl->bufers[i].len,
|
|
DMA_BIDIRECTIONAL);
|
|
}
|
|
}
|
|
if (!dma_mapping_error(dev, blp))
|
|
dma_unmap_single(dev, blp, sz, DMA_TO_DEVICE);
|
|
kfree(bufl);
|
|
if (sgl != sglout && buflout) {
|
|
for_each_sg(sglout, sg, n, i) {
|
|
int y = i + bufs;
|
|
|
|
if (!dma_mapping_error(dev, buflout->bufers[y].addr))
|
|
dma_unmap_single(dev, buflout->bufers[y].addr,
|
|
buflout->bufers[y].len,
|
|
DMA_BIDIRECTIONAL);
|
|
}
|
|
if (!dma_mapping_error(dev, bloutp))
|
|
dma_unmap_single(dev, bloutp, sz, DMA_TO_DEVICE);
|
|
kfree(buflout);
|
|
}
|
|
return -ENOMEM;
|
|
}
|
|
|
|
void qat_alg_callback(void *resp)
|
|
{
|
|
struct icp_qat_fw_la_resp *qat_resp = resp;
|
|
struct qat_crypto_request *qat_req =
|
|
(void *)(__force long)qat_resp->opaque_data;
|
|
struct qat_alg_session_ctx *ctx = qat_req->ctx;
|
|
struct qat_crypto_instance *inst = ctx->inst;
|
|
struct aead_request *areq = qat_req->areq;
|
|
uint8_t stat_filed = qat_resp->comn_resp.comn_status;
|
|
int res = 0, qat_res = ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(stat_filed);
|
|
|
|
qat_alg_free_bufl(inst, qat_req);
|
|
if (unlikely(qat_res != ICP_QAT_FW_COMN_STATUS_FLAG_OK))
|
|
res = -EBADMSG;
|
|
areq->base.complete(&areq->base, res);
|
|
}
|
|
|
|
static int qat_alg_dec(struct aead_request *areq)
|
|
{
|
|
struct crypto_aead *aead_tfm = crypto_aead_reqtfm(areq);
|
|
struct crypto_tfm *tfm = crypto_aead_tfm(aead_tfm);
|
|
struct qat_alg_session_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
struct qat_crypto_request *qat_req = aead_request_ctx(areq);
|
|
struct icp_qat_fw_la_cipher_req_params *cipher_param;
|
|
struct icp_qat_fw_la_auth_req_params *auth_param;
|
|
struct icp_qat_fw_la_bulk_req *msg;
|
|
int digst_size = crypto_aead_crt(aead_tfm)->authsize;
|
|
int ret, ctr = 0;
|
|
|
|
ret = qat_alg_sgl_to_bufl(ctx->inst, areq->assoc, areq->src, areq->dst,
|
|
areq->iv, AES_BLOCK_SIZE, qat_req);
|
|
if (unlikely(ret))
|
|
return ret;
|
|
|
|
msg = &qat_req->req;
|
|
*msg = ctx->dec_fw_req_tmpl;
|
|
qat_req->ctx = ctx;
|
|
qat_req->areq = areq;
|
|
qat_req->req.comn_mid.opaque_data = (uint64_t)(__force long)qat_req;
|
|
qat_req->req.comn_mid.src_data_addr = qat_req->buf.blp;
|
|
qat_req->req.comn_mid.dest_data_addr = qat_req->buf.bloutp;
|
|
cipher_param = (void *)&qat_req->req.serv_specif_rqpars;
|
|
cipher_param->cipher_length = areq->cryptlen - digst_size;
|
|
cipher_param->cipher_offset = areq->assoclen + AES_BLOCK_SIZE;
|
|
memcpy(cipher_param->u.cipher_IV_array, areq->iv, AES_BLOCK_SIZE);
|
|
auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
|
|
auth_param->auth_off = 0;
|
|
auth_param->auth_len = areq->assoclen +
|
|
cipher_param->cipher_length + AES_BLOCK_SIZE;
|
|
do {
|
|
ret = adf_send_message(ctx->inst->sym_tx, (uint32_t *)msg);
|
|
} while (ret == -EAGAIN && ctr++ < 10);
|
|
|
|
if (ret == -EAGAIN) {
|
|
qat_alg_free_bufl(ctx->inst, qat_req);
|
|
return -EBUSY;
|
|
}
|
|
return -EINPROGRESS;
|
|
}
|
|
|
|
static int qat_alg_enc_internal(struct aead_request *areq, uint8_t *iv,
|
|
int enc_iv)
|
|
{
|
|
struct crypto_aead *aead_tfm = crypto_aead_reqtfm(areq);
|
|
struct crypto_tfm *tfm = crypto_aead_tfm(aead_tfm);
|
|
struct qat_alg_session_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
struct qat_crypto_request *qat_req = aead_request_ctx(areq);
|
|
struct icp_qat_fw_la_cipher_req_params *cipher_param;
|
|
struct icp_qat_fw_la_auth_req_params *auth_param;
|
|
struct icp_qat_fw_la_bulk_req *msg;
|
|
int ret, ctr = 0;
|
|
|
|
ret = qat_alg_sgl_to_bufl(ctx->inst, areq->assoc, areq->src, areq->dst,
|
|
iv, AES_BLOCK_SIZE, qat_req);
|
|
if (unlikely(ret))
|
|
return ret;
|
|
|
|
msg = &qat_req->req;
|
|
*msg = ctx->enc_fw_req_tmpl;
|
|
qat_req->ctx = ctx;
|
|
qat_req->areq = areq;
|
|
qat_req->req.comn_mid.opaque_data = (uint64_t)(__force long)qat_req;
|
|
qat_req->req.comn_mid.src_data_addr = qat_req->buf.blp;
|
|
qat_req->req.comn_mid.dest_data_addr = qat_req->buf.bloutp;
|
|
cipher_param = (void *)&qat_req->req.serv_specif_rqpars;
|
|
auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
|
|
|
|
if (enc_iv) {
|
|
cipher_param->cipher_length = areq->cryptlen + AES_BLOCK_SIZE;
|
|
cipher_param->cipher_offset = areq->assoclen;
|
|
} else {
|
|
memcpy(cipher_param->u.cipher_IV_array, iv, AES_BLOCK_SIZE);
|
|
cipher_param->cipher_length = areq->cryptlen;
|
|
cipher_param->cipher_offset = areq->assoclen + AES_BLOCK_SIZE;
|
|
}
|
|
auth_param->auth_off = 0;
|
|
auth_param->auth_len = areq->assoclen + areq->cryptlen + AES_BLOCK_SIZE;
|
|
|
|
do {
|
|
ret = adf_send_message(ctx->inst->sym_tx, (uint32_t *)msg);
|
|
} while (ret == -EAGAIN && ctr++ < 10);
|
|
|
|
if (ret == -EAGAIN) {
|
|
qat_alg_free_bufl(ctx->inst, qat_req);
|
|
return -EBUSY;
|
|
}
|
|
return -EINPROGRESS;
|
|
}
|
|
|
|
static int qat_alg_enc(struct aead_request *areq)
|
|
{
|
|
return qat_alg_enc_internal(areq, areq->iv, 0);
|
|
}
|
|
|
|
static int qat_alg_genivenc(struct aead_givcrypt_request *req)
|
|
{
|
|
struct crypto_aead *aead_tfm = crypto_aead_reqtfm(&req->areq);
|
|
struct crypto_tfm *tfm = crypto_aead_tfm(aead_tfm);
|
|
struct qat_alg_session_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
__be64 seq;
|
|
|
|
memcpy(req->giv, ctx->salt, AES_BLOCK_SIZE);
|
|
seq = cpu_to_be64(req->seq);
|
|
memcpy(req->giv + AES_BLOCK_SIZE - sizeof(uint64_t),
|
|
&seq, sizeof(uint64_t));
|
|
return qat_alg_enc_internal(&req->areq, req->giv, 1);
|
|
}
|
|
|
|
static int qat_alg_init(struct crypto_tfm *tfm,
|
|
enum icp_qat_hw_auth_algo hash, const char *hash_name)
|
|
{
|
|
struct qat_alg_session_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
|
|
memset(ctx, '\0', sizeof(*ctx));
|
|
ctx->hash_tfm = crypto_alloc_shash(hash_name, 0, 0);
|
|
if (IS_ERR(ctx->hash_tfm))
|
|
return -EFAULT;
|
|
spin_lock_init(&ctx->lock);
|
|
ctx->qat_hash_alg = hash;
|
|
tfm->crt_aead.reqsize = sizeof(struct aead_request) +
|
|
sizeof(struct qat_crypto_request);
|
|
ctx->tfm = tfm;
|
|
return 0;
|
|
}
|
|
|
|
static int qat_alg_sha1_init(struct crypto_tfm *tfm)
|
|
{
|
|
return qat_alg_init(tfm, ICP_QAT_HW_AUTH_ALGO_SHA1, "sha1");
|
|
}
|
|
|
|
static int qat_alg_sha256_init(struct crypto_tfm *tfm)
|
|
{
|
|
return qat_alg_init(tfm, ICP_QAT_HW_AUTH_ALGO_SHA256, "sha256");
|
|
}
|
|
|
|
static int qat_alg_sha512_init(struct crypto_tfm *tfm)
|
|
{
|
|
return qat_alg_init(tfm, ICP_QAT_HW_AUTH_ALGO_SHA512, "sha512");
|
|
}
|
|
|
|
static void qat_alg_exit(struct crypto_tfm *tfm)
|
|
{
|
|
struct qat_alg_session_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
struct qat_crypto_instance *inst = ctx->inst;
|
|
struct device *dev;
|
|
|
|
if (!IS_ERR(ctx->hash_tfm))
|
|
crypto_free_shash(ctx->hash_tfm);
|
|
|
|
if (!inst)
|
|
return;
|
|
|
|
dev = &GET_DEV(inst->accel_dev);
|
|
if (ctx->enc_cd)
|
|
dma_free_coherent(dev, sizeof(struct qat_alg_cd),
|
|
ctx->enc_cd, ctx->enc_cd_paddr);
|
|
if (ctx->dec_cd)
|
|
dma_free_coherent(dev, sizeof(struct qat_alg_cd),
|
|
ctx->dec_cd, ctx->dec_cd_paddr);
|
|
qat_crypto_put_instance(inst);
|
|
}
|
|
|
|
static struct crypto_alg qat_algs[] = { {
|
|
.cra_name = "authenc(hmac(sha1),cbc(aes))",
|
|
.cra_driver_name = "qat_aes_cbc_hmac_sha1",
|
|
.cra_priority = 4001,
|
|
.cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct qat_alg_session_ctx),
|
|
.cra_alignmask = 0,
|
|
.cra_type = &crypto_aead_type,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_init = qat_alg_sha1_init,
|
|
.cra_exit = qat_alg_exit,
|
|
.cra_u = {
|
|
.aead = {
|
|
.setkey = qat_alg_setkey,
|
|
.decrypt = qat_alg_dec,
|
|
.encrypt = qat_alg_enc,
|
|
.givencrypt = qat_alg_genivenc,
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
.maxauthsize = SHA1_DIGEST_SIZE,
|
|
},
|
|
},
|
|
}, {
|
|
.cra_name = "authenc(hmac(sha256),cbc(aes))",
|
|
.cra_driver_name = "qat_aes_cbc_hmac_sha256",
|
|
.cra_priority = 4001,
|
|
.cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct qat_alg_session_ctx),
|
|
.cra_alignmask = 0,
|
|
.cra_type = &crypto_aead_type,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_init = qat_alg_sha256_init,
|
|
.cra_exit = qat_alg_exit,
|
|
.cra_u = {
|
|
.aead = {
|
|
.setkey = qat_alg_setkey,
|
|
.decrypt = qat_alg_dec,
|
|
.encrypt = qat_alg_enc,
|
|
.givencrypt = qat_alg_genivenc,
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
.maxauthsize = SHA256_DIGEST_SIZE,
|
|
},
|
|
},
|
|
}, {
|
|
.cra_name = "authenc(hmac(sha512),cbc(aes))",
|
|
.cra_driver_name = "qat_aes_cbc_hmac_sha512",
|
|
.cra_priority = 4001,
|
|
.cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct qat_alg_session_ctx),
|
|
.cra_alignmask = 0,
|
|
.cra_type = &crypto_aead_type,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_init = qat_alg_sha512_init,
|
|
.cra_exit = qat_alg_exit,
|
|
.cra_u = {
|
|
.aead = {
|
|
.setkey = qat_alg_setkey,
|
|
.decrypt = qat_alg_dec,
|
|
.encrypt = qat_alg_enc,
|
|
.givencrypt = qat_alg_genivenc,
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
.maxauthsize = SHA512_DIGEST_SIZE,
|
|
},
|
|
},
|
|
} };
|
|
|
|
int qat_algs_register(void)
|
|
{
|
|
if (atomic_add_return(1, &active_dev) == 1) {
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(qat_algs); i++)
|
|
qat_algs[i].cra_flags = CRYPTO_ALG_TYPE_AEAD |
|
|
CRYPTO_ALG_ASYNC;
|
|
return crypto_register_algs(qat_algs, ARRAY_SIZE(qat_algs));
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int qat_algs_unregister(void)
|
|
{
|
|
if (atomic_sub_return(1, &active_dev) == 0)
|
|
return crypto_unregister_algs(qat_algs, ARRAY_SIZE(qat_algs));
|
|
return 0;
|
|
}
|
|
|
|
int qat_algs_init(void)
|
|
{
|
|
atomic_set(&active_dev, 0);
|
|
crypto_get_default_rng();
|
|
return 0;
|
|
}
|
|
|
|
void qat_algs_exit(void)
|
|
{
|
|
crypto_put_default_rng();
|
|
}
|