Lin Huang 9dc486fdf6 clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399 ... Since hclk_sd and pclk_ddr source clock from CPLL or GPLL, and these two PLL may change their frequency. If we do not assign right id to pclk_ddr and hclk_sd, they will alway use default cur register value, and may get the frequency exceed their signed off frequency. So assign correct Id for them, then we can assign frequency for them in dts. Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>		2018-03-23 09:09:19 +01:00
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Makefile	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
clk-cpu.c	clk: rockchip: Remove superfluous error message in rockchip_clk_register_cpuclk()	2017-09-28 15:22:50 +02:00
clk-ddr.c	clk: rockchip: don't return NULL when failing to register ddrclk branch	2016-10-16 02:39:58 +02:00
clk-inverter.c	clk: rockchip: don't return NULL when registering inverter fails	2016-02-15 23:35:20 +01:00
clk-mmc-phase.c	clk: rockchip: Fix error return in phase clock registration	2018-03-23 09:08:43 +01:00
clk-muxgrf.c	clk: rockchip: add a clock-type for muxes based in the grf	2017-01-02 14:24:57 +01:00
clk-pll.c	clk: rockchip: add pll_wait_lock for pll_enable	2017-03-22 18:33:22 +01:00
clk-rk3036.c	clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036	2017-06-02 15:42:38 +02:00
clk-rk3128.c	clk: rockchip: add sclk_timer5 as critical clock on rk3128	2017-09-17 01:55:36 +02:00
clk-rk3188.c	clk: rockchip: use new cif/vdpu clock ids on rk3188	2017-10-14 21:32:11 +02:00
clk-rk3228.c	clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228	2018-03-23 08:49:35 +01:00
clk-rk3288.c	clk: rockchip: mark noc and some special clk as critical on rk3288	2017-06-02 15:54:20 +02:00
clk-rk3328.c	clk: rockchip: Fix wrong parents for MMC phase clock for rk3328	2018-03-23 08:58:19 +01:00
clk-rk3368.c	clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs	2017-10-14 21:31:58 +02:00
clk-rk3399.c	clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399	2018-03-23 09:09:19 +01:00
clk-rockchip.c	clk: rockchip: handle of_iomap failures in legacy clock driver	2016-08-23 18:00:25 +02:00
clk-rv1108.c	clk: rockchip: fix the rv1108 clk_mac sel register description	2017-08-22 02:55:03 +02:00
clk.c	clk: rockchip: Free the memory on the error path	2018-03-02 08:51:03 +01:00
clk.h	clk: rockchip: rename RK1108 to RV1108	2017-03-22 18:03:04 +01:00
softrst.c	clk: rockchip: Make reset_control_ops const	2016-03-29 16:29:46 -07:00