560 строки
14 KiB
C
560 строки
14 KiB
C
/*
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* linux/drivers/char/serial_core.h
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*
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef LINUX_SERIAL_CORE_H
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#define LINUX_SERIAL_CORE_H
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#include <linux/serial.h>
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/*
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* The type definitions. These are from Ted Ts'o's serial.h
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*/
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#define PORT_UNKNOWN 0
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#define PORT_8250 1
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#define PORT_16450 2
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#define PORT_16550 3
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#define PORT_16550A 4
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#define PORT_CIRRUS 5
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#define PORT_16650 6
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#define PORT_16650V2 7
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#define PORT_16750 8
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#define PORT_STARTECH 9
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#define PORT_16C950 10
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#define PORT_16654 11
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#define PORT_16850 12
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#define PORT_RSA 13
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#define PORT_NS16550A 14
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#define PORT_XSCALE 15
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#define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
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#define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
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#define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
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#define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
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#define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
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#define PORT_XR17D15X 21 /* Exar XR17D15x UART */
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#define PORT_MAX_8250 21 /* max port ID */
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/*
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* ARM specific type numbers. These are not currently guaranteed
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* to be implemented, and will change in the future. These are
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* separate so any additions to the old serial.c that occur before
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* we are merged can be easily merged here.
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*/
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#define PORT_PXA 31
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#define PORT_AMBA 32
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#define PORT_CLPS711X 33
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#define PORT_SA1100 34
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#define PORT_UART00 35
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#define PORT_21285 37
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/* Sparc type numbers. */
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#define PORT_SUNZILOG 38
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#define PORT_SUNSAB 39
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/* DEC */
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#define PORT_DZ 46
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#define PORT_ZS 47
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/* Parisc type numbers. */
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#define PORT_MUX 48
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/* Atmel AT91 / AT32 SoC */
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#define PORT_ATMEL 49
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/* Macintosh Zilog type numbers */
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#define PORT_MAC_ZILOG 50 /* m68k : not yet implemented */
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#define PORT_PMAC_ZILOG 51
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/* SH-SCI */
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#define PORT_SCI 52
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#define PORT_SCIF 53
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#define PORT_IRDA 54
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/* Samsung S3C2410 SoC and derivatives thereof */
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#define PORT_S3C2410 55
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/* SGI IP22 aka Indy / Challenge S / Indigo 2 */
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#define PORT_IP22ZILOG 56
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/* Sharp LH7a40x -- an ARM9 SoC series */
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#define PORT_LH7A40X 57
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/* PPC CPM type number */
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#define PORT_CPM 58
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/* MPC52xx (and MPC512x) type numbers */
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#define PORT_MPC52xx 59
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/* IBM icom */
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#define PORT_ICOM 60
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/* Samsung S3C2440 SoC */
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#define PORT_S3C2440 61
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/* Motorola i.MX SoC */
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#define PORT_IMX 62
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/* Marvell MPSC */
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#define PORT_MPSC 63
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/* TXX9 type number */
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#define PORT_TXX9 64
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/* NEC VR4100 series SIU/DSIU */
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#define PORT_VR41XX_SIU 65
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#define PORT_VR41XX_DSIU 66
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/* Samsung S3C2400 SoC */
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#define PORT_S3C2400 67
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/* M32R SIO */
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#define PORT_M32R_SIO 68
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/*Digi jsm */
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#define PORT_JSM 69
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#define PORT_PNX8XXX 70
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/* Hilscher netx */
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#define PORT_NETX 71
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/* SUN4V Hypervisor Console */
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#define PORT_SUNHV 72
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#define PORT_S3C2412 73
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/* Xilinx uartlite */
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#define PORT_UARTLITE 74
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/* Blackfin bf5xx */
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#define PORT_BFIN 75
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/* Micrel KS8695 */
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#define PORT_KS8695 76
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/* Broadcom SB1250, etc. SOC */
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#define PORT_SB1250_DUART 77
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/* Freescale ColdFire */
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#define PORT_MCF 78
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/* Blackfin SPORT */
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#define PORT_BFIN_SPORT 79
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/* MN10300 on-chip UART numbers */
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#define PORT_MN10300 80
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#define PORT_MN10300_CTS 81
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#define PORT_SC26XX 82
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/* SH-SCI */
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#define PORT_SCIFA 83
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#define PORT_S3C6400 84
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/* NWPSERIAL */
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#define PORT_NWPSERIAL 85
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/* MAX3100 */
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#define PORT_MAX3100 86
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/* Timberdale UART */
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#define PORT_TIMBUART 87
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/* Qualcomm MSM SoCs */
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#define PORT_MSM 88
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/* BCM63xx family SoCs */
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#define PORT_BCM63XX 89
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/* Aeroflex Gaisler GRLIB APBUART */
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#define PORT_APBUART 90
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/* Altera UARTs */
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#define PORT_ALTERA_JTAGUART 91
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#define PORT_ALTERA_UART 92
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/* SH-SCI */
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#define PORT_SCIFB 93
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/* MAX3107 */
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#define PORT_MAX3107 94
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/* High Speed UART for Medfield */
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#define PORT_MFD 95
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/* TI OMAP-UART */
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#define PORT_OMAP 96
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/* VIA VT8500 SoC */
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#define PORT_VT8500 97
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/* Xilinx PSS UART */
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#define PORT_XUARTPS 98
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/* Atheros AR933X SoC */
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#define PORT_AR933X 99
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/* Energy Micro efm32 SoC */
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#define PORT_EFMUART 100
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#ifdef __KERNEL__
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#include <linux/compiler.h>
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#include <linux/interrupt.h>
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#include <linux/circ_buf.h>
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#include <linux/spinlock.h>
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#include <linux/sched.h>
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#include <linux/tty.h>
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#include <linux/mutex.h>
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#include <linux/sysrq.h>
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#include <linux/pps_kernel.h>
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struct uart_port;
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struct serial_struct;
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struct device;
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/*
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* This structure describes all the operations that can be
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* done on the physical hardware.
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*/
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struct uart_ops {
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unsigned int (*tx_empty)(struct uart_port *);
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void (*set_mctrl)(struct uart_port *, unsigned int mctrl);
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unsigned int (*get_mctrl)(struct uart_port *);
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void (*stop_tx)(struct uart_port *);
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void (*start_tx)(struct uart_port *);
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void (*send_xchar)(struct uart_port *, char ch);
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void (*stop_rx)(struct uart_port *);
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void (*enable_ms)(struct uart_port *);
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void (*break_ctl)(struct uart_port *, int ctl);
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int (*startup)(struct uart_port *);
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void (*shutdown)(struct uart_port *);
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void (*flush_buffer)(struct uart_port *);
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void (*set_termios)(struct uart_port *, struct ktermios *new,
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struct ktermios *old);
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void (*set_ldisc)(struct uart_port *, int new);
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void (*pm)(struct uart_port *, unsigned int state,
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unsigned int oldstate);
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int (*set_wake)(struct uart_port *, unsigned int state);
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/*
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* Return a string describing the type of the port
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*/
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const char *(*type)(struct uart_port *);
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/*
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* Release IO and memory resources used by the port.
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* This includes iounmap if necessary.
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*/
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void (*release_port)(struct uart_port *);
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/*
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* Request IO and memory resources used by the port.
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* This includes iomapping the port if necessary.
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*/
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int (*request_port)(struct uart_port *);
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void (*config_port)(struct uart_port *, int);
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int (*verify_port)(struct uart_port *, struct serial_struct *);
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int (*ioctl)(struct uart_port *, unsigned int, unsigned long);
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#ifdef CONFIG_CONSOLE_POLL
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void (*poll_put_char)(struct uart_port *, unsigned char);
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int (*poll_get_char)(struct uart_port *);
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#endif
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};
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#define NO_POLL_CHAR 0x00ff0000
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#define UART_CONFIG_TYPE (1 << 0)
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#define UART_CONFIG_IRQ (1 << 1)
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struct uart_icount {
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__u32 cts;
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__u32 dsr;
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__u32 rng;
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__u32 dcd;
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__u32 rx;
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__u32 tx;
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__u32 frame;
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__u32 overrun;
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__u32 parity;
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__u32 brk;
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__u32 buf_overrun;
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};
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typedef unsigned int __bitwise__ upf_t;
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struct uart_port {
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spinlock_t lock; /* port lock */
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unsigned long iobase; /* in/out[bwl] */
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unsigned char __iomem *membase; /* read/write[bwl] */
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unsigned int (*serial_in)(struct uart_port *, int);
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void (*serial_out)(struct uart_port *, int, int);
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void (*set_termios)(struct uart_port *,
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struct ktermios *new,
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struct ktermios *old);
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int (*handle_irq)(struct uart_port *);
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void (*pm)(struct uart_port *, unsigned int state,
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unsigned int old);
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unsigned int irq; /* irq number */
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unsigned long irqflags; /* irq flags */
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unsigned int uartclk; /* base uart clock */
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unsigned int fifosize; /* tx fifo size */
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unsigned char x_char; /* xon/xoff char */
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unsigned char regshift; /* reg offset shift */
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unsigned char iotype; /* io access style */
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unsigned char unused1;
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#define UPIO_PORT (0)
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#define UPIO_HUB6 (1)
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#define UPIO_MEM (2)
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#define UPIO_MEM32 (3)
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#define UPIO_AU (4) /* Au1x00 type IO */
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#define UPIO_TSI (5) /* Tsi108/109 type IO */
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#define UPIO_RM9000 (6) /* RM9000 type IO */
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unsigned int read_status_mask; /* driver specific */
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unsigned int ignore_status_mask; /* driver specific */
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struct uart_state *state; /* pointer to parent state */
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struct uart_icount icount; /* statistics */
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struct console *cons; /* struct console, if any */
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#if defined(CONFIG_SERIAL_CORE_CONSOLE) || defined(SUPPORT_SYSRQ)
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unsigned long sysrq; /* sysrq timeout */
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#endif
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upf_t flags;
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#define UPF_FOURPORT ((__force upf_t) (1 << 1))
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#define UPF_SAK ((__force upf_t) (1 << 2))
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#define UPF_SPD_MASK ((__force upf_t) (0x1030))
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#define UPF_SPD_HI ((__force upf_t) (0x0010))
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#define UPF_SPD_VHI ((__force upf_t) (0x0020))
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#define UPF_SPD_CUST ((__force upf_t) (0x0030))
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#define UPF_SPD_SHI ((__force upf_t) (0x1000))
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#define UPF_SPD_WARP ((__force upf_t) (0x1010))
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#define UPF_SKIP_TEST ((__force upf_t) (1 << 6))
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#define UPF_AUTO_IRQ ((__force upf_t) (1 << 7))
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#define UPF_HARDPPS_CD ((__force upf_t) (1 << 11))
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#define UPF_LOW_LATENCY ((__force upf_t) (1 << 13))
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#define UPF_BUGGY_UART ((__force upf_t) (1 << 14))
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#define UPF_NO_TXEN_TEST ((__force upf_t) (1 << 15))
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#define UPF_MAGIC_MULTIPLIER ((__force upf_t) (1 << 16))
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#define UPF_CONS_FLOW ((__force upf_t) (1 << 23))
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#define UPF_SHARE_IRQ ((__force upf_t) (1 << 24))
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#define UPF_EXAR_EFR ((__force upf_t) (1 << 25))
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#define UPF_BUG_THRE ((__force upf_t) (1 << 26))
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/* The exact UART type is known and should not be probed. */
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#define UPF_FIXED_TYPE ((__force upf_t) (1 << 27))
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#define UPF_BOOT_AUTOCONF ((__force upf_t) (1 << 28))
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#define UPF_FIXED_PORT ((__force upf_t) (1 << 29))
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#define UPF_DEAD ((__force upf_t) (1 << 30))
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#define UPF_IOREMAP ((__force upf_t) (1 << 31))
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#define UPF_CHANGE_MASK ((__force upf_t) (0x17fff))
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#define UPF_USR_MASK ((__force upf_t) (UPF_SPD_MASK|UPF_LOW_LATENCY))
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unsigned int mctrl; /* current modem ctrl settings */
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unsigned int timeout; /* character-based timeout */
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unsigned int type; /* port type */
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const struct uart_ops *ops;
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unsigned int custom_divisor;
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unsigned int line; /* port index */
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resource_size_t mapbase; /* for ioremap */
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struct device *dev; /* parent device */
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unsigned char hub6; /* this should be in the 8250 driver */
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unsigned char suspended;
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unsigned char irq_wake;
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unsigned char unused[2];
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void *private_data; /* generic platform data pointer */
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};
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static inline int serial_port_in(struct uart_port *up, int offset)
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{
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return up->serial_in(up, offset);
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}
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static inline void serial_port_out(struct uart_port *up, int offset, int value)
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{
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up->serial_out(up, offset, value);
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}
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/*
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* This is the state information which is persistent across opens.
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*/
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struct uart_state {
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struct tty_port port;
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int pm_state;
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struct circ_buf xmit;
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struct uart_port *uart_port;
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};
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#define UART_XMIT_SIZE PAGE_SIZE
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/* number of characters left in xmit buffer before we ask for more */
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#define WAKEUP_CHARS 256
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struct module;
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struct tty_driver;
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struct uart_driver {
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struct module *owner;
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const char *driver_name;
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const char *dev_name;
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int major;
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int minor;
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int nr;
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struct console *cons;
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/*
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* these are private; the low level driver should not
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* touch these; they should be initialised to NULL
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*/
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struct uart_state *state;
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struct tty_driver *tty_driver;
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};
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void uart_write_wakeup(struct uart_port *port);
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/*
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* Baud rate helpers.
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*/
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void uart_update_timeout(struct uart_port *port, unsigned int cflag,
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unsigned int baud);
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unsigned int uart_get_baud_rate(struct uart_port *port, struct ktermios *termios,
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struct ktermios *old, unsigned int min,
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unsigned int max);
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unsigned int uart_get_divisor(struct uart_port *port, unsigned int baud);
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/* Base timer interval for polling */
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static inline int uart_poll_timeout(struct uart_port *port)
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{
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int timeout = port->timeout;
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return timeout > 6 ? (timeout / 2 - 2) : 1;
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}
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/*
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* Console helpers.
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*/
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struct uart_port *uart_get_console(struct uart_port *ports, int nr,
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struct console *c);
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void uart_parse_options(char *options, int *baud, int *parity, int *bits,
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int *flow);
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int uart_set_options(struct uart_port *port, struct console *co, int baud,
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int parity, int bits, int flow);
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struct tty_driver *uart_console_device(struct console *co, int *index);
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void uart_console_write(struct uart_port *port, const char *s,
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unsigned int count,
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void (*putchar)(struct uart_port *, int));
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/*
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* Port/driver registration/removal
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*/
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int uart_register_driver(struct uart_driver *uart);
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void uart_unregister_driver(struct uart_driver *uart);
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int uart_add_one_port(struct uart_driver *reg, struct uart_port *port);
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int uart_remove_one_port(struct uart_driver *reg, struct uart_port *port);
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int uart_match_port(struct uart_port *port1, struct uart_port *port2);
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/*
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* Power Management
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*/
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int uart_suspend_port(struct uart_driver *reg, struct uart_port *port);
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int uart_resume_port(struct uart_driver *reg, struct uart_port *port);
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#define uart_circ_empty(circ) ((circ)->head == (circ)->tail)
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#define uart_circ_clear(circ) ((circ)->head = (circ)->tail = 0)
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#define uart_circ_chars_pending(circ) \
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(CIRC_CNT((circ)->head, (circ)->tail, UART_XMIT_SIZE))
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#define uart_circ_chars_free(circ) \
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(CIRC_SPACE((circ)->head, (circ)->tail, UART_XMIT_SIZE))
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static inline int uart_tx_stopped(struct uart_port *port)
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{
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struct tty_struct *tty = port->state->port.tty;
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if(tty->stopped || tty->hw_stopped)
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return 1;
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return 0;
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}
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/*
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* The following are helper functions for the low level drivers.
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*/
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extern void uart_handle_dcd_change(struct uart_port *uport,
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unsigned int status);
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extern void uart_handle_cts_change(struct uart_port *uport,
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unsigned int status);
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extern void uart_insert_char(struct uart_port *port, unsigned int status,
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unsigned int overrun, unsigned int ch, unsigned int flag);
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#ifdef SUPPORT_SYSRQ
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static inline int
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uart_handle_sysrq_char(struct uart_port *port, unsigned int ch)
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{
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if (port->sysrq) {
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if (ch && time_before(jiffies, port->sysrq)) {
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handle_sysrq(ch);
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port->sysrq = 0;
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return 1;
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}
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port->sysrq = 0;
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}
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return 0;
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}
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#else
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#define uart_handle_sysrq_char(port,ch) ({ (void)port; 0; })
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#endif
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/*
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* We do the SysRQ and SAK checking like this...
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*/
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static inline int uart_handle_break(struct uart_port *port)
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{
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struct uart_state *state = port->state;
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#ifdef SUPPORT_SYSRQ
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if (port->cons && port->cons->index == port->line) {
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if (!port->sysrq) {
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port->sysrq = jiffies + HZ*5;
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return 1;
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}
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port->sysrq = 0;
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}
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#endif
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if (port->flags & UPF_SAK)
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do_SAK(state->port.tty);
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return 0;
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}
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/*
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* UART_ENABLE_MS - determine if port should enable modem status irqs
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*/
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#define UART_ENABLE_MS(port,cflag) ((port)->flags & UPF_HARDPPS_CD || \
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(cflag) & CRTSCTS || \
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!((cflag) & CLOCAL))
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#endif
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#endif /* LINUX_SERIAL_CORE_H */
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