606 строки
14 KiB
C
606 строки
14 KiB
C
/*******************************************************************************
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Intel(R) Gigabit Ethernet Linux driver
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Copyright(c) 2007 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#include <linux/if_ether.h>
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#include <linux/delay.h>
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#include "e1000_mac.h"
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#include "e1000_nvm.h"
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/**
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* e1000_raise_eec_clk - Raise EEPROM clock
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* @hw: pointer to the HW structure
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* @eecd: pointer to the EEPROM
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*
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* Enable/Raise the EEPROM clock bit.
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**/
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static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
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{
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*eecd = *eecd | E1000_EECD_SK;
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wr32(E1000_EECD, *eecd);
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wrfl();
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udelay(hw->nvm.delay_usec);
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}
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/**
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* e1000_lower_eec_clk - Lower EEPROM clock
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* @hw: pointer to the HW structure
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* @eecd: pointer to the EEPROM
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*
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* Clear/Lower the EEPROM clock bit.
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**/
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static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
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{
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*eecd = *eecd & ~E1000_EECD_SK;
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wr32(E1000_EECD, *eecd);
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wrfl();
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udelay(hw->nvm.delay_usec);
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}
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/**
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* e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
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* @hw: pointer to the HW structure
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* @data: data to send to the EEPROM
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* @count: number of bits to shift out
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*
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* We need to shift 'count' bits out to the EEPROM. So, the value in the
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* "data" parameter will be shifted out to the EEPROM one bit at a time.
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* In order to do this, "data" must be broken down into bits.
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**/
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static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
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{
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struct e1000_nvm_info *nvm = &hw->nvm;
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u32 eecd = rd32(E1000_EECD);
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u32 mask;
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mask = 0x01 << (count - 1);
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if (nvm->type == e1000_nvm_eeprom_microwire)
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eecd &= ~E1000_EECD_DO;
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else if (nvm->type == e1000_nvm_eeprom_spi)
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eecd |= E1000_EECD_DO;
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do {
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eecd &= ~E1000_EECD_DI;
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if (data & mask)
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eecd |= E1000_EECD_DI;
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wr32(E1000_EECD, eecd);
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wrfl();
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udelay(nvm->delay_usec);
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igb_raise_eec_clk(hw, &eecd);
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igb_lower_eec_clk(hw, &eecd);
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mask >>= 1;
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} while (mask);
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eecd &= ~E1000_EECD_DI;
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wr32(E1000_EECD, eecd);
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}
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/**
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* e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
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* @hw: pointer to the HW structure
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* @count: number of bits to shift in
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*
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* In order to read a register from the EEPROM, we need to shift 'count' bits
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* in from the EEPROM. Bits are "shifted in" by raising the clock input to
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* the EEPROM (setting the SK bit), and then reading the value of the data out
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* "DO" bit. During this "shifting in" process the data in "DI" bit should
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* always be clear.
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**/
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static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
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{
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u32 eecd;
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u32 i;
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u16 data;
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eecd = rd32(E1000_EECD);
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eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
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data = 0;
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for (i = 0; i < count; i++) {
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data <<= 1;
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igb_raise_eec_clk(hw, &eecd);
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eecd = rd32(E1000_EECD);
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eecd &= ~E1000_EECD_DI;
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if (eecd & E1000_EECD_DO)
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data |= 1;
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igb_lower_eec_clk(hw, &eecd);
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}
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return data;
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}
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/**
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* e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
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* @hw: pointer to the HW structure
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* @ee_reg: EEPROM flag for polling
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*
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* Polls the EEPROM status bit for either read or write completion based
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* upon the value of 'ee_reg'.
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**/
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static s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
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{
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u32 attempts = 100000;
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u32 i, reg = 0;
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s32 ret_val = -E1000_ERR_NVM;
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for (i = 0; i < attempts; i++) {
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if (ee_reg == E1000_NVM_POLL_READ)
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reg = rd32(E1000_EERD);
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else
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reg = rd32(E1000_EEWR);
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if (reg & E1000_NVM_RW_REG_DONE) {
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ret_val = 0;
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break;
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}
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udelay(5);
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}
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return ret_val;
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}
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/**
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* e1000_acquire_nvm - Generic request for access to EEPROM
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* @hw: pointer to the HW structure
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*
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* Set the EEPROM access request bit and wait for EEPROM access grant bit.
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* Return successful if access grant bit set, else clear the request for
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* EEPROM access and return -E1000_ERR_NVM (-1).
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**/
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s32 igb_acquire_nvm(struct e1000_hw *hw)
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{
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u32 eecd = rd32(E1000_EECD);
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s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
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s32 ret_val = 0;
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wr32(E1000_EECD, eecd | E1000_EECD_REQ);
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eecd = rd32(E1000_EECD);
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while (timeout) {
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if (eecd & E1000_EECD_GNT)
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break;
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udelay(5);
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eecd = rd32(E1000_EECD);
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timeout--;
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}
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if (!timeout) {
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eecd &= ~E1000_EECD_REQ;
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wr32(E1000_EECD, eecd);
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hw_dbg(hw, "Could not acquire NVM grant\n");
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ret_val = -E1000_ERR_NVM;
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}
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return ret_val;
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}
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/**
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* e1000_standby_nvm - Return EEPROM to standby state
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* @hw: pointer to the HW structure
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*
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* Return the EEPROM to a standby state.
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**/
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static void igb_standby_nvm(struct e1000_hw *hw)
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{
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struct e1000_nvm_info *nvm = &hw->nvm;
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u32 eecd = rd32(E1000_EECD);
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if (nvm->type == e1000_nvm_eeprom_microwire) {
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eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
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wr32(E1000_EECD, eecd);
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wrfl();
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udelay(nvm->delay_usec);
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igb_raise_eec_clk(hw, &eecd);
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/* Select EEPROM */
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eecd |= E1000_EECD_CS;
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wr32(E1000_EECD, eecd);
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wrfl();
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udelay(nvm->delay_usec);
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igb_lower_eec_clk(hw, &eecd);
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} else if (nvm->type == e1000_nvm_eeprom_spi) {
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/* Toggle CS to flush commands */
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eecd |= E1000_EECD_CS;
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wr32(E1000_EECD, eecd);
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wrfl();
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udelay(nvm->delay_usec);
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eecd &= ~E1000_EECD_CS;
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wr32(E1000_EECD, eecd);
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wrfl();
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udelay(nvm->delay_usec);
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}
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}
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/**
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* e1000_stop_nvm - Terminate EEPROM command
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* @hw: pointer to the HW structure
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*
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* Terminates the current command by inverting the EEPROM's chip select pin.
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**/
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static void e1000_stop_nvm(struct e1000_hw *hw)
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{
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u32 eecd;
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eecd = rd32(E1000_EECD);
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if (hw->nvm.type == e1000_nvm_eeprom_spi) {
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/* Pull CS high */
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eecd |= E1000_EECD_CS;
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igb_lower_eec_clk(hw, &eecd);
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} else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
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/* CS on Microcwire is active-high */
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eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
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wr32(E1000_EECD, eecd);
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igb_raise_eec_clk(hw, &eecd);
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igb_lower_eec_clk(hw, &eecd);
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}
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}
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/**
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* e1000_release_nvm - Release exclusive access to EEPROM
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* @hw: pointer to the HW structure
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*
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* Stop any current commands to the EEPROM and clear the EEPROM request bit.
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**/
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void igb_release_nvm(struct e1000_hw *hw)
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{
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u32 eecd;
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e1000_stop_nvm(hw);
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eecd = rd32(E1000_EECD);
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eecd &= ~E1000_EECD_REQ;
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wr32(E1000_EECD, eecd);
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}
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/**
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* e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
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* @hw: pointer to the HW structure
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*
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* Setups the EEPROM for reading and writing.
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**/
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static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw)
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{
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struct e1000_nvm_info *nvm = &hw->nvm;
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u32 eecd = rd32(E1000_EECD);
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s32 ret_val = 0;
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u16 timeout = 0;
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u8 spi_stat_reg;
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if (nvm->type == e1000_nvm_eeprom_microwire) {
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/* Clear SK and DI */
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eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
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wr32(E1000_EECD, eecd);
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/* Set CS */
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eecd |= E1000_EECD_CS;
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wr32(E1000_EECD, eecd);
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} else if (nvm->type == e1000_nvm_eeprom_spi) {
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/* Clear SK and CS */
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eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
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wr32(E1000_EECD, eecd);
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udelay(1);
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timeout = NVM_MAX_RETRY_SPI;
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/*
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* Read "Status Register" repeatedly until the LSB is cleared.
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* The EEPROM will signal that the command has been completed
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* by clearing bit 0 of the internal status register. If it's
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* not cleared within 'timeout', then error out.
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*/
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while (timeout) {
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igb_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
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hw->nvm.opcode_bits);
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spi_stat_reg = (u8)igb_shift_in_eec_bits(hw, 8);
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if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
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break;
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udelay(5);
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igb_standby_nvm(hw);
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timeout--;
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}
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if (!timeout) {
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hw_dbg(hw, "SPI NVM Status error\n");
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ret_val = -E1000_ERR_NVM;
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goto out;
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}
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}
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out:
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return ret_val;
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}
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/**
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* e1000_read_nvm_eerd - Reads EEPROM using EERD register
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* @hw: pointer to the HW structure
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* @offset: offset of word in the EEPROM to read
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* @words: number of words to read
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* @data: word read from the EEPROM
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*
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* Reads a 16 bit word from the EEPROM using the EERD register.
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**/
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s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
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{
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struct e1000_nvm_info *nvm = &hw->nvm;
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u32 i, eerd = 0;
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s32 ret_val = 0;
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/*
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* A check for invalid values: offset too large, too many words,
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* and not enough words.
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*/
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if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
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(words == 0)) {
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hw_dbg(hw, "nvm parameter(s) out of bounds\n");
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ret_val = -E1000_ERR_NVM;
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goto out;
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}
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for (i = 0; i < words; i++) {
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eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
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E1000_NVM_RW_REG_START;
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wr32(E1000_EERD, eerd);
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ret_val = igb_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
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if (ret_val)
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break;
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data[i] = (rd32(E1000_EERD) >>
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E1000_NVM_RW_REG_DATA);
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}
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out:
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return ret_val;
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}
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/**
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* e1000_write_nvm_spi - Write to EEPROM using SPI
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* @hw: pointer to the HW structure
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* @offset: offset within the EEPROM to be written to
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* @words: number of words to write
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* @data: 16 bit word(s) to be written to the EEPROM
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*
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* Writes data to EEPROM at offset using SPI interface.
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*
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* If e1000_update_nvm_checksum is not called after this function , the
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* EEPROM will most likley contain an invalid checksum.
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**/
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s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
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{
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struct e1000_nvm_info *nvm = &hw->nvm;
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s32 ret_val;
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u16 widx = 0;
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/*
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* A check for invalid values: offset too large, too many words,
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* and not enough words.
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*/
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if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
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(words == 0)) {
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hw_dbg(hw, "nvm parameter(s) out of bounds\n");
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ret_val = -E1000_ERR_NVM;
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goto out;
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}
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ret_val = hw->nvm.ops.acquire_nvm(hw);
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if (ret_val)
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goto out;
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msleep(10);
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while (widx < words) {
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u8 write_opcode = NVM_WRITE_OPCODE_SPI;
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ret_val = igb_ready_nvm_eeprom(hw);
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if (ret_val)
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goto release;
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igb_standby_nvm(hw);
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/* Send the WRITE ENABLE command (8 bit opcode) */
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igb_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
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nvm->opcode_bits);
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igb_standby_nvm(hw);
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/*
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* Some SPI eeproms use the 8th address bit embedded in the
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* opcode
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*/
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if ((nvm->address_bits == 8) && (offset >= 128))
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write_opcode |= NVM_A8_OPCODE_SPI;
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/* Send the Write command (8-bit opcode + addr) */
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igb_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
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igb_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
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nvm->address_bits);
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/* Loop to allow for up to whole page write of eeprom */
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while (widx < words) {
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u16 word_out = data[widx];
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word_out = (word_out >> 8) | (word_out << 8);
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igb_shift_out_eec_bits(hw, word_out, 16);
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widx++;
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if ((((offset + widx) * 2) % nvm->page_size) == 0) {
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igb_standby_nvm(hw);
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break;
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}
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}
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}
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msleep(10);
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release:
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hw->nvm.ops.release_nvm(hw);
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out:
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return ret_val;
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}
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/**
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* e1000_read_part_num - Read device part number
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* @hw: pointer to the HW structure
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* @part_num: pointer to device part number
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*
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* Reads the product board assembly (PBA) number from the EEPROM and stores
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* the value in part_num.
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**/
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s32 igb_read_part_num(struct e1000_hw *hw, u32 *part_num)
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{
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s32 ret_val;
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u16 nvm_data;
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ret_val = hw->nvm.ops.read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
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if (ret_val) {
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hw_dbg(hw, "NVM Read Error\n");
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goto out;
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}
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*part_num = (u32)(nvm_data << 16);
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ret_val = hw->nvm.ops.read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
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if (ret_val) {
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hw_dbg(hw, "NVM Read Error\n");
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goto out;
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}
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*part_num |= nvm_data;
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out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* e1000_read_mac_addr - Read device MAC address
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Reads the device MAC address from the EEPROM and stores the value.
|
|
* Since devices with two ports use the same EEPROM, we increment the
|
|
* last bit in the MAC address for the second port.
|
|
**/
|
|
s32 igb_read_mac_addr(struct e1000_hw *hw)
|
|
{
|
|
s32 ret_val = 0;
|
|
u16 offset, nvm_data, i;
|
|
|
|
for (i = 0; i < ETH_ALEN; i += 2) {
|
|
offset = i >> 1;
|
|
ret_val = hw->nvm.ops.read_nvm(hw, offset, 1, &nvm_data);
|
|
if (ret_val) {
|
|
hw_dbg(hw, "NVM Read Error\n");
|
|
goto out;
|
|
}
|
|
hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
|
|
hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
|
|
}
|
|
|
|
/* Flip last bit of mac address if we're on second port */
|
|
if (hw->bus.func == E1000_FUNC_1)
|
|
hw->mac.perm_addr[5] ^= 1;
|
|
|
|
for (i = 0; i < ETH_ALEN; i++)
|
|
hw->mac.addr[i] = hw->mac.perm_addr[i];
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* e1000_validate_nvm_checksum - Validate EEPROM checksum
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Calculates the EEPROM checksum by reading/adding each word of the EEPROM
|
|
* and then verifies that the sum of the EEPROM is equal to 0xBABA.
|
|
**/
|
|
s32 igb_validate_nvm_checksum(struct e1000_hw *hw)
|
|
{
|
|
s32 ret_val = 0;
|
|
u16 checksum = 0;
|
|
u16 i, nvm_data;
|
|
|
|
for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
|
|
ret_val = hw->nvm.ops.read_nvm(hw, i, 1, &nvm_data);
|
|
if (ret_val) {
|
|
hw_dbg(hw, "NVM Read Error\n");
|
|
goto out;
|
|
}
|
|
checksum += nvm_data;
|
|
}
|
|
|
|
if (checksum != (u16) NVM_SUM) {
|
|
hw_dbg(hw, "NVM Checksum Invalid\n");
|
|
ret_val = -E1000_ERR_NVM;
|
|
goto out;
|
|
}
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|
|
/**
|
|
* e1000_update_nvm_checksum - Update EEPROM checksum
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Updates the EEPROM checksum by reading/adding each word of the EEPROM
|
|
* up to the checksum. Then calculates the EEPROM checksum and writes the
|
|
* value to the EEPROM.
|
|
**/
|
|
s32 igb_update_nvm_checksum(struct e1000_hw *hw)
|
|
{
|
|
s32 ret_val;
|
|
u16 checksum = 0;
|
|
u16 i, nvm_data;
|
|
|
|
for (i = 0; i < NVM_CHECKSUM_REG; i++) {
|
|
ret_val = hw->nvm.ops.read_nvm(hw, i, 1, &nvm_data);
|
|
if (ret_val) {
|
|
hw_dbg(hw, "NVM Read Error while updating checksum.\n");
|
|
goto out;
|
|
}
|
|
checksum += nvm_data;
|
|
}
|
|
checksum = (u16) NVM_SUM - checksum;
|
|
ret_val = hw->nvm.ops.write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
|
|
if (ret_val)
|
|
hw_dbg(hw, "NVM Write Error while updating checksum.\n");
|
|
|
|
out:
|
|
return ret_val;
|
|
}
|
|
|