WSL2-Linux-Kernel/arch/x86/events/intel
Kan Liang b0380e1350 perf/x86/intel/lbr: Fix unchecked MSR access error on HSW
The fuzzer triggers the below trace.

[ 7763.384369] unchecked MSR access error: WRMSR to 0x689
(tried to write 0x1fffffff8101349e) at rIP: 0xffffffff810704a4
(native_write_msr+0x4/0x20)
[ 7763.397420] Call Trace:
[ 7763.399881]  <TASK>
[ 7763.401994]  intel_pmu_lbr_restore+0x9a/0x1f0
[ 7763.406363]  intel_pmu_lbr_sched_task+0x91/0x1c0
[ 7763.410992]  __perf_event_task_sched_in+0x1cd/0x240

On a machine with the LBR format LBR_FORMAT_EIP_FLAGS2, when the TSX is
disabled, a TSX quirk is required to access LBR from registers.
The lbr_from_signext_quirk_needed() is introduced to determine whether
the TSX quirk should be applied. However, the
lbr_from_signext_quirk_needed() is invoked before the
intel_pmu_lbr_init(), which parses the LBR format information. Without
the correct LBR format information, the TSX quirk never be applied.

Move the lbr_from_signext_quirk_needed() into the intel_pmu_lbr_init().
Checking x86_pmu.lbr_has_tsx in the lbr_from_signext_quirk_needed() is
not required anymore.

Both LBR_FORMAT_EIP_FLAGS2 and LBR_FORMAT_INFO have LBR_TSX flag, but
only the LBR_FORMAT_EIP_FLAGS2 requirs the quirk. Update the comments
accordingly.

Fixes: 1ac7fd8159 ("perf/x86/intel/lbr: Support LBR format V7")
Reported-by: Vince Weaver <vincent.weaver@maine.edu>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20220714182630.342107-1-kan.liang@linux.intel.com
2022-07-20 19:24:55 +02:00
..
Makefile perf/x86/intel/uncore: Parse uncore discovery tables 2021-04-02 10:04:54 +02:00
bts.c perf/x86: Add compiler barrier after updating BTS 2021-09-17 15:08:38 +02:00
core.c perf/x86/intel: Fix event constraints for ICL 2022-05-25 15:55:52 +02:00
cstate.c perf/x86/cstate: Add new Alder Lake and Raptor Lake support 2022-05-11 16:27:08 +02:00
ds.c perf/x86/intel: Enable PEBS format 5 2022-02-02 13:11:43 +01:00
knc.c License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
lbr.c perf/x86/intel/lbr: Fix unchecked MSR access error on HSW 2022-07-20 19:24:55 +02:00
p4.c Perf events changes in this cycle were: 2021-04-28 13:03:44 -07:00
p6.c x86/cpu: Rename cpu_data.x86_mask to cpu_data.x86_stepping 2018-02-15 01:15:52 +01:00
pt.c Changes for this cycle were: 2022-03-22 13:06:49 -07:00
pt.h perf/x86/intel/pt: Prevent redundant WRMSRs 2019-11-13 11:06:18 +01:00
uncore.c perf/x86/uncore: Add new Alder Lake and Raptor Lake support 2022-05-11 16:27:09 +02:00
uncore.h perf/x86/intel/uncore: Add IMC uncore support for ADL 2022-01-18 12:09:49 +01:00
uncore_discovery.c perf/x86/intel/uncore: Fix the build on !CONFIG_PHYS_ADDR_T_64BIT 2022-03-03 08:58:22 +01:00
uncore_discovery.h perf/x86/intel/uncore: Make uncore_discovery clean for 64 bit addresses 2022-03-01 16:19:01 +01:00
uncore_nhmex.c perf/x86/intel/uncore: Correct fixed counter index check for NHM 2018-05-31 12:36:28 +02:00
uncore_snb.c perf/x86/uncore: Add new Alder Lake and Raptor Lake support 2022-05-11 16:27:09 +02:00
uncore_snbep.c perf/x86/intel/uncore: Fix CAS_COUNT_WRITE issue for ICX 2022-01-18 12:09:48 +01:00