388 строки
8.8 KiB
Plaintext
388 строки
8.8 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* IPQ5332 device tree source
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*
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* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,apss-ipq.h>
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#include <dt-bindings/clock/qcom,ipq5332-gcc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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clocks {
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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xo_board: xo-board-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x2>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x3>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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L2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm-ipq5332", "qcom,scm";
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qcom,dload-mode = <&tcsr 0x6100>;
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};
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};
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memory@40000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the size */
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reg = <0x0 0x40000000 0x0 0x0>;
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};
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cpu_opp_table: opp-table-cpu {
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compatible = "operating-points-v2";
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opp-shared;
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opp-1488000000 {
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opp-hz = /bits/ 64 <1488000000>;
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clock-latency-ns = <200000>;
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};
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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tz_mem: tz@4a600000 {
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reg = <0x0 0x4a600000 0x0 0x200000>;
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no-map;
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};
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smem@4a800000 {
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compatible = "qcom,smem";
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reg = <0x0 0x4a800000 0x0 0x00100000>;
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no-map;
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hwlocks = <&tcsr_mutex 0>;
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};
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};
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soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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rng: rng@e3000 {
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compatible = "qcom,prng-ee";
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reg = <0x000e3000 0x1000>;
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clocks = <&gcc GCC_PRNG_AHB_CLK>;
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clock-names = "core";
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};
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq5332-tlmm";
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reg = <0x01000000 0x300000>;
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interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 53>;
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interrupt-controller;
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#interrupt-cells = <2>;
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serial_0_pins: serial0-state {
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pins = "gpio18", "gpio19";
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function = "blsp0_uart0";
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drive-strength = <8>;
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bias-pull-up;
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};
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};
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gcc: clock-controller@1800000 {
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compatible = "qcom,ipq5332-gcc";
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reg = <0x01800000 0x80000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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clocks = <&xo_board>,
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<&sleep_clk>,
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<0>,
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<0>,
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<0>;
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};
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tcsr_mutex: hwlock@1905000 {
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compatible = "qcom,tcsr-mutex";
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reg = <0x01905000 0x20000>;
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#hwlock-cells = <1>;
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};
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tcsr: syscon@1937000 {
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compatible = "qcom,tcsr-ipq5332", "syscon";
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reg = <0x01937000 0x21000>;
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};
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sdhc: mmc@7804000 {
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compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";
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reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
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interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC1_AHB_CLK>,
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<&gcc GCC_SDCC1_APPS_CLK>,
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<&xo_board>;
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clock-names = "iface", "core", "xo";
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status = "disabled";
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};
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blsp_dma: dma-controller@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x07884000 0x1d000>;
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interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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};
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blsp1_uart0: serial@78af000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x078af000 0x200>;
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interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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blsp1_spi0: spi@78b5000 {
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compatible = "qcom,spi-qup-v2.2.1";
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reg = <0x078b5000 0x600>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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dmas = <&blsp_dma 4>, <&blsp_dma 5>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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blsp1_i2c1: i2c@78b6000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x078b6000 0x600>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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dmas = <&blsp_dma 6>, <&blsp_dma 7>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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blsp1_spi2: spi@78b7000 {
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compatible = "qcom,spi-qup-v2.2.1";
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reg = <0x078b7000 0x600>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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dmas = <&blsp_dma 8>, <&blsp_dma 9>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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intc: interrupt-controller@b000000 {
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compatible = "qcom,msm-qgic2";
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reg = <0x0b000000 0x1000>, /* GICD */
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<0x0b002000 0x1000>, /* GICC */
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<0x0b001000 0x1000>, /* GICH */
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<0x0b004000 0x1000>; /* GICV */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0b00c000 0x3000>;
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v2m0: v2m@0 {
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compatible = "arm,gic-v2m-frame";
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reg = <0x00000000 0xffd>;
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msi-controller;
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};
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v2m1: v2m@1000 {
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compatible = "arm,gic-v2m-frame";
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reg = <0x00001000 0xffd>;
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msi-controller;
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};
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v2m2: v2m@2000 {
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compatible = "arm,gic-v2m-frame";
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reg = <0x00002000 0xffd>;
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msi-controller;
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};
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};
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watchdog: watchdog@b017000 {
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compatible = "qcom,apss-wdt-ipq5332", "qcom,kpss-wdt";
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reg = <0x0b017000 0x1000>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
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clocks = <&sleep_clk>;
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timeout-sec = <30>;
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};
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apcs_glb: mailbox@b111000 {
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compatible = "qcom,ipq5332-apcs-apps-global",
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"qcom,ipq6018-apcs-apps-global";
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reg = <0x0b111000 0x1000>;
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#clock-cells = <1>;
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clocks = <&a53pll>, <&xo_board>;
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clock-names = "pll", "xo";
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#mbox-cells = <1>;
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};
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a53pll: clock@b116000 {
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compatible = "qcom,ipq5332-a53pll";
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reg = <0x0b116000 0x40>;
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#clock-cells = <0>;
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clocks = <&xo_board>;
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clock-names = "xo";
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};
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timer@b120000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x0b120000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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frame@b120000 {
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reg = <0x0b121000 0x1000>,
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<0x0b122000 0x1000>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <0>;
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};
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frame@b123000 {
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reg = <0x0b123000 0x1000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <1>;
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status = "disabled";
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};
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frame@b124000 {
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reg = <0x0b124000 0x1000>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <2>;
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status = "disabled";
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};
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frame@b125000 {
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reg = <0x0b125000 0x1000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <3>;
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status = "disabled";
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};
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frame@b126000 {
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reg = <0x0b126000 0x1000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <4>;
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status = "disabled";
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};
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frame@b127000 {
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reg = <0x0b127000 0x1000>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <5>;
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status = "disabled";
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};
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frame@b128000 {
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reg = <0x0b128000 0x1000>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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frame-number = <6>;
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status = "disabled";
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};
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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};
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