865 строки
18 KiB
Plaintext
865 строки
18 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Google Gru (and derivatives) board device tree source
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*
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* Copyright 2016-2017 Google, Inc
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*/
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#include <dt-bindings/input/input.h>
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#include "rk3399.dtsi"
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#include "rk3399-op1-opp.dtsi"
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/ {
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aliases {
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mmc0 = &sdmmc;
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mmc1 = &sdhci;
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};
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chosen {
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stdout-path = "serial2:115200n8";
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};
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/*
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* Power Tree
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*
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* In general an attempt is made to include all rails called out by
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* the schematic as long as those rails interact in some way with
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* the AP. AKA:
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* - Rails that only connect to the EC (or devices that the EC talks to)
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* are not included.
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* - Rails _are_ included if the rails go to the AP even if the AP
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* doesn't currently care about them / they are always on. The idea
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* here is that it makes it easier to map to the schematic or extend
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* later.
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*
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* If two rails are substantially the same from the AP's point of
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* view, though, we won't create a full fixed regulator. We'll just
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* put the child rail as an alias of the parent rail. Sometimes rails
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* look the same to the AP because one of these is true:
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* - The EC controls the enable and the EC always enables a rail as
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* long as the AP is running.
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* - The rails are actually connected to each other by a jumper and
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* the distinction is just there to add clarity/flexibility to the
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* schematic.
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*/
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ppvar_sys: ppvar-sys {
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compatible = "regulator-fixed";
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regulator-name = "ppvar_sys";
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regulator-always-on;
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regulator-boot-on;
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};
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pp1200_lpddr: pp1200-lpddr {
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compatible = "regulator-fixed";
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regulator-name = "pp1200_lpddr";
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/* EC turns on w/ lpddr_pwr_en; always on for AP */
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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vin-supply = <&ppvar_sys>;
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};
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pp1800: pp1800 {
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compatible = "regulator-fixed";
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regulator-name = "pp1800";
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/* Always on when ppvar_sys shows power good */
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <&ppvar_sys>;
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};
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pp3300: pp3300 {
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compatible = "regulator-fixed";
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regulator-name = "pp3300";
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/* Always on; plain and simple */
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&ppvar_sys>;
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};
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pp5000: pp5000 {
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compatible = "regulator-fixed";
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regulator-name = "pp5000";
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/* EC turns on w/ pp5000_en; always on for AP */
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&ppvar_sys>;
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};
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ppvar_bigcpu_pwm: ppvar-bigcpu-pwm {
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compatible = "pwm-regulator";
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regulator-name = "ppvar_bigcpu_pwm";
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pwms = <&pwm1 0 3337 0>;
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pwm-supply = <&ppvar_sys>;
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pwm-dutycycle-range = <100 0>;
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pwm-dutycycle-unit = <100>;
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/* EC turns on w/ ap_core_en; always on for AP */
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <800107>;
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regulator-max-microvolt = <1302232>;
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};
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ppvar_bigcpu: ppvar-bigcpu {
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compatible = "vctrl-regulator";
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regulator-name = "ppvar_bigcpu";
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regulator-min-microvolt = <800107>;
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regulator-max-microvolt = <1302232>;
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ctrl-supply = <&ppvar_bigcpu_pwm>;
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ctrl-voltage-range = <800107 1302232>;
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regulator-settling-time-up-us = <322>;
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};
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ppvar_litcpu_pwm: ppvar-litcpu-pwm {
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compatible = "pwm-regulator";
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regulator-name = "ppvar_litcpu_pwm";
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pwms = <&pwm2 0 3337 0>;
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pwm-supply = <&ppvar_sys>;
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pwm-dutycycle-range = <100 0>;
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pwm-dutycycle-unit = <100>;
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/* EC turns on w/ ap_core_en; always on for AP */
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <797743>;
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regulator-max-microvolt = <1307837>;
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};
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ppvar_litcpu: ppvar-litcpu {
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compatible = "vctrl-regulator";
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regulator-name = "ppvar_litcpu";
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regulator-min-microvolt = <797743>;
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regulator-max-microvolt = <1307837>;
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ctrl-supply = <&ppvar_litcpu_pwm>;
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ctrl-voltage-range = <797743 1307837>;
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regulator-settling-time-up-us = <384>;
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};
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ppvar_gpu_pwm: ppvar-gpu-pwm {
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compatible = "pwm-regulator";
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regulator-name = "ppvar_gpu_pwm";
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pwms = <&pwm0 0 3337 0>;
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pwm-supply = <&ppvar_sys>;
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pwm-dutycycle-range = <100 0>;
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pwm-dutycycle-unit = <100>;
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/* EC turns on w/ ap_core_en; always on for AP */
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <786384>;
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regulator-max-microvolt = <1217747>;
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};
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ppvar_gpu: ppvar-gpu {
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compatible = "vctrl-regulator";
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regulator-name = "ppvar_gpu";
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regulator-min-microvolt = <786384>;
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regulator-max-microvolt = <1217747>;
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ctrl-supply = <&ppvar_gpu_pwm>;
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ctrl-voltage-range = <786384 1217747>;
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regulator-settling-time-up-us = <390>;
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};
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/* EC turns on w/ pp900_ddrpll_en */
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pp900_ddrpll: pp900-ap {
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};
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/* EC turns on w/ pp900_pll_en */
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pp900_pll: pp900-ap {
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};
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/* EC turns on w/ pp900_pmu_en */
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pp900_pmu: pp900-ap {
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};
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/* EC turns on w/ pp1800_s0_en_l */
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pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 {
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};
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/* EC turns on w/ pp1800_avdd_en_l */
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pp1800_avdd: pp1800 {
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};
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/* EC turns on w/ pp1800_lid_en_l */
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pp1800_lid: pp1800_mic: pp1800 {
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};
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/* EC turns on w/ lpddr_pwr_en */
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pp1800_lpddr: pp1800 {
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};
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/* EC turns on w/ pp1800_pmu_en_l */
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pp1800_pmu: pp1800 {
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};
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/* EC turns on w/ pp1800_usb_en_l */
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pp1800_usb: pp1800 {
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};
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pp3000_sd_slot: pp3000-sd-slot {
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compatible = "regulator-fixed";
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regulator-name = "pp3000_sd_slot";
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pinctrl-names = "default";
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pinctrl-0 = <&sd_slot_pwr_en>;
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enable-active-high;
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gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
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vin-supply = <&pp3000>;
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};
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/*
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* Technically, this is a small abuse of 'regulator-gpio'; this
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* regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are
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* always on though, so it is sufficient to simply control the mux
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* here.
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*/
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ppvar_sd_card_io: ppvar-sd-card-io {
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compatible = "regulator-gpio";
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regulator-name = "ppvar_sd_card_io";
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pinctrl-names = "default";
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pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>;
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enable-active-high;
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enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
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gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
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states = <1800000 0x1>,
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<3000000 0x0>;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3000000>;
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};
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/* EC turns on w/ pp3300_trackpad_en_l */
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pp3300_trackpad: pp3300-trackpad {
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};
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/* EC turns on w/ usb_a_en */
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pp5000_usb_a_vbus: pp5000 {
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};
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ap_rtc_clk: ap-rtc-clk {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "xin32k";
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#clock-cells = <0>;
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};
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max98357a: max98357a {
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compatible = "maxim,max98357a";
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pinctrl-names = "default";
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pinctrl-0 = <&sdmode_en>;
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sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
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sdmode-delay = <2>;
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#sound-dai-cells = <0>;
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status = "okay";
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};
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sound: sound {
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compatible = "rockchip,rk3399-gru-sound";
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rockchip,cpu = <&i2s0 &spdif>;
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};
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};
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&cdn_dp {
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status = "okay";
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};
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/*
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* Set some suspend operating points to avoid OVP in suspend
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*
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* When we go into S3 ARM Trusted Firmware will transition our PWM regulators
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* from wherever they're at back to the "default" operating point (whatever
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* voltage we get when we set the PWM pins to "input").
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*
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* This quick transition under light load has the possibility to trigger the
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* regulator "over voltage protection" (OVP).
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*
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* To make extra certain that we don't hit this OVP at suspend time, we'll
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* transition to a voltage that's much closer to the default (~1.0 V) so that
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* there will not be a big jump. Technically we only need to get within 200 mV
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* of the default voltage, but the speed here should be fast enough and we need
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* suspend/resume to be rock solid.
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*/
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&cluster0_opp {
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opp05 {
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opp-suspend;
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};
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};
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&cluster1_opp {
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opp06 {
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opp-suspend;
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};
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};
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&cpu_l0 {
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cpu-supply = <&ppvar_litcpu>;
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};
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&cpu_l1 {
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cpu-supply = <&ppvar_litcpu>;
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};
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&cpu_l2 {
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cpu-supply = <&ppvar_litcpu>;
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};
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&cpu_l3 {
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cpu-supply = <&ppvar_litcpu>;
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};
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&cpu_b0 {
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cpu-supply = <&ppvar_bigcpu>;
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};
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&cpu_b1 {
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cpu-supply = <&ppvar_bigcpu>;
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};
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&cru {
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assigned-clocks =
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<&cru PLL_GPLL>, <&cru PLL_CPLL>,
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<&cru PLL_NPLL>,
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<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
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<&cru PCLK_PERIHP>,
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<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
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<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
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<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
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<&cru ACLK_VIO>, <&cru ACLK_HDCP>,
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<&cru ACLK_GIC_PRE>,
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<&cru PCLK_DDR>;
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assigned-clock-rates =
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<600000000>, <800000000>,
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<1000000000>,
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<150000000>, <75000000>,
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<37500000>,
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<100000000>, <100000000>,
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<50000000>, <800000000>,
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<100000000>, <50000000>,
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<400000000>, <400000000>,
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<200000000>,
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<200000000>;
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};
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&dfi {
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status = "okay";
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};
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&dmc {
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status = "okay";
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rockchip,pd-idle-ns = <160>;
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rockchip,sr-idle-ns = <10240>;
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rockchip,sr-mc-gate-idle-ns = <40960>;
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rockchip,srpd-lite-idle-ns = <61440>;
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rockchip,standby-idle-ns = <81920>;
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rockchip,ddr3_odt_dis_freq = <666000000>;
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rockchip,lpddr3_odt_dis_freq = <666000000>;
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rockchip,lpddr4_odt_dis_freq = <666000000>;
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rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>;
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rockchip,srpd-lite-idle-dis-freq-hz = <0>;
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rockchip,standby-idle-dis-freq-hz = <928000000>;
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};
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&dmc_opp_table {
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opp03 {
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opp-suspend;
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};
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};
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&emmc_phy {
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status = "okay";
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};
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&gpu {
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mali-supply = <&ppvar_gpu>;
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status = "okay";
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};
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ap_i2c_ts: &i2c3 {
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status = "okay";
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clock-frequency = <400000>;
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/* These are relatively safe rise/fall times */
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i2c-scl-falling-time-ns = <50>;
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i2c-scl-rising-time-ns = <300>;
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};
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ap_i2c_audio: &i2c8 {
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status = "okay";
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clock-frequency = <400000>;
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/* These are relatively safe rise/fall times */
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i2c-scl-falling-time-ns = <50>;
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i2c-scl-rising-time-ns = <300>;
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codec: da7219@1a {
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compatible = "dlg,da7219";
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reg = <0x1a>;
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interrupt-parent = <&gpio1>;
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interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&cru SCLK_I2S_8CH_OUT>;
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clock-names = "mclk";
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dlg,micbias-lvl = <2600>;
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dlg,mic-amp-in-sel = "diff";
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pinctrl-names = "default";
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pinctrl-0 = <&headset_int_l>;
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VDD-supply = <&pp1800>;
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VDDMIC-supply = <&pp3300>;
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VDDIO-supply = <&pp1800>;
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da7219_aad {
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dlg,adc-1bit-rpt = <1>;
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dlg,btn-avg = <4>;
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dlg,btn-cfg = <50>;
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dlg,mic-det-thr = <500>;
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dlg,jack-ins-deb = <20>;
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dlg,jack-det-rate = "32ms_64ms";
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dlg,jack-rem-deb = <1>;
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dlg,a-d-btn-thr = <0xa>;
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dlg,d-b-btn-thr = <0x16>;
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dlg,b-c-btn-thr = <0x21>;
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dlg,c-mic-btn-thr = <0x3E>;
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};
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};
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};
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&i2s0 {
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status = "okay";
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};
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&io_domains {
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status = "okay";
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audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */
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bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */
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gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */
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sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */
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};
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&pcie0 {
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status = "okay";
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ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>;
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vpcie3v3-supply = <&pp3300_wifi_bt>;
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vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */
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vpcie0v9-supply = <&pp900_pcie>;
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pci_rootport: pcie@0,0 {
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reg = <0x0000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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};
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&pcie_phy {
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status = "okay";
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};
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&pmu_io_domains {
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status = "okay";
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pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */
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};
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&pwm0 {
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status = "okay";
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};
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&pwm1 {
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status = "okay";
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};
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&pwm2 {
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status = "okay";
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};
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&pwm3 {
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status = "okay";
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};
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&sdhci {
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/*
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* Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the
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* same (or nearly the same) performance for all eMMC that are intended
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* to be used.
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*/
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assigned-clock-rates = <150000000>;
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bus-width = <8>;
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mmc-hs400-1_8v;
|
|
mmc-hs400-enhanced-strobe;
|
|
non-removable;
|
|
status = "okay";
|
|
};
|
|
|
|
&sdmmc {
|
|
status = "okay";
|
|
|
|
/*
|
|
* Note: configure "sdmmc_cd" as card detect even though it's actually
|
|
* hooked to ground. Because we specified "cd-gpios" below dw_mmc
|
|
* should be ignoring card detect anyway. Specifying the pin as
|
|
* sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag)
|
|
* turned on that the system will still make sure the port is
|
|
* configured as SDMMC and not JTAG.
|
|
*/
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_pin
|
|
&sdmmc_bus4>;
|
|
|
|
bus-width = <4>;
|
|
cap-mmc-highspeed;
|
|
cap-sd-highspeed;
|
|
cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
|
|
disable-wp;
|
|
sd-uhs-sdr12;
|
|
sd-uhs-sdr25;
|
|
sd-uhs-sdr50;
|
|
sd-uhs-sdr104;
|
|
vmmc-supply = <&pp3000_sd_slot>;
|
|
vqmmc-supply = <&ppvar_sd_card_io>;
|
|
};
|
|
|
|
&spdif {
|
|
status = "okay";
|
|
|
|
/*
|
|
* SPDIF is routed internally to DP; we either don't use these pins, or
|
|
* mux them to something else.
|
|
*/
|
|
/delete-property/ pinctrl-0;
|
|
/delete-property/ pinctrl-names;
|
|
};
|
|
|
|
&spi1 {
|
|
status = "okay";
|
|
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-1 = <&spi1_sleep>;
|
|
|
|
flash@0 {
|
|
compatible = "jedec,spi-nor";
|
|
reg = <0>;
|
|
|
|
/* May run faster once verified. */
|
|
spi-max-frequency = <10000000>;
|
|
};
|
|
};
|
|
|
|
&spi2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&spi5 {
|
|
status = "okay";
|
|
|
|
cros_ec: ec@0 {
|
|
compatible = "google,cros-ec-spi";
|
|
reg = <0>;
|
|
interrupt-parent = <&gpio0>;
|
|
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&ec_ap_int_l>;
|
|
spi-max-frequency = <3000000>;
|
|
|
|
i2c_tunnel: i2c-tunnel {
|
|
compatible = "google,cros-ec-i2c-tunnel";
|
|
google,remote-bus = <4>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
usbc_extcon0: extcon0 {
|
|
compatible = "google,extcon-usbc-cros-ec";
|
|
google,usb-port-id = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&tsadc {
|
|
status = "okay";
|
|
|
|
rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
|
|
rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
|
|
};
|
|
|
|
&tcphy0 {
|
|
status = "okay";
|
|
extcon = <&usbc_extcon0>;
|
|
};
|
|
|
|
&u2phy0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&u2phy0_host {
|
|
status = "okay";
|
|
};
|
|
|
|
&u2phy1_host {
|
|
status = "okay";
|
|
};
|
|
|
|
&u2phy0_otg {
|
|
status = "okay";
|
|
};
|
|
|
|
&u2phy1_otg {
|
|
status = "okay";
|
|
};
|
|
|
|
&uart2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb_host0_ohci {
|
|
status = "okay";
|
|
};
|
|
|
|
&usbdrd3_0 {
|
|
status = "okay";
|
|
extcon = <&usbc_extcon0>;
|
|
};
|
|
|
|
&usbdrd_dwc3_0 {
|
|
status = "okay";
|
|
dr_mode = "host";
|
|
};
|
|
|
|
&vopb {
|
|
status = "okay";
|
|
};
|
|
|
|
&vopb_mmu {
|
|
status = "okay";
|
|
};
|
|
|
|
&vopl {
|
|
status = "okay";
|
|
};
|
|
|
|
&vopl_mmu {
|
|
status = "okay";
|
|
};
|
|
|
|
#include <arm/cros-ec-keyboard.dtsi>
|
|
#include <arm/cros-ec-sbs.dtsi>
|
|
|
|
&pinctrl {
|
|
/*
|
|
* pinctrl settings for pins that have no real owners.
|
|
*
|
|
* At the moment settings are identical for S0 and S3, but if we later
|
|
* need to configure things differently for S3 we'll adjust here.
|
|
*/
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <
|
|
&ap_pwroff /* AP will auto-assert this when in S3 */
|
|
&clk_32k /* This pin is always 32k on gru boards */
|
|
>;
|
|
|
|
pcfg_output_low: pcfg-output-low {
|
|
output-low;
|
|
};
|
|
|
|
pcfg_output_high: pcfg-output-high {
|
|
output-high;
|
|
};
|
|
|
|
pcfg_pull_none_8ma: pcfg-pull-none-8ma {
|
|
bias-disable;
|
|
drive-strength = <8>;
|
|
};
|
|
|
|
backlight-enable {
|
|
bl_en: bl-en {
|
|
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
cros-ec {
|
|
ec_ap_int_l: ec-ap-int-l {
|
|
rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
discrete-regulators {
|
|
sd_io_pwr_en: sd-io-pwr-en {
|
|
rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO
|
|
&pcfg_pull_none>;
|
|
};
|
|
|
|
sd_pwr_1800_sel: sd-pwr-1800-sel {
|
|
rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO
|
|
&pcfg_pull_none>;
|
|
};
|
|
|
|
sd_slot_pwr_en: sd-slot-pwr-en {
|
|
rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO
|
|
&pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
codec {
|
|
/* Has external pullup */
|
|
headset_int_l: headset-int-l {
|
|
rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
|
|
mic_int: mic-int {
|
|
rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
};
|
|
};
|
|
|
|
max98357a {
|
|
sdmode_en: sdmode-en {
|
|
rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
};
|
|
};
|
|
|
|
pcie {
|
|
pcie_clkreqn_cpm: pci-clkreqn-cpm {
|
|
/*
|
|
* Since our pcie doesn't support ClockPM(CPM), we want
|
|
* to hack this as gpio, so the EP could be able to
|
|
* de-assert it along and make ClockPM(CPM) work.
|
|
*/
|
|
rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sdmmc {
|
|
/*
|
|
* We run sdmmc at max speed; bump up drive strength.
|
|
* We also have external pulls, so disable the internal ones.
|
|
*/
|
|
sdmmc_bus4: sdmmc-bus4 {
|
|
rockchip,pins =
|
|
<4 RK_PB0 1 &pcfg_pull_none_8ma>,
|
|
<4 RK_PB1 1 &pcfg_pull_none_8ma>,
|
|
<4 RK_PB2 1 &pcfg_pull_none_8ma>,
|
|
<4 RK_PB3 1 &pcfg_pull_none_8ma>;
|
|
};
|
|
|
|
sdmmc_clk: sdmmc-clk {
|
|
rockchip,pins =
|
|
<4 RK_PB4 1 &pcfg_pull_none_8ma>;
|
|
};
|
|
|
|
sdmmc_cmd: sdmmc-cmd {
|
|
rockchip,pins =
|
|
<4 RK_PB5 1 &pcfg_pull_none_8ma>;
|
|
};
|
|
|
|
/*
|
|
* In our case the official card detect is hooked to ground
|
|
* to avoid getting access to JTAG just by sticking something
|
|
* in the SD card slot (see the force_jtag bit in the TRM).
|
|
*
|
|
* We still configure it as card detect because it doesn't
|
|
* hurt and dw_mmc will ignore it. We make sure to disable
|
|
* the pull though so we don't burn needless power.
|
|
*/
|
|
sdmmc_cd: sdmmc-cd {
|
|
rockchip,pins =
|
|
<0 RK_PA7 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/* This is where we actually hook up CD; has external pull */
|
|
sdmmc_cd_pin: sdmmc-cd-pin {
|
|
rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spi1 {
|
|
spi1_sleep: spi1-sleep {
|
|
/*
|
|
* Pull down SPI1 CLK/CS/RX/TX during suspend, to
|
|
* prevent leakage.
|
|
*/
|
|
rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
<1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
<1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>,
|
|
<1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
};
|
|
};
|
|
|
|
touchscreen {
|
|
touch_int_l: touch-int-l {
|
|
rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
};
|
|
|
|
touch_reset_l: touch-reset-l {
|
|
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
trackpad {
|
|
ap_i2c_tp_pu_en: ap-i2c-tp-pu-en {
|
|
rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>;
|
|
};
|
|
|
|
trackpad_int_l: trackpad-int-l {
|
|
rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
wifi: wifi {
|
|
wlan_module_reset_l: wlan-module-reset-l {
|
|
rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
|
|
bt_host_wake_l: bt-host-wake-l {
|
|
/* Kevin has an external pull up, but Gru does not */
|
|
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
write-protect {
|
|
ap_fw_wp: ap-fw-wp {
|
|
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
};
|
|
};
|
|
};
|