764 строки
21 KiB
C
764 строки
21 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*
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* A code-rewriter that enables instruction single-stepping.
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* Derived from iLib's single-stepping code.
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*/
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#ifndef __tilegx__ /* Hardware support for single step unavailable. */
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/* These functions are only used on the TILE platform */
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#include <linux/slab.h>
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#include <linux/thread_info.h>
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#include <linux/uaccess.h>
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#include <linux/mman.h>
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#include <linux/types.h>
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#include <linux/err.h>
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#include <asm/cacheflush.h>
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#include <asm/opcode-tile.h>
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#include <asm/opcode_constants.h>
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#include <arch/abi.h>
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#define signExtend17(val) sign_extend((val), 17)
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#define TILE_X1_MASK (0xffffffffULL << 31)
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int unaligned_printk;
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static int __init setup_unaligned_printk(char *str)
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{
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long val;
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if (strict_strtol(str, 0, &val) != 0)
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return 0;
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unaligned_printk = val;
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pr_info("Printk for each unaligned data accesses is %s\n",
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unaligned_printk ? "enabled" : "disabled");
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return 1;
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}
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__setup("unaligned_printk=", setup_unaligned_printk);
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unsigned int unaligned_fixup_count;
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enum mem_op {
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MEMOP_NONE,
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MEMOP_LOAD,
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MEMOP_STORE,
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MEMOP_LOAD_POSTINCR,
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MEMOP_STORE_POSTINCR
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};
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static inline tile_bundle_bits set_BrOff_X1(tile_bundle_bits n, s32 offset)
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{
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tile_bundle_bits result;
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/* mask out the old offset */
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tile_bundle_bits mask = create_BrOff_X1(-1);
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result = n & (~mask);
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/* or in the new offset */
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result |= create_BrOff_X1(offset);
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return result;
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}
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static inline tile_bundle_bits move_X1(tile_bundle_bits n, int dest, int src)
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{
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tile_bundle_bits result;
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tile_bundle_bits op;
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result = n & (~TILE_X1_MASK);
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op = create_Opcode_X1(SPECIAL_0_OPCODE_X1) |
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create_RRROpcodeExtension_X1(OR_SPECIAL_0_OPCODE_X1) |
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create_Dest_X1(dest) |
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create_SrcB_X1(TREG_ZERO) |
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create_SrcA_X1(src) ;
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result |= op;
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return result;
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}
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static inline tile_bundle_bits nop_X1(tile_bundle_bits n)
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{
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return move_X1(n, TREG_ZERO, TREG_ZERO);
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}
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static inline tile_bundle_bits addi_X1(
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tile_bundle_bits n, int dest, int src, int imm)
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{
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n &= ~TILE_X1_MASK;
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n |= (create_SrcA_X1(src) |
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create_Dest_X1(dest) |
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create_Imm8_X1(imm) |
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create_S_X1(0) |
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create_Opcode_X1(IMM_0_OPCODE_X1) |
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create_ImmOpcodeExtension_X1(ADDI_IMM_0_OPCODE_X1));
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return n;
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}
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static tile_bundle_bits rewrite_load_store_unaligned(
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struct single_step_state *state,
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tile_bundle_bits bundle,
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struct pt_regs *regs,
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enum mem_op mem_op,
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int size, int sign_ext)
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{
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unsigned char __user *addr;
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int val_reg, addr_reg, err, val;
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/* Get address and value registers */
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if (bundle & TILE_BUNDLE_Y_ENCODING_MASK) {
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addr_reg = get_SrcA_Y2(bundle);
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val_reg = get_SrcBDest_Y2(bundle);
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} else if (mem_op == MEMOP_LOAD || mem_op == MEMOP_LOAD_POSTINCR) {
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addr_reg = get_SrcA_X1(bundle);
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val_reg = get_Dest_X1(bundle);
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} else {
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addr_reg = get_SrcA_X1(bundle);
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val_reg = get_SrcB_X1(bundle);
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}
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/*
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* If registers are not GPRs, don't try to handle it.
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*
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* FIXME: we could handle non-GPR loads by getting the real value
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* from memory, writing it to the single step buffer, using a
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* temp_reg to hold a pointer to that memory, then executing that
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* instruction and resetting temp_reg. For non-GPR stores, it's a
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* little trickier; we could use the single step buffer for that
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* too, but we'd have to add some more state bits so that we could
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* call back in here to copy that value to the real target. For
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* now, we just handle the simple case.
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*/
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if ((val_reg >= PTREGS_NR_GPRS &&
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(val_reg != TREG_ZERO ||
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mem_op == MEMOP_LOAD ||
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mem_op == MEMOP_LOAD_POSTINCR)) ||
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addr_reg >= PTREGS_NR_GPRS)
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return bundle;
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/* If it's aligned, don't handle it specially */
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addr = (void __user *)regs->regs[addr_reg];
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if (((unsigned long)addr % size) == 0)
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return bundle;
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#ifndef __LITTLE_ENDIAN
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# error We assume little-endian representation with copy_xx_user size 2 here
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#endif
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/* Handle unaligned load/store */
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if (mem_op == MEMOP_LOAD || mem_op == MEMOP_LOAD_POSTINCR) {
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unsigned short val_16;
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switch (size) {
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case 2:
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err = copy_from_user(&val_16, addr, sizeof(val_16));
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val = sign_ext ? ((short)val_16) : val_16;
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break;
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case 4:
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err = copy_from_user(&val, addr, sizeof(val));
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break;
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default:
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BUG();
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}
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if (err == 0) {
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state->update_reg = val_reg;
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state->update_value = val;
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state->update = 1;
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}
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} else {
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val = (val_reg == TREG_ZERO) ? 0 : regs->regs[val_reg];
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err = copy_to_user(addr, &val, size);
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}
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if (err) {
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siginfo_t info = {
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.si_signo = SIGSEGV,
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.si_code = SEGV_MAPERR,
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.si_addr = addr
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};
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trace_unhandled_signal("segfault", regs,
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(unsigned long)addr, SIGSEGV);
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force_sig_info(info.si_signo, &info, current);
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return (tile_bundle_bits) 0;
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}
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if (unaligned_fixup == 0) {
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siginfo_t info = {
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.si_signo = SIGBUS,
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.si_code = BUS_ADRALN,
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.si_addr = addr
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};
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trace_unhandled_signal("unaligned trap", regs,
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(unsigned long)addr, SIGBUS);
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force_sig_info(info.si_signo, &info, current);
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return (tile_bundle_bits) 0;
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}
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if (unaligned_printk || unaligned_fixup_count == 0) {
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pr_info("Process %d/%s: PC %#lx: Fixup of"
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" unaligned %s at %#lx.\n",
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current->pid, current->comm, regs->pc,
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(mem_op == MEMOP_LOAD ||
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mem_op == MEMOP_LOAD_POSTINCR) ?
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"load" : "store",
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(unsigned long)addr);
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if (!unaligned_printk) {
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#define P pr_info
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P("\n");
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P("Unaligned fixups in the kernel will slow your application considerably.\n");
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P("To find them, write a \"1\" to /proc/sys/tile/unaligned_fixup/printk,\n");
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P("which requests the kernel show all unaligned fixups, or write a \"0\"\n");
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P("to /proc/sys/tile/unaligned_fixup/enabled, in which case each unaligned\n");
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P("access will become a SIGBUS you can debug. No further warnings will be\n");
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P("shown so as to avoid additional slowdown, but you can track the number\n");
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P("of fixups performed via /proc/sys/tile/unaligned_fixup/count.\n");
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P("Use the tile-addr2line command (see \"info addr2line\") to decode PCs.\n");
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P("\n");
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#undef P
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}
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}
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++unaligned_fixup_count;
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if (bundle & TILE_BUNDLE_Y_ENCODING_MASK) {
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/* Convert the Y2 instruction to a prefetch. */
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bundle &= ~(create_SrcBDest_Y2(-1) |
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create_Opcode_Y2(-1));
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bundle |= (create_SrcBDest_Y2(TREG_ZERO) |
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create_Opcode_Y2(LW_OPCODE_Y2));
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/* Replace the load postincr with an addi */
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} else if (mem_op == MEMOP_LOAD_POSTINCR) {
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bundle = addi_X1(bundle, addr_reg, addr_reg,
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get_Imm8_X1(bundle));
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/* Replace the store postincr with an addi */
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} else if (mem_op == MEMOP_STORE_POSTINCR) {
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bundle = addi_X1(bundle, addr_reg, addr_reg,
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get_Dest_Imm8_X1(bundle));
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} else {
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/* Convert the X1 instruction to a nop. */
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bundle &= ~(create_Opcode_X1(-1) |
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create_UnShOpcodeExtension_X1(-1) |
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create_UnOpcodeExtension_X1(-1));
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bundle |= (create_Opcode_X1(SHUN_0_OPCODE_X1) |
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create_UnShOpcodeExtension_X1(
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UN_0_SHUN_0_OPCODE_X1) |
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create_UnOpcodeExtension_X1(
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NOP_UN_0_SHUN_0_OPCODE_X1));
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}
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return bundle;
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}
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/*
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* Called after execve() has started the new image. This allows us
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* to reset the info state. Note that the the mmap'ed memory, if there
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* was any, has already been unmapped by the exec.
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*/
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void single_step_execve(void)
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{
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struct thread_info *ti = current_thread_info();
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kfree(ti->step_state);
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ti->step_state = NULL;
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}
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/**
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* single_step_once() - entry point when single stepping has been triggered.
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* @regs: The machine register state
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*
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* When we arrive at this routine via a trampoline, the single step
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* engine copies the executing bundle to the single step buffer.
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* If the instruction is a condition branch, then the target is
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* reset to one past the next instruction. If the instruction
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* sets the lr, then that is noted. If the instruction is a jump
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* or call, then the new target pc is preserved and the current
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* bundle instruction set to null.
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*
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* The necessary post-single-step rewriting information is stored in
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* single_step_state-> We use data segment values because the
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* stack will be rewound when we run the rewritten single-stepped
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* instruction.
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*/
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void single_step_once(struct pt_regs *regs)
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{
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extern tile_bundle_bits __single_step_ill_insn;
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extern tile_bundle_bits __single_step_j_insn;
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extern tile_bundle_bits __single_step_addli_insn;
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extern tile_bundle_bits __single_step_auli_insn;
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struct thread_info *info = (void *)current_thread_info();
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struct single_step_state *state = info->step_state;
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int is_single_step = test_ti_thread_flag(info, TIF_SINGLESTEP);
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tile_bundle_bits __user *buffer, *pc;
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tile_bundle_bits bundle;
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int temp_reg;
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int target_reg = TREG_LR;
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int err;
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enum mem_op mem_op = MEMOP_NONE;
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int size = 0, sign_ext = 0; /* happy compiler */
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asm(
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" .pushsection .rodata.single_step\n"
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" .align 8\n"
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" .globl __single_step_ill_insn\n"
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"__single_step_ill_insn:\n"
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" ill\n"
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" .globl __single_step_addli_insn\n"
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"__single_step_addli_insn:\n"
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" { nop; addli r0, zero, 0 }\n"
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" .globl __single_step_auli_insn\n"
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"__single_step_auli_insn:\n"
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" { nop; auli r0, r0, 0 }\n"
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" .globl __single_step_j_insn\n"
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"__single_step_j_insn:\n"
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" j .\n"
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" .popsection\n"
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);
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/*
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* Enable interrupts here to allow touching userspace and the like.
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* The callers expect this: do_trap() already has interrupts
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* enabled, and do_work_pending() handles functions that enable
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* interrupts internally.
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*/
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local_irq_enable();
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if (state == NULL) {
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/* allocate a page of writable, executable memory */
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state = kmalloc(sizeof(struct single_step_state), GFP_KERNEL);
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if (state == NULL) {
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pr_err("Out of kernel memory trying to single-step\n");
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return;
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}
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/* allocate a cache line of writable, executable memory */
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down_write(¤t->mm->mmap_sem);
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buffer = (void __user *) do_mmap(NULL, 0, 64,
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PROT_EXEC | PROT_READ | PROT_WRITE,
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MAP_PRIVATE | MAP_ANONYMOUS,
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0);
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up_write(¤t->mm->mmap_sem);
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if (IS_ERR((void __force *)buffer)) {
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kfree(state);
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pr_err("Out of kernel pages trying to single-step\n");
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return;
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}
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state->buffer = buffer;
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state->is_enabled = 0;
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info->step_state = state;
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/* Validate our stored instruction patterns */
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BUG_ON(get_Opcode_X1(__single_step_addli_insn) !=
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ADDLI_OPCODE_X1);
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BUG_ON(get_Opcode_X1(__single_step_auli_insn) !=
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AULI_OPCODE_X1);
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BUG_ON(get_SrcA_X1(__single_step_addli_insn) != TREG_ZERO);
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BUG_ON(get_Dest_X1(__single_step_addli_insn) != 0);
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BUG_ON(get_JOffLong_X1(__single_step_j_insn) != 0);
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}
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/*
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* If we are returning from a syscall, we still haven't hit the
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* "ill" for the swint1 instruction. So back the PC up to be
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* pointing at the swint1, but we'll actually return directly
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* back to the "ill" so we come back in via SIGILL as if we
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* had "executed" the swint1 without ever being in kernel space.
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*/
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if (regs->faultnum == INT_SWINT_1)
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regs->pc -= 8;
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pc = (tile_bundle_bits __user *)(regs->pc);
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if (get_user(bundle, pc) != 0) {
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pr_err("Couldn't read instruction at %p trying to step\n", pc);
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return;
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}
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/* We'll follow the instruction with 2 ill op bundles */
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state->orig_pc = (unsigned long)pc;
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state->next_pc = (unsigned long)(pc + 1);
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state->branch_next_pc = 0;
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state->update = 0;
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if (!(bundle & TILE_BUNDLE_Y_ENCODING_MASK)) {
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/* two wide, check for control flow */
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int opcode = get_Opcode_X1(bundle);
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switch (opcode) {
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/* branches */
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case BRANCH_OPCODE_X1:
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{
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s32 offset = signExtend17(get_BrOff_X1(bundle));
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/*
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* For branches, we use a rewriting trick to let the
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* hardware evaluate whether the branch is taken or
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* untaken. We record the target offset and then
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* rewrite the branch instruction to target 1 insn
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* ahead if the branch is taken. We then follow the
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* rewritten branch with two bundles, each containing
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* an "ill" instruction. The supervisor examines the
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* pc after the single step code is executed, and if
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* the pc is the first ill instruction, then the
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* branch (if any) was not taken. If the pc is the
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* second ill instruction, then the branch was
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* taken. The new pc is computed for these cases, and
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* inserted into the registers for the thread. If
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* the pc is the start of the single step code, then
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* an exception or interrupt was taken before the
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* code started processing, and the same "original"
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* pc is restored. This change, different from the
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* original implementation, has the advantage of
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* executing a single user instruction.
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*/
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state->branch_next_pc = (unsigned long)(pc + offset);
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/* rewrite branch offset to go forward one bundle */
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bundle = set_BrOff_X1(bundle, 2);
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}
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break;
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/* jumps */
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case JALB_OPCODE_X1:
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case JALF_OPCODE_X1:
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state->update = 1;
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state->next_pc =
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(unsigned long) (pc + get_JOffLong_X1(bundle));
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break;
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case JB_OPCODE_X1:
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case JF_OPCODE_X1:
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state->next_pc =
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(unsigned long) (pc + get_JOffLong_X1(bundle));
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bundle = nop_X1(bundle);
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break;
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case SPECIAL_0_OPCODE_X1:
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switch (get_RRROpcodeExtension_X1(bundle)) {
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/* jump-register */
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case JALRP_SPECIAL_0_OPCODE_X1:
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case JALR_SPECIAL_0_OPCODE_X1:
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state->update = 1;
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state->next_pc =
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regs->regs[get_SrcA_X1(bundle)];
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break;
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case JRP_SPECIAL_0_OPCODE_X1:
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case JR_SPECIAL_0_OPCODE_X1:
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state->next_pc =
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regs->regs[get_SrcA_X1(bundle)];
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bundle = nop_X1(bundle);
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break;
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case LNK_SPECIAL_0_OPCODE_X1:
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state->update = 1;
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target_reg = get_Dest_X1(bundle);
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break;
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/* stores */
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case SH_SPECIAL_0_OPCODE_X1:
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mem_op = MEMOP_STORE;
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size = 2;
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break;
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case SW_SPECIAL_0_OPCODE_X1:
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mem_op = MEMOP_STORE;
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size = 4;
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break;
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}
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break;
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/* loads and iret */
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case SHUN_0_OPCODE_X1:
|
|
if (get_UnShOpcodeExtension_X1(bundle) ==
|
|
UN_0_SHUN_0_OPCODE_X1) {
|
|
switch (get_UnOpcodeExtension_X1(bundle)) {
|
|
case LH_UN_0_SHUN_0_OPCODE_X1:
|
|
mem_op = MEMOP_LOAD;
|
|
size = 2;
|
|
sign_ext = 1;
|
|
break;
|
|
|
|
case LH_U_UN_0_SHUN_0_OPCODE_X1:
|
|
mem_op = MEMOP_LOAD;
|
|
size = 2;
|
|
sign_ext = 0;
|
|
break;
|
|
|
|
case LW_UN_0_SHUN_0_OPCODE_X1:
|
|
mem_op = MEMOP_LOAD;
|
|
size = 4;
|
|
break;
|
|
|
|
case IRET_UN_0_SHUN_0_OPCODE_X1:
|
|
{
|
|
unsigned long ex0_0 = __insn_mfspr(
|
|
SPR_EX_CONTEXT_0_0);
|
|
unsigned long ex0_1 = __insn_mfspr(
|
|
SPR_EX_CONTEXT_0_1);
|
|
/*
|
|
* Special-case it if we're iret'ing
|
|
* to PL0 again. Otherwise just let
|
|
* it run and it will generate SIGILL.
|
|
*/
|
|
if (EX1_PL(ex0_1) == USER_PL) {
|
|
state->next_pc = ex0_0;
|
|
regs->ex1 = ex0_1;
|
|
bundle = nop_X1(bundle);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
|
|
#if CHIP_HAS_WH64()
|
|
/* postincrement operations */
|
|
case IMM_0_OPCODE_X1:
|
|
switch (get_ImmOpcodeExtension_X1(bundle)) {
|
|
case LWADD_IMM_0_OPCODE_X1:
|
|
mem_op = MEMOP_LOAD_POSTINCR;
|
|
size = 4;
|
|
break;
|
|
|
|
case LHADD_IMM_0_OPCODE_X1:
|
|
mem_op = MEMOP_LOAD_POSTINCR;
|
|
size = 2;
|
|
sign_ext = 1;
|
|
break;
|
|
|
|
case LHADD_U_IMM_0_OPCODE_X1:
|
|
mem_op = MEMOP_LOAD_POSTINCR;
|
|
size = 2;
|
|
sign_ext = 0;
|
|
break;
|
|
|
|
case SWADD_IMM_0_OPCODE_X1:
|
|
mem_op = MEMOP_STORE_POSTINCR;
|
|
size = 4;
|
|
break;
|
|
|
|
case SHADD_IMM_0_OPCODE_X1:
|
|
mem_op = MEMOP_STORE_POSTINCR;
|
|
size = 2;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
#endif /* CHIP_HAS_WH64() */
|
|
}
|
|
|
|
if (state->update) {
|
|
/*
|
|
* Get an available register. We start with a
|
|
* bitmask with 1's for available registers.
|
|
* We truncate to the low 32 registers since
|
|
* we are guaranteed to have set bits in the
|
|
* low 32 bits, then use ctz to pick the first.
|
|
*/
|
|
u32 mask = (u32) ~((1ULL << get_Dest_X0(bundle)) |
|
|
(1ULL << get_SrcA_X0(bundle)) |
|
|
(1ULL << get_SrcB_X0(bundle)) |
|
|
(1ULL << target_reg));
|
|
temp_reg = __builtin_ctz(mask);
|
|
state->update_reg = temp_reg;
|
|
state->update_value = regs->regs[temp_reg];
|
|
regs->regs[temp_reg] = (unsigned long) (pc+1);
|
|
regs->flags |= PT_FLAGS_RESTORE_REGS;
|
|
bundle = move_X1(bundle, target_reg, temp_reg);
|
|
}
|
|
} else {
|
|
int opcode = get_Opcode_Y2(bundle);
|
|
|
|
switch (opcode) {
|
|
/* loads */
|
|
case LH_OPCODE_Y2:
|
|
mem_op = MEMOP_LOAD;
|
|
size = 2;
|
|
sign_ext = 1;
|
|
break;
|
|
|
|
case LH_U_OPCODE_Y2:
|
|
mem_op = MEMOP_LOAD;
|
|
size = 2;
|
|
sign_ext = 0;
|
|
break;
|
|
|
|
case LW_OPCODE_Y2:
|
|
mem_op = MEMOP_LOAD;
|
|
size = 4;
|
|
break;
|
|
|
|
/* stores */
|
|
case SH_OPCODE_Y2:
|
|
mem_op = MEMOP_STORE;
|
|
size = 2;
|
|
break;
|
|
|
|
case SW_OPCODE_Y2:
|
|
mem_op = MEMOP_STORE;
|
|
size = 4;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Check if we need to rewrite an unaligned load/store.
|
|
* Returning zero is a special value meaning we need to SIGSEGV.
|
|
*/
|
|
if (mem_op != MEMOP_NONE && unaligned_fixup >= 0) {
|
|
bundle = rewrite_load_store_unaligned(state, bundle, regs,
|
|
mem_op, size, sign_ext);
|
|
if (bundle == 0)
|
|
return;
|
|
}
|
|
|
|
/* write the bundle to our execution area */
|
|
buffer = state->buffer;
|
|
err = __put_user(bundle, buffer++);
|
|
|
|
/*
|
|
* If we're really single-stepping, we take an INT_ILL after.
|
|
* If we're just handling an unaligned access, we can just
|
|
* jump directly back to where we were in user code.
|
|
*/
|
|
if (is_single_step) {
|
|
err |= __put_user(__single_step_ill_insn, buffer++);
|
|
err |= __put_user(__single_step_ill_insn, buffer++);
|
|
} else {
|
|
long delta;
|
|
|
|
if (state->update) {
|
|
/* We have some state to update; do it inline */
|
|
int ha16;
|
|
bundle = __single_step_addli_insn;
|
|
bundle |= create_Dest_X1(state->update_reg);
|
|
bundle |= create_Imm16_X1(state->update_value);
|
|
err |= __put_user(bundle, buffer++);
|
|
bundle = __single_step_auli_insn;
|
|
bundle |= create_Dest_X1(state->update_reg);
|
|
bundle |= create_SrcA_X1(state->update_reg);
|
|
ha16 = (state->update_value + 0x8000) >> 16;
|
|
bundle |= create_Imm16_X1(ha16);
|
|
err |= __put_user(bundle, buffer++);
|
|
state->update = 0;
|
|
}
|
|
|
|
/* End with a jump back to the next instruction */
|
|
delta = ((regs->pc + TILE_BUNDLE_SIZE_IN_BYTES) -
|
|
(unsigned long)buffer) >>
|
|
TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES;
|
|
bundle = __single_step_j_insn;
|
|
bundle |= create_JOffLong_X1(delta);
|
|
err |= __put_user(bundle, buffer++);
|
|
}
|
|
|
|
if (err) {
|
|
pr_err("Fault when writing to single-step buffer\n");
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Flush the buffer.
|
|
* We do a local flush only, since this is a thread-specific buffer.
|
|
*/
|
|
__flush_icache_range((unsigned long)state->buffer,
|
|
(unsigned long)buffer);
|
|
|
|
/* Indicate enabled */
|
|
state->is_enabled = is_single_step;
|
|
regs->pc = (unsigned long)state->buffer;
|
|
|
|
/* Fault immediately if we are coming back from a syscall. */
|
|
if (regs->faultnum == INT_SWINT_1)
|
|
regs->pc += 8;
|
|
}
|
|
|
|
#else
|
|
#include <linux/smp.h>
|
|
#include <linux/ptrace.h>
|
|
#include <arch/spr_def.h>
|
|
|
|
static DEFINE_PER_CPU(unsigned long, ss_saved_pc);
|
|
|
|
|
|
/*
|
|
* Called directly on the occasion of an interrupt.
|
|
*
|
|
* If the process doesn't have single step set, then we use this as an
|
|
* opportunity to turn single step off.
|
|
*
|
|
* It has been mentioned that we could conditionally turn off single stepping
|
|
* on each entry into the kernel and rely on single_step_once to turn it
|
|
* on for the processes that matter (as we already do), but this
|
|
* implementation is somewhat more efficient in that we muck with registers
|
|
* once on a bum interrupt rather than on every entry into the kernel.
|
|
*
|
|
* If SINGLE_STEP_CONTROL_K has CANCELED set, then an interrupt occurred,
|
|
* so we have to run through this process again before we can say that an
|
|
* instruction has executed.
|
|
*
|
|
* swint will set CANCELED, but it's a legitimate instruction. Fortunately
|
|
* it changes the PC. If it hasn't changed, then we know that the interrupt
|
|
* wasn't generated by swint and we'll need to run this process again before
|
|
* we can say an instruction has executed.
|
|
*
|
|
* If either CANCELED == 0 or the PC's changed, we send out SIGTRAPs and get
|
|
* on with our lives.
|
|
*/
|
|
|
|
void gx_singlestep_handle(struct pt_regs *regs, int fault_num)
|
|
{
|
|
unsigned long *ss_pc = &__get_cpu_var(ss_saved_pc);
|
|
struct thread_info *info = (void *)current_thread_info();
|
|
int is_single_step = test_ti_thread_flag(info, TIF_SINGLESTEP);
|
|
unsigned long control = __insn_mfspr(SPR_SINGLE_STEP_CONTROL_K);
|
|
|
|
if (is_single_step == 0) {
|
|
__insn_mtspr(SPR_SINGLE_STEP_EN_K_K, 0);
|
|
|
|
} else if ((*ss_pc != regs->pc) ||
|
|
(!(control & SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK))) {
|
|
|
|
ptrace_notify(SIGTRAP);
|
|
control |= SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK;
|
|
control |= SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK;
|
|
__insn_mtspr(SPR_SINGLE_STEP_CONTROL_K, control);
|
|
}
|
|
}
|
|
|
|
|
|
/*
|
|
* Called from need_singlestep. Set up the control registers and the enable
|
|
* register, then return back.
|
|
*/
|
|
|
|
void single_step_once(struct pt_regs *regs)
|
|
{
|
|
unsigned long *ss_pc = &__get_cpu_var(ss_saved_pc);
|
|
unsigned long control = __insn_mfspr(SPR_SINGLE_STEP_CONTROL_K);
|
|
|
|
*ss_pc = regs->pc;
|
|
control |= SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK;
|
|
control |= SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK;
|
|
__insn_mtspr(SPR_SINGLE_STEP_CONTROL_K, control);
|
|
__insn_mtspr(SPR_SINGLE_STEP_EN_K_K, 1 << USER_PL);
|
|
}
|
|
|
|
void single_step_execve(void)
|
|
{
|
|
/* Nothing */
|
|
}
|
|
|
|
#endif /* !__tilegx__ */
|