298 строки
7.8 KiB
C
298 строки
7.8 KiB
C
#ifndef _ASM_IO_H
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#define _ASM_IO_H
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/*
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* This file contains the definitions for the x86 IO instructions
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* inb/inw/inl/outb/outw/outl and the "string versions" of the same
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* (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
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* versions of the single-IO instructions (inb_p/inw_p/..).
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*
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* This file is not meant to be obfuscating: it's just complicated
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* to (a) handle it all in a way that makes gcc able to optimize it
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* as well as possible and (b) trying to avoid writing the same thing
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* over and over again with slight variations and possibly making a
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* mistake somewhere.
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*/
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/*
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* Thanks to James van Artsdalen for a better timing-fix than
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* the two short jumps: using outb's to a nonexistent port seems
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* to guarantee better timings even on fast machines.
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*
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* On the other hand, I'd like to be sure of a non-existent port:
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* I feel a bit unsafe about using 0x80 (should be safe, though)
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*
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* Linus
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*/
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/*
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* Bit simplified and optimized by Jan Hubicka
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* Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
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*
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* isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
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* isa_read[wl] and isa_write[wl] fixed
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* - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
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*/
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extern void native_io_delay(void);
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extern int io_delay_type;
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extern void io_delay_init(void);
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#if defined(CONFIG_PARAVIRT)
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#include <asm/paravirt.h>
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#else
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static inline void slow_down_io(void)
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{
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native_io_delay();
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#ifdef REALLY_SLOW_IO
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native_io_delay();
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native_io_delay();
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native_io_delay();
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#endif
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}
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#endif
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/*
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* Talk about misusing macros..
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*/
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#define __OUT1(s,x) \
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static inline void out##s(unsigned x value, unsigned short port) {
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#define __OUT2(s,s1,s2) \
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__asm__ __volatile__ ("out" #s " %" s1 "0,%" s2 "1"
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#ifndef REALLY_SLOW_IO
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#define REALLY_SLOW_IO
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#define UNSET_REALLY_SLOW_IO
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#endif
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#define __OUT(s,s1,x) \
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__OUT1(s,x) __OUT2(s,s1,"w") : : "a" (value), "Nd" (port)); } \
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__OUT1(s##_p, x) __OUT2(s, s1, "w") : : "a" (value), "Nd" (port)); \
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slow_down_io(); }
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#define __IN1(s) \
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static inline RETURN_TYPE in##s(unsigned short port) { RETURN_TYPE _v;
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#define __IN2(s,s1,s2) \
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__asm__ __volatile__ ("in" #s " %" s2 "1,%" s1 "0"
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#define __IN(s,s1,i...) \
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__IN1(s) __IN2(s, s1, "w") : "=a" (_v) : "Nd" (port), ##i); return _v; } \
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__IN1(s##_p) __IN2(s, s1, "w") : "=a" (_v) : "Nd" (port), ##i); \
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slow_down_io(); return _v; }
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#ifdef UNSET_REALLY_SLOW_IO
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#undef REALLY_SLOW_IO
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#endif
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#define __INS(s) \
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static inline void ins##s(unsigned short port, void * addr, unsigned long count) \
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{ __asm__ __volatile__ ("rep ; ins" #s \
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: "=D" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); }
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#define __OUTS(s) \
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static inline void outs##s(unsigned short port, const void * addr, unsigned long count) \
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{ __asm__ __volatile__ ("rep ; outs" #s \
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: "=S" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); }
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#define RETURN_TYPE unsigned char
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__IN(b,"")
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#undef RETURN_TYPE
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#define RETURN_TYPE unsigned short
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__IN(w,"")
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#undef RETURN_TYPE
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#define RETURN_TYPE unsigned int
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__IN(l,"")
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#undef RETURN_TYPE
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__OUT(b,"b",char)
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__OUT(w,"w",short)
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__OUT(l,,int)
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__INS(b)
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__INS(w)
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__INS(l)
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__OUTS(b)
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__OUTS(w)
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__OUTS(l)
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#define IO_SPACE_LIMIT 0xffff
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#if defined(__KERNEL__) && defined(__x86_64__)
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#include <linux/vmalloc.h>
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#ifndef __i386__
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/*
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* Change virtual addresses to physical addresses and vv.
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* These are pretty trivial
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*/
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static inline unsigned long virt_to_phys(volatile void * address)
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{
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return __pa(address);
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}
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static inline void * phys_to_virt(unsigned long address)
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{
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return __va(address);
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}
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#endif
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/*
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* Change "struct page" to physical address.
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*/
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#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
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#include <asm-generic/iomap.h>
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extern void *early_ioremap(unsigned long addr, unsigned long size);
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extern void early_iounmap(void *addr, unsigned long size);
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/*
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* This one maps high address device memory and turns off caching for that area.
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* it's useful if some control registers are in such an area and write combining
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* or read caching is not desirable:
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*/
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extern void __iomem *ioremap_nocache(unsigned long offset, unsigned long size);
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extern void __iomem *ioremap_cache(unsigned long offset, unsigned long size);
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/*
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* The default ioremap() behavior is non-cached:
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*/
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static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
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{
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return ioremap_nocache(offset, size);
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}
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extern void iounmap(volatile void __iomem *addr);
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extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys);
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/*
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* ISA I/O bus memory addresses are 1:1 with the physical address.
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*/
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#define isa_virt_to_bus virt_to_phys
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#define isa_page_to_bus page_to_phys
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#define isa_bus_to_virt phys_to_virt
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/*
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* However PCI ones are not necessarily 1:1 and therefore these interfaces
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* are forbidden in portable PCI drivers.
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*
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* Allow them on x86 for legacy drivers, though.
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*/
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#define virt_to_bus virt_to_phys
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#define bus_to_virt phys_to_virt
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/*
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* readX/writeX() are used to access memory mapped devices. On some
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* architectures the memory mapped IO stuff needs to be accessed
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* differently. On the x86 architecture, we just read/write the
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* memory location directly.
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*/
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static inline __u8 __readb(const volatile void __iomem *addr)
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{
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return *(__force volatile __u8 *)addr;
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}
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static inline __u16 __readw(const volatile void __iomem *addr)
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{
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return *(__force volatile __u16 *)addr;
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}
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static __always_inline __u32 __readl(const volatile void __iomem *addr)
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{
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return *(__force volatile __u32 *)addr;
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}
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static inline __u64 __readq(const volatile void __iomem *addr)
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{
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return *(__force volatile __u64 *)addr;
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}
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#define readb(x) __readb(x)
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#define readw(x) __readw(x)
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#define readl(x) __readl(x)
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#define readq(x) __readq(x)
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#define readb_relaxed(a) readb(a)
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#define readw_relaxed(a) readw(a)
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#define readl_relaxed(a) readl(a)
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#define readq_relaxed(a) readq(a)
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#define __raw_readb readb
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#define __raw_readw readw
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#define __raw_readl readl
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#define __raw_readq readq
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#define mmiowb()
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static inline void __writel(__u32 b, volatile void __iomem *addr)
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{
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*(__force volatile __u32 *)addr = b;
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}
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static inline void __writeq(__u64 b, volatile void __iomem *addr)
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{
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*(__force volatile __u64 *)addr = b;
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}
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static inline void __writeb(__u8 b, volatile void __iomem *addr)
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{
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*(__force volatile __u8 *)addr = b;
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}
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static inline void __writew(__u16 b, volatile void __iomem *addr)
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{
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*(__force volatile __u16 *)addr = b;
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}
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#define writeq(val,addr) __writeq((val),(addr))
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#define writel(val,addr) __writel((val),(addr))
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#define writew(val,addr) __writew((val),(addr))
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#define writeb(val,addr) __writeb((val),(addr))
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#define __raw_writeb writeb
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#define __raw_writew writew
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#define __raw_writel writel
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#define __raw_writeq writeq
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void __memcpy_fromio(void*,unsigned long,unsigned);
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void __memcpy_toio(unsigned long,const void*,unsigned);
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static inline void memcpy_fromio(void *to, const volatile void __iomem *from, unsigned len)
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{
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__memcpy_fromio(to,(unsigned long)from,len);
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}
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static inline void memcpy_toio(volatile void __iomem *to, const void *from, unsigned len)
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{
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__memcpy_toio((unsigned long)to,from,len);
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}
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void memset_io(volatile void __iomem *a, int b, size_t c);
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/*
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* ISA space is 'always mapped' on a typical x86 system, no need to
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* explicitly ioremap() it. The fact that the ISA IO space is mapped
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* to PAGE_OFFSET is pure coincidence - it does not mean ISA values
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* are physical addresses. The following constant pointer can be
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* used as the IO-area pointer (it can be iounmapped as well, so the
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* analogy with PCI is quite large):
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*/
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#define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET))
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#define flush_write_buffers()
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extern int iommu_bio_merge;
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#define BIO_VMERGE_BOUNDARY iommu_bio_merge
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/*
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* Convert a physical pointer to a virtual kernel pointer for /dev/mem
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* access
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*/
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#define xlate_dev_mem_ptr(p) __va(p)
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/*
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* Convert a virtual cached pointer to an uncached pointer
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*/
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#define xlate_dev_kmem_ptr(p) p
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#endif /* __KERNEL__ */
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#endif
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