175 строки
5.4 KiB
C
175 строки
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* vineetg: May 2011
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* -Refactored get_new_mmu_context( ) to only handle live-mm.
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* retiring-mm handled in other hooks
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*
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* Vineetg: March 25th, 2008: Bug #92690
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* -Major rewrite of Core ASID allocation routine get_new_mmu_context
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*
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* Amit Bhor, Sameer Dhavale: Codito Technologies 2004
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*/
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#ifndef _ASM_ARC_MMU_CONTEXT_H
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#define _ASM_ARC_MMU_CONTEXT_H
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#include <linux/sched/mm.h>
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#include <asm/tlb.h>
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#include <asm-generic/mm_hooks.h>
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/* ARC ASID Management
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*
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* MMU tags TLBs with an 8-bit ASID, avoiding need to flush the TLB on
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* context-switch.
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*
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* ASID is managed per cpu, so task threads across CPUs can have different
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* ASID. Global ASID management is needed if hardware supports TLB shootdown
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* and/or shared TLB across cores, which ARC doesn't.
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*
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* Each task is assigned unique ASID, with a simple round-robin allocator
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* tracked in @asid_cpu. When 8-bit value rolls over,a new cycle is started
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* over from 0, and TLB is flushed
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*
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* A new allocation cycle, post rollover, could potentially reassign an ASID
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* to a different task. Thus the rule is to refresh the ASID in a new cycle.
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* The 32 bit @asid_cpu (and mm->asid) have 8 bits MMU PID and rest 24 bits
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* serve as cycle/generation indicator and natural 32 bit unsigned math
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* automagically increments the generation when lower 8 bits rollover.
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*/
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#define MM_CTXT_ASID_MASK 0x000000ff /* MMU PID reg :8 bit PID */
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#define MM_CTXT_CYCLE_MASK (~MM_CTXT_ASID_MASK)
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#define MM_CTXT_FIRST_CYCLE (MM_CTXT_ASID_MASK + 1)
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#define MM_CTXT_NO_ASID 0UL
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#define asid_mm(mm, cpu) mm->context.asid[cpu]
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#define hw_pid(mm, cpu) (asid_mm(mm, cpu) & MM_CTXT_ASID_MASK)
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DECLARE_PER_CPU(unsigned int, asid_cache);
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#define asid_cpu(cpu) per_cpu(asid_cache, cpu)
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/*
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* Get a new ASID if task doesn't have a valid one (unalloc or from prev cycle)
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* Also set the MMU PID register to existing/updated ASID
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*/
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static inline void get_new_mmu_context(struct mm_struct *mm)
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{
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const unsigned int cpu = smp_processor_id();
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unsigned long flags;
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local_irq_save(flags);
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/*
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* Move to new ASID if it was not from current alloc-cycle/generation.
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* This is done by ensuring that the generation bits in both mm->ASID
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* and cpu's ASID counter are exactly same.
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*
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* Note: Callers needing new ASID unconditionally, independent of
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* generation, e.g. local_flush_tlb_mm() for forking parent,
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* first need to destroy the context, setting it to invalid
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* value.
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*/
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if (!((asid_mm(mm, cpu) ^ asid_cpu(cpu)) & MM_CTXT_CYCLE_MASK))
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goto set_hw;
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/* move to new ASID and handle rollover */
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if (unlikely(!(++asid_cpu(cpu) & MM_CTXT_ASID_MASK))) {
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local_flush_tlb_all();
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/*
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* Above check for rollover of 8 bit ASID in 32 bit container.
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* If the container itself wrapped around, set it to a non zero
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* "generation" to distinguish from no context
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*/
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if (!asid_cpu(cpu))
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asid_cpu(cpu) = MM_CTXT_FIRST_CYCLE;
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}
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/* Assign new ASID to tsk */
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asid_mm(mm, cpu) = asid_cpu(cpu);
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set_hw:
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mmu_setup_asid(mm, hw_pid(mm, cpu));
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local_irq_restore(flags);
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}
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/*
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* Initialize the context related info for a new mm_struct
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* instance.
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*/
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#define init_new_context init_new_context
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static inline int
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init_new_context(struct task_struct *tsk, struct mm_struct *mm)
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{
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int i;
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for_each_possible_cpu(i)
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asid_mm(mm, i) = MM_CTXT_NO_ASID;
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return 0;
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}
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#define destroy_context destroy_context
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static inline void destroy_context(struct mm_struct *mm)
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{
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unsigned long flags;
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/* Needed to elide CONFIG_DEBUG_PREEMPT warning */
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local_irq_save(flags);
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asid_mm(mm, smp_processor_id()) = MM_CTXT_NO_ASID;
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local_irq_restore(flags);
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}
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/* Prepare the MMU for task: setup PID reg with allocated ASID
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If task doesn't have an ASID (never alloc or stolen, get a new ASID)
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*/
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static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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const int cpu = smp_processor_id();
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/*
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* Note that the mm_cpumask is "aggregating" only, we don't clear it
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* for the switched-out task, unlike some other arches.
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* It is used to enlist cpus for sending TLB flush IPIs and not sending
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* it to CPUs where a task once ran-on, could cause stale TLB entry
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* re-use, specially for a multi-threaded task.
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* e.g. T1 runs on C1, migrates to C3. T2 running on C2 munmaps.
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* For a non-aggregating mm_cpumask, IPI not sent C1, and if T1
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* were to re-migrate to C1, it could access the unmapped region
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* via any existing stale TLB entries.
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*/
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cpumask_set_cpu(cpu, mm_cpumask(next));
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mmu_setup_pgd(next, next->pgd);
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get_new_mmu_context(next);
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}
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/*
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* activate_mm defaults (in asm-generic) to switch_mm and is called at the
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* time of execve() to get a new ASID Note the subtlety here:
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* get_new_mmu_context() behaves differently here vs. in switch_mm(). Here
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* it always returns a new ASID, because mm has an unallocated "initial"
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* value, while in latter, it moves to a new ASID, only if it was
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* unallocated
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*/
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/* it seemed that deactivate_mm( ) is a reasonable place to do book-keeping
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* for retiring-mm. However destroy_context( ) still needs to do that because
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* between mm_release( ) = >deactive_mm( ) and
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* mmput => .. => __mmdrop( ) => destroy_context( )
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* there is a good chance that task gets sched-out/in, making it's ASID valid
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* again (this teased me for a whole day).
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*/
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#include <asm-generic/mmu_context.h>
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#endif /* __ASM_ARC_MMU_CONTEXT_H */
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