869 строки
21 KiB
C
869 строки
21 KiB
C
/*
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* OMAP2/3 clockdomains
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*
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* Copyright (C) 2008-2009 Texas Instruments, Inc.
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* Copyright (C) 2008-2010 Nokia Corporation
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*
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* Paul Walmsley, Jouni Högander
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*
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* This file contains clockdomains and clockdomain wakeup/sleep
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* dependencies for the OMAP2/3 chips. Some notes:
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*
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* A useful validation rule for struct clockdomain: Any clockdomain
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* referenced by a wkdep_srcs or sleepdep_srcs array must have a
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* dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really just
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* software-controllable dependencies. Non-software-controllable
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* dependencies do exist, but they are not encoded below (yet).
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*
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* 24xx does not support programmable sleep dependencies (SLEEPDEP)
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*
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* The overly-specific dep_bit names are due to a bit name collision
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* with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
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* value are the same for all powerdomains: 2
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*
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* XXX should dep_bit be a mask, so we can test to see if it is 0 as a
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* sanity check?
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* XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
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*/
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/*
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* To-Do List
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* -> Port the Sleep/Wakeup dependencies for the domains
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* from the Power domain framework
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include "clockdomain.h"
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#include "prm2xxx_3xxx.h"
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#include "cm2xxx_3xxx.h"
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#include "cm-regbits-24xx.h"
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#include "cm-regbits-34xx.h"
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#include "cm-regbits-44xx.h"
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#include "prm-regbits-24xx.h"
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#include "prm-regbits-34xx.h"
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/*
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* Clockdomain dependencies for wkdeps/sleepdeps
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*
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* XXX Hardware dependencies (e.g., dependencies that cannot be
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* changed in software) are not included here yet, but should be.
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*/
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/* OMAP2/3-common wakeup dependencies */
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/*
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* 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP
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* 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
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* 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
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* These can share data since they will never be present simultaneously
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* on the same device.
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*/
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static struct clkdm_dep gfx_sgx_wkdeps[] = {
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{
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.clkdm_name = "core_l3_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
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},
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{
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.clkdm_name = "core_l4_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
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},
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{
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.clkdm_name = "iva2_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "mpu_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
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CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "wkup_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
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CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/* 24XX-specific possible dependencies */
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#ifdef CONFIG_ARCH_OMAP2
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/* Wakeup dependency source arrays */
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/* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */
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static struct clkdm_dep dsp_24xx_wkdeps[] = {
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{
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.clkdm_name = "core_l3_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
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},
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{
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.clkdm_name = "core_l4_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
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},
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{
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.clkdm_name = "mpu_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
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},
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{
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.clkdm_name = "wkup_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
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},
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{ NULL },
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};
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/*
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* 2420 PM_WKDEP_MPU: CORE, DSP, WKUP
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* 2430 adds MDM
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*/
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static struct clkdm_dep mpu_24xx_wkdeps[] = {
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{
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.clkdm_name = "core_l3_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
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},
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{
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.clkdm_name = "core_l4_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
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},
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{
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.clkdm_name = "dsp_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
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},
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{
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.clkdm_name = "wkup_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
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},
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{
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.clkdm_name = "mdm_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
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},
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{ NULL },
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};
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/*
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* 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP
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* 2430 adds MDM
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*/
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static struct clkdm_dep core_24xx_wkdeps[] = {
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{
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.clkdm_name = "dsp_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
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},
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{
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.clkdm_name = "gfx_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
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},
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{
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.clkdm_name = "mpu_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
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},
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{
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.clkdm_name = "wkup_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
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},
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{
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.clkdm_name = "mdm_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
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},
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{ NULL },
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};
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#endif /* CONFIG_ARCH_OMAP2 */
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/* 2430-specific possible wakeup dependencies */
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#ifdef CONFIG_SOC_OMAP2430
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/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
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static struct clkdm_dep mdm_2430_wkdeps[] = {
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{
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.clkdm_name = "core_l3_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
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},
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{
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.clkdm_name = "core_l4_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
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},
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{
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.clkdm_name = "mpu_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
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},
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{
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.clkdm_name = "wkup_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
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},
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{ NULL },
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};
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#endif /* CONFIG_SOC_OMAP2430 */
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/* OMAP3-specific possible dependencies */
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#ifdef CONFIG_ARCH_OMAP3
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/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
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static struct clkdm_dep per_wkdeps[] = {
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{
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.clkdm_name = "core_l3_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "core_l4_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "iva2_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "mpu_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "wkup_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
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static struct clkdm_dep usbhost_wkdeps[] = {
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{
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.clkdm_name = "core_l3_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "core_l4_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "iva2_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "mpu_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "wkup_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
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static struct clkdm_dep mpu_3xxx_wkdeps[] = {
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{
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.clkdm_name = "core_l3_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "core_l4_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "iva2_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "dss_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "per_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
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static struct clkdm_dep iva2_wkdeps[] = {
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{
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.clkdm_name = "core_l3_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "core_l4_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "mpu_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "wkup_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "dss_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "per_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
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static struct clkdm_dep cam_wkdeps[] = {
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{
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.clkdm_name = "iva2_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "mpu_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "wkup_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
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static struct clkdm_dep dss_wkdeps[] = {
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{
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.clkdm_name = "iva2_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "mpu_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "wkup_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/* 3430: PM_WKDEP_NEON: MPU */
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static struct clkdm_dep neon_wkdeps[] = {
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{
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.clkdm_name = "mpu_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/* Sleep dependency source arrays for OMAP3-specific clkdms */
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/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
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static struct clkdm_dep dss_sleepdeps[] = {
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{
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.clkdm_name = "mpu_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "iva2_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
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static struct clkdm_dep per_sleepdeps[] = {
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{
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.clkdm_name = "mpu_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "iva2_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
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static struct clkdm_dep usbhost_sleepdeps[] = {
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{
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.clkdm_name = "mpu_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.clkdm_name = "iva2_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/* 3430: CM_SLEEPDEP_CAM: MPU */
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static struct clkdm_dep cam_sleepdeps[] = {
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{
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.clkdm_name = "mpu_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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/*
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* 3430ES1: CM_SLEEPDEP_GFX: MPU
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* 3430ES2: CM_SLEEPDEP_SGX: MPU
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* These can share data since they will never be present simultaneously
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* on the same device.
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*/
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static struct clkdm_dep gfx_sgx_sleepdeps[] = {
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{
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.clkdm_name = "mpu_clkdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{ NULL },
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};
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#endif /* CONFIG_ARCH_OMAP3 */
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/*
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* OMAP2/3-common clockdomains
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*
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* Even though the 2420 has a single PRCM module from the
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* interconnect's perspective, internally it does appear to have
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* separate PRM and CM clockdomains. The usual test case is
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* sys_clkout/sys_clkout2.
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*/
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/* This is an implicit clockdomain - it is never defined as such in TRM */
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static struct clockdomain wkup_clkdm = {
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.name = "wkup_clkdm",
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.pwrdm = { .name = "wkup_pwrdm" },
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.dep_bit = OMAP_EN_WKUP_SHIFT,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
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};
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static struct clockdomain prm_clkdm = {
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.name = "prm_clkdm",
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.pwrdm = { .name = "wkup_pwrdm" },
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
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};
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static struct clockdomain cm_clkdm = {
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.name = "cm_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
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};
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/*
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* 2420-only clockdomains
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*/
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#if defined(CONFIG_SOC_OMAP2420)
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static struct clockdomain mpu_2420_clkdm = {
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.name = "mpu_clkdm",
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.pwrdm = { .name = "mpu_pwrdm" },
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.flags = CLKDM_CAN_HWSUP,
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.wkdep_srcs = mpu_24xx_wkdeps,
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.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
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};
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static struct clockdomain iva1_2420_clkdm = {
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.name = "iva1_clkdm",
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.pwrdm = { .name = "dsp_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
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.wkdep_srcs = dsp_24xx_wkdeps,
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.clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
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};
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static struct clockdomain dsp_2420_clkdm = {
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.name = "dsp_clkdm",
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.pwrdm = { .name = "dsp_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
|
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
|
};
|
|
|
|
static struct clockdomain gfx_2420_clkdm = {
|
|
.name = "gfx_clkdm",
|
|
.pwrdm = { .name = "gfx_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
|
.wkdep_srcs = gfx_sgx_wkdeps,
|
|
.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
|
};
|
|
|
|
static struct clockdomain core_l3_2420_clkdm = {
|
|
.name = "core_l3_clkdm",
|
|
.pwrdm = { .name = "core_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP,
|
|
.wkdep_srcs = core_24xx_wkdeps,
|
|
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
|
};
|
|
|
|
static struct clockdomain core_l4_2420_clkdm = {
|
|
.name = "core_l4_clkdm",
|
|
.pwrdm = { .name = "core_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP,
|
|
.wkdep_srcs = core_24xx_wkdeps,
|
|
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
|
};
|
|
|
|
static struct clockdomain dss_2420_clkdm = {
|
|
.name = "dss_clkdm",
|
|
.pwrdm = { .name = "core_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP,
|
|
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
|
};
|
|
|
|
#endif /* CONFIG_SOC_OMAP2420 */
|
|
|
|
|
|
/*
|
|
* 2430-only clockdomains
|
|
*/
|
|
|
|
#if defined(CONFIG_SOC_OMAP2430)
|
|
|
|
static struct clockdomain mpu_2430_clkdm = {
|
|
.name = "mpu_clkdm",
|
|
.pwrdm = { .name = "mpu_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
|
.wkdep_srcs = mpu_24xx_wkdeps,
|
|
.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
|
};
|
|
|
|
/* Another case of bit name collisions between several registers: EN_MDM */
|
|
static struct clockdomain mdm_clkdm = {
|
|
.name = "mdm_clkdm",
|
|
.pwrdm = { .name = "mdm_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
|
.dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
|
|
.wkdep_srcs = mdm_2430_wkdeps,
|
|
.clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
|
};
|
|
|
|
static struct clockdomain dsp_2430_clkdm = {
|
|
.name = "dsp_clkdm",
|
|
.pwrdm = { .name = "dsp_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
|
.dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
|
|
.wkdep_srcs = dsp_24xx_wkdeps,
|
|
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
|
};
|
|
|
|
static struct clockdomain gfx_2430_clkdm = {
|
|
.name = "gfx_clkdm",
|
|
.pwrdm = { .name = "gfx_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
|
.wkdep_srcs = gfx_sgx_wkdeps,
|
|
.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
|
};
|
|
|
|
/*
|
|
* XXX add usecounting for clkdm dependencies, otherwise the presence
|
|
* of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
|
|
* could cause trouble
|
|
*/
|
|
static struct clockdomain core_l3_2430_clkdm = {
|
|
.name = "core_l3_clkdm",
|
|
.pwrdm = { .name = "core_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP,
|
|
.dep_bit = OMAP24XX_EN_CORE_SHIFT,
|
|
.wkdep_srcs = core_24xx_wkdeps,
|
|
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
|
};
|
|
|
|
/*
|
|
* XXX add usecounting for clkdm dependencies, otherwise the presence
|
|
* of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
|
|
* could cause trouble
|
|
*/
|
|
static struct clockdomain core_l4_2430_clkdm = {
|
|
.name = "core_l4_clkdm",
|
|
.pwrdm = { .name = "core_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP,
|
|
.dep_bit = OMAP24XX_EN_CORE_SHIFT,
|
|
.wkdep_srcs = core_24xx_wkdeps,
|
|
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
|
};
|
|
|
|
static struct clockdomain dss_2430_clkdm = {
|
|
.name = "dss_clkdm",
|
|
.pwrdm = { .name = "core_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP,
|
|
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
|
};
|
|
|
|
#endif /* CONFIG_SOC_OMAP2430 */
|
|
|
|
|
|
/*
|
|
* OMAP3 clockdomains
|
|
*/
|
|
|
|
#if defined(CONFIG_ARCH_OMAP3)
|
|
|
|
static struct clockdomain mpu_3xxx_clkdm = {
|
|
.name = "mpu_clkdm",
|
|
.pwrdm = { .name = "mpu_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
|
|
.dep_bit = OMAP3430_EN_MPU_SHIFT,
|
|
.wkdep_srcs = mpu_3xxx_wkdeps,
|
|
.clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
static struct clockdomain neon_clkdm = {
|
|
.name = "neon_clkdm",
|
|
.pwrdm = { .name = "neon_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
|
.wkdep_srcs = neon_wkdeps,
|
|
.clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
static struct clockdomain iva2_clkdm = {
|
|
.name = "iva2_clkdm",
|
|
.pwrdm = { .name = "iva2_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
|
.dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
|
|
.wkdep_srcs = iva2_wkdeps,
|
|
.clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
static struct clockdomain gfx_3430es1_clkdm = {
|
|
.name = "gfx_clkdm",
|
|
.pwrdm = { .name = "gfx_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
|
.wkdep_srcs = gfx_sgx_wkdeps,
|
|
.sleepdep_srcs = gfx_sgx_sleepdeps,
|
|
.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
|
|
};
|
|
|
|
static struct clockdomain sgx_clkdm = {
|
|
.name = "sgx_clkdm",
|
|
.pwrdm = { .name = "sgx_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
|
.wkdep_srcs = gfx_sgx_wkdeps,
|
|
.sleepdep_srcs = gfx_sgx_sleepdeps,
|
|
.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
|
|
};
|
|
|
|
/*
|
|
* The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
|
|
* then that information was removed from the 34xx ES2+ TRM. It is
|
|
* unclear whether the core is still there, but the clockdomain logic
|
|
* is there, and must be programmed to an appropriate state if the
|
|
* CORE clockdomain is to become inactive.
|
|
*/
|
|
static struct clockdomain d2d_clkdm = {
|
|
.name = "d2d_clkdm",
|
|
.pwrdm = { .name = "core_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
|
.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
/*
|
|
* XXX add usecounting for clkdm dependencies, otherwise the presence
|
|
* of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
|
|
* could cause trouble
|
|
*/
|
|
static struct clockdomain core_l3_3xxx_clkdm = {
|
|
.name = "core_l3_clkdm",
|
|
.pwrdm = { .name = "core_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP,
|
|
.dep_bit = OMAP3430_EN_CORE_SHIFT,
|
|
.clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
/*
|
|
* XXX add usecounting for clkdm dependencies, otherwise the presence
|
|
* of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
|
|
* could cause trouble
|
|
*/
|
|
static struct clockdomain core_l4_3xxx_clkdm = {
|
|
.name = "core_l4_clkdm",
|
|
.pwrdm = { .name = "core_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP,
|
|
.dep_bit = OMAP3430_EN_CORE_SHIFT,
|
|
.clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
/* Another case of bit name collisions between several registers: EN_DSS */
|
|
static struct clockdomain dss_3xxx_clkdm = {
|
|
.name = "dss_clkdm",
|
|
.pwrdm = { .name = "dss_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
|
.dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
|
|
.wkdep_srcs = dss_wkdeps,
|
|
.sleepdep_srcs = dss_sleepdeps,
|
|
.clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
static struct clockdomain cam_clkdm = {
|
|
.name = "cam_clkdm",
|
|
.pwrdm = { .name = "cam_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
|
.wkdep_srcs = cam_wkdeps,
|
|
.sleepdep_srcs = cam_sleepdeps,
|
|
.clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
static struct clockdomain usbhost_clkdm = {
|
|
.name = "usbhost_clkdm",
|
|
.pwrdm = { .name = "usbhost_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
|
.wkdep_srcs = usbhost_wkdeps,
|
|
.sleepdep_srcs = usbhost_sleepdeps,
|
|
.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
|
|
};
|
|
|
|
static struct clockdomain per_clkdm = {
|
|
.name = "per_clkdm",
|
|
.pwrdm = { .name = "per_pwrdm" },
|
|
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
|
.dep_bit = OMAP3430_EN_PER_SHIFT,
|
|
.wkdep_srcs = per_wkdeps,
|
|
.sleepdep_srcs = per_sleepdeps,
|
|
.clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
/*
|
|
* Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
|
|
* switched of even if sdti is in use
|
|
*/
|
|
static struct clockdomain emu_clkdm = {
|
|
.name = "emu_clkdm",
|
|
.pwrdm = { .name = "emu_pwrdm" },
|
|
.flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP,
|
|
.clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
static struct clockdomain dpll1_clkdm = {
|
|
.name = "dpll1_clkdm",
|
|
.pwrdm = { .name = "dpll1_pwrdm" },
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
static struct clockdomain dpll2_clkdm = {
|
|
.name = "dpll2_clkdm",
|
|
.pwrdm = { .name = "dpll2_pwrdm" },
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
static struct clockdomain dpll3_clkdm = {
|
|
.name = "dpll3_clkdm",
|
|
.pwrdm = { .name = "dpll3_pwrdm" },
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
static struct clockdomain dpll4_clkdm = {
|
|
.name = "dpll4_clkdm",
|
|
.pwrdm = { .name = "dpll4_pwrdm" },
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
|
};
|
|
|
|
static struct clockdomain dpll5_clkdm = {
|
|
.name = "dpll5_clkdm",
|
|
.pwrdm = { .name = "dpll5_pwrdm" },
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
|
|
};
|
|
|
|
#endif /* CONFIG_ARCH_OMAP3 */
|
|
|
|
/*
|
|
* Clockdomain hwsup dependencies (OMAP3 only)
|
|
*/
|
|
|
|
static struct clkdm_autodep clkdm_autodeps[] = {
|
|
{
|
|
.clkdm = { .name = "mpu_clkdm" },
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
|
},
|
|
{
|
|
.clkdm = { .name = "iva2_clkdm" },
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
|
},
|
|
{
|
|
.clkdm = { .name = NULL },
|
|
}
|
|
};
|
|
|
|
static struct clockdomain *clockdomains_omap2[] __initdata = {
|
|
&wkup_clkdm,
|
|
&cm_clkdm,
|
|
&prm_clkdm,
|
|
|
|
#ifdef CONFIG_SOC_OMAP2420
|
|
&mpu_2420_clkdm,
|
|
&iva1_2420_clkdm,
|
|
&dsp_2420_clkdm,
|
|
&gfx_2420_clkdm,
|
|
&core_l3_2420_clkdm,
|
|
&core_l4_2420_clkdm,
|
|
&dss_2420_clkdm,
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_OMAP2430
|
|
&mpu_2430_clkdm,
|
|
&mdm_clkdm,
|
|
&dsp_2430_clkdm,
|
|
&gfx_2430_clkdm,
|
|
&core_l3_2430_clkdm,
|
|
&core_l4_2430_clkdm,
|
|
&dss_2430_clkdm,
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP3
|
|
&mpu_3xxx_clkdm,
|
|
&neon_clkdm,
|
|
&iva2_clkdm,
|
|
&gfx_3430es1_clkdm,
|
|
&sgx_clkdm,
|
|
&d2d_clkdm,
|
|
&core_l3_3xxx_clkdm,
|
|
&core_l4_3xxx_clkdm,
|
|
&dss_3xxx_clkdm,
|
|
&cam_clkdm,
|
|
&usbhost_clkdm,
|
|
&per_clkdm,
|
|
&emu_clkdm,
|
|
&dpll1_clkdm,
|
|
&dpll2_clkdm,
|
|
&dpll3_clkdm,
|
|
&dpll4_clkdm,
|
|
&dpll5_clkdm,
|
|
#endif
|
|
NULL,
|
|
};
|
|
|
|
void __init omap2xxx_clockdomains_init(void)
|
|
{
|
|
clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap2_clkdm_operations);
|
|
}
|
|
|
|
void __init omap3xxx_clockdomains_init(void)
|
|
{
|
|
clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap3_clkdm_operations);
|
|
}
|