442 строки
11 KiB
C
442 строки
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2019 HiSilicon Limited. */
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#ifndef HISI_ACC_QM_H
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#define HISI_ACC_QM_H
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#include <linux/bitfield.h>
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#include <linux/debugfs.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#define QM_QNUM_V1 4096
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#define QM_QNUM_V2 1024
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#define QM_MAX_VFS_NUM_V2 63
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/* qm user domain */
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#define QM_ARUSER_M_CFG_1 0x100088
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#define AXUSER_SNOOP_ENABLE BIT(30)
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#define AXUSER_CMD_TYPE GENMASK(14, 12)
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#define AXUSER_CMD_SMMU_NORMAL 1
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#define AXUSER_NS BIT(6)
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#define AXUSER_NO BIT(5)
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#define AXUSER_FP BIT(4)
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#define AXUSER_SSV BIT(0)
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#define AXUSER_BASE (AXUSER_SNOOP_ENABLE | \
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FIELD_PREP(AXUSER_CMD_TYPE, \
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AXUSER_CMD_SMMU_NORMAL) | \
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AXUSER_NS | AXUSER_NO | AXUSER_FP)
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#define QM_ARUSER_M_CFG_ENABLE 0x100090
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#define ARUSER_M_CFG_ENABLE 0xfffffffe
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#define QM_AWUSER_M_CFG_1 0x100098
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#define QM_AWUSER_M_CFG_ENABLE 0x1000a0
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#define AWUSER_M_CFG_ENABLE 0xfffffffe
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#define QM_WUSER_M_CFG_ENABLE 0x1000a8
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#define WUSER_M_CFG_ENABLE 0xffffffff
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/* qm cache */
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#define QM_CACHE_CTL 0x100050
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#define SQC_CACHE_ENABLE BIT(0)
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#define CQC_CACHE_ENABLE BIT(1)
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#define SQC_CACHE_WB_ENABLE BIT(4)
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#define SQC_CACHE_WB_THRD GENMASK(10, 5)
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#define CQC_CACHE_WB_ENABLE BIT(11)
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#define CQC_CACHE_WB_THRD GENMASK(17, 12)
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#define QM_AXI_M_CFG 0x1000ac
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#define AXI_M_CFG 0xffff
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#define QM_AXI_M_CFG_ENABLE 0x1000b0
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#define AM_CFG_SINGLE_PORT_MAX_TRANS 0x300014
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#define AXI_M_CFG_ENABLE 0xffffffff
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#define QM_PEH_AXUSER_CFG 0x1000cc
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#define QM_PEH_AXUSER_CFG_ENABLE 0x1000d0
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#define PEH_AXUSER_CFG 0x401001
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#define PEH_AXUSER_CFG_ENABLE 0xffffffff
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#define QM_AXI_RRESP BIT(0)
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#define QM_AXI_BRESP BIT(1)
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#define QM_ECC_MBIT BIT(2)
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#define QM_ECC_1BIT BIT(3)
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#define QM_ACC_GET_TASK_TIMEOUT BIT(4)
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#define QM_ACC_DO_TASK_TIMEOUT BIT(5)
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#define QM_ACC_WB_NOT_READY_TIMEOUT BIT(6)
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#define QM_SQ_CQ_VF_INVALID BIT(7)
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#define QM_CQ_VF_INVALID BIT(8)
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#define QM_SQ_VF_INVALID BIT(9)
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#define QM_DB_TIMEOUT BIT(10)
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#define QM_OF_FIFO_OF BIT(11)
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#define QM_DB_RANDOM_INVALID BIT(12)
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#define QM_MAILBOX_TIMEOUT BIT(13)
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#define QM_FLR_TIMEOUT BIT(14)
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#define QM_BASE_NFE (QM_AXI_RRESP | QM_AXI_BRESP | QM_ECC_MBIT | \
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QM_ACC_GET_TASK_TIMEOUT | QM_DB_TIMEOUT | \
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QM_OF_FIFO_OF | QM_DB_RANDOM_INVALID | \
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QM_MAILBOX_TIMEOUT | QM_FLR_TIMEOUT)
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#define QM_BASE_CE QM_ECC_1BIT
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#define QM_Q_DEPTH 1024
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#define QM_MIN_QNUM 2
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#define HISI_ACC_SGL_SGE_NR_MAX 255
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#define QM_SHAPER_CFG 0x100164
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#define QM_SHAPER_ENABLE BIT(30)
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#define QM_SHAPER_TYPE1_OFFSET 10
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/* page number for queue file region */
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#define QM_DOORBELL_PAGE_NR 1
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/* uacce mode of the driver */
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#define UACCE_MODE_NOUACCE 0 /* don't use uacce */
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#define UACCE_MODE_SVA 1 /* use uacce sva mode */
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#define UACCE_MODE_DESC "0(default) means only register to crypto, 1 means both register to crypto and uacce"
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enum qm_stop_reason {
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QM_NORMAL,
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QM_SOFT_RESET,
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QM_FLR,
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};
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enum qm_state {
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QM_INIT = 0,
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QM_START,
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QM_CLOSE,
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QM_STOP,
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};
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enum qp_state {
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QP_INIT = 1,
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QP_START,
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QP_STOP,
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QP_CLOSE,
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};
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enum qm_hw_ver {
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QM_HW_UNKNOWN = -1,
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QM_HW_V1 = 0x20,
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QM_HW_V2 = 0x21,
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QM_HW_V3 = 0x30,
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};
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enum qm_fun_type {
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QM_HW_PF,
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QM_HW_VF,
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};
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enum qm_debug_file {
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CURRENT_QM,
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CURRENT_Q,
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CLEAR_ENABLE,
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DEBUG_FILE_NUM,
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};
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struct qm_dfx {
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atomic64_t err_irq_cnt;
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atomic64_t aeq_irq_cnt;
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atomic64_t abnormal_irq_cnt;
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atomic64_t create_qp_err_cnt;
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atomic64_t mb_err_cnt;
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};
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struct debugfs_file {
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enum qm_debug_file index;
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struct mutex lock;
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struct qm_debug *debug;
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};
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struct qm_debug {
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u32 curr_qm_qp_num;
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u32 sqe_mask_offset;
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u32 sqe_mask_len;
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struct qm_dfx dfx;
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struct dentry *debug_root;
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struct dentry *qm_d;
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struct debugfs_file files[DEBUG_FILE_NUM];
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};
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struct qm_shaper_factor {
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u32 func_qos;
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u64 cir_b;
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u64 cir_u;
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u64 cir_s;
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u64 cbs_s;
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};
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struct qm_dma {
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void *va;
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dma_addr_t dma;
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size_t size;
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};
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struct hisi_qm_status {
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u32 eq_head;
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bool eqc_phase;
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u32 aeq_head;
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bool aeqc_phase;
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atomic_t flags;
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int stop_reason;
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};
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struct hisi_qm;
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struct hisi_qm_err_info {
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char *acpi_rst;
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u32 msi_wr_port;
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u32 ecc_2bits_mask;
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u32 dev_ce_mask;
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u32 ce;
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u32 nfe;
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u32 fe;
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};
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struct hisi_qm_err_status {
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u32 is_qm_ecc_mbit;
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u32 is_dev_ecc_mbit;
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};
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struct hisi_qm_err_ini {
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int (*hw_init)(struct hisi_qm *qm);
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void (*hw_err_enable)(struct hisi_qm *qm);
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void (*hw_err_disable)(struct hisi_qm *qm);
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u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);
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void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts);
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void (*open_axi_master_ooo)(struct hisi_qm *qm);
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void (*close_axi_master_ooo)(struct hisi_qm *qm);
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void (*open_sva_prefetch)(struct hisi_qm *qm);
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void (*close_sva_prefetch)(struct hisi_qm *qm);
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void (*log_dev_hw_err)(struct hisi_qm *qm, u32 err_sts);
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void (*err_info_init)(struct hisi_qm *qm);
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};
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struct hisi_qm_list {
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struct mutex lock;
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struct list_head list;
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int (*register_to_crypto)(struct hisi_qm *qm);
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void (*unregister_from_crypto)(struct hisi_qm *qm);
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};
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struct hisi_qm {
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enum qm_hw_ver ver;
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enum qm_fun_type fun_type;
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const char *dev_name;
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struct pci_dev *pdev;
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void __iomem *io_base;
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void __iomem *db_io_base;
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u32 sqe_size;
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u32 qp_base;
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u32 qp_num;
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u32 qp_in_used;
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u32 ctrl_qp_num;
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u32 max_qp_num;
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u32 vfs_num;
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u32 db_interval;
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struct list_head list;
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struct hisi_qm_list *qm_list;
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struct qm_dma qdma;
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struct qm_sqc *sqc;
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struct qm_cqc *cqc;
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struct qm_eqe *eqe;
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struct qm_aeqe *aeqe;
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dma_addr_t sqc_dma;
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dma_addr_t cqc_dma;
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dma_addr_t eqe_dma;
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dma_addr_t aeqe_dma;
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struct hisi_qm_status status;
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const struct hisi_qm_err_ini *err_ini;
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struct hisi_qm_err_info err_info;
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struct hisi_qm_err_status err_status;
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unsigned long misc_ctl; /* driver removing and reset sched */
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struct rw_semaphore qps_lock;
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struct idr qp_idr;
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struct hisi_qp *qp_array;
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struct mutex mailbox_lock;
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const struct hisi_qm_hw_ops *ops;
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struct qm_debug debug;
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u32 error_mask;
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struct workqueue_struct *wq;
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struct work_struct work;
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struct work_struct rst_work;
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struct work_struct cmd_process;
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const char *algs;
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bool use_sva;
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bool is_frozen;
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/* doorbell isolation enable */
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bool use_db_isolation;
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resource_size_t phys_base;
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resource_size_t db_phys_base;
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struct uacce_device *uacce;
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int mode;
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struct qm_shaper_factor *factor;
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u32 mb_qos;
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u32 type_rate;
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};
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struct hisi_qp_status {
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atomic_t used;
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u16 sq_tail;
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u16 cq_head;
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bool cqc_phase;
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atomic_t flags;
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};
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struct hisi_qp_ops {
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int (*fill_sqe)(void *sqe, void *q_parm, void *d_parm);
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};
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struct hisi_qp {
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u32 qp_id;
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u8 alg_type;
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u8 req_type;
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struct qm_dma qdma;
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void *sqe;
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struct qm_cqe *cqe;
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dma_addr_t sqe_dma;
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dma_addr_t cqe_dma;
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struct hisi_qp_status qp_status;
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struct hisi_qp_ops *hw_ops;
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void *qp_ctx;
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void (*req_cb)(struct hisi_qp *qp, void *data);
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void (*event_cb)(struct hisi_qp *qp);
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struct hisi_qm *qm;
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bool is_resetting;
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bool is_in_kernel;
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u16 pasid;
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struct uacce_queue *uacce_q;
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};
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static inline int q_num_set(const char *val, const struct kernel_param *kp,
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unsigned int device)
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{
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struct pci_dev *pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI,
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device, NULL);
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u32 n, q_num;
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int ret;
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if (!val)
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return -EINVAL;
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if (!pdev) {
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q_num = min_t(u32, QM_QNUM_V1, QM_QNUM_V2);
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pr_info("No device found currently, suppose queue number is %u\n",
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q_num);
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} else {
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if (pdev->revision == QM_HW_V1)
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q_num = QM_QNUM_V1;
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else
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q_num = QM_QNUM_V2;
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}
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ret = kstrtou32(val, 10, &n);
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if (ret || n < QM_MIN_QNUM || n > q_num)
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return -EINVAL;
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return param_set_int(val, kp);
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}
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static inline int vfs_num_set(const char *val, const struct kernel_param *kp)
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{
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u32 n;
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int ret;
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if (!val)
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return -EINVAL;
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ret = kstrtou32(val, 10, &n);
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if (ret < 0)
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return ret;
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if (n > QM_MAX_VFS_NUM_V2)
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return -EINVAL;
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return param_set_int(val, kp);
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}
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static inline int mode_set(const char *val, const struct kernel_param *kp)
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{
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u32 n;
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int ret;
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if (!val)
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return -EINVAL;
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ret = kstrtou32(val, 10, &n);
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if (ret != 0 || (n != UACCE_MODE_SVA &&
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n != UACCE_MODE_NOUACCE))
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return -EINVAL;
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return param_set_int(val, kp);
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}
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static inline int uacce_mode_set(const char *val, const struct kernel_param *kp)
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{
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return mode_set(val, kp);
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}
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static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
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{
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INIT_LIST_HEAD(&qm_list->list);
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mutex_init(&qm_list->lock);
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}
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int hisi_qm_init(struct hisi_qm *qm);
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void hisi_qm_uninit(struct hisi_qm *qm);
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int hisi_qm_start(struct hisi_qm *qm);
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int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r);
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struct hisi_qp *hisi_qm_create_qp(struct hisi_qm *qm, u8 alg_type);
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int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
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int hisi_qm_stop_qp(struct hisi_qp *qp);
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void hisi_qm_release_qp(struct hisi_qp *qp);
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int hisi_qp_send(struct hisi_qp *qp, const void *msg);
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int hisi_qm_get_free_qp_num(struct hisi_qm *qm);
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int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number);
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void hisi_qm_debug_init(struct hisi_qm *qm);
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enum qm_hw_ver hisi_qm_get_hw_version(struct pci_dev *pdev);
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void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
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int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs);
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int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen);
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int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs);
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void hisi_qm_dev_err_init(struct hisi_qm *qm);
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void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
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pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
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pci_channel_state_t state);
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pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev);
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void hisi_qm_reset_prepare(struct pci_dev *pdev);
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void hisi_qm_reset_done(struct pci_dev *pdev);
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struct hisi_acc_sgl_pool;
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struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
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struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool,
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u32 index, dma_addr_t *hw_sgl_dma);
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void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
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struct hisi_acc_hw_sgl *hw_sgl);
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struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
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u32 count, u32 sge_nr);
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void hisi_acc_free_sgl_pool(struct device *dev,
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struct hisi_acc_sgl_pool *pool);
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int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
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u8 alg_type, int node, struct hisi_qp **qps);
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void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num);
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void hisi_qm_dev_shutdown(struct pci_dev *pdev);
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void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
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int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
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void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
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int hisi_qm_resume(struct device *dev);
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int hisi_qm_suspend(struct device *dev);
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void hisi_qm_pm_uninit(struct hisi_qm *qm);
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void hisi_qm_pm_init(struct hisi_qm *qm);
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int hisi_qm_get_dfx_access(struct hisi_qm *qm);
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void hisi_qm_put_dfx_access(struct hisi_qm *qm);
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void hisi_qm_regs_dump(struct seq_file *s, struct debugfs_regset32 *regset);
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#endif
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