717 строки
18 KiB
C
717 строки
18 KiB
C
/*
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* Intel 82975X Memory Controller kernel module
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* (C) 2007 aCarLab (India) Pvt. Ltd. (http://acarlab.com)
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* (C) 2007 jetzbroadband (http://jetzbroadband.com)
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* This file may be distributed under the terms of the
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* GNU General Public License.
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*
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* Written by Arvind R.
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* Copied from i82875p_edac.c source:
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <linux/edac.h>
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#include "edac_module.h"
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#define I82975X_REVISION " Ver: 1.0.0"
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#define EDAC_MOD_STR "i82975x_edac"
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#define i82975x_printk(level, fmt, arg...) \
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edac_printk(level, "i82975x", fmt, ##arg)
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#define i82975x_mc_printk(mci, level, fmt, arg...) \
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edac_mc_chipset_printk(mci, level, "i82975x", fmt, ##arg)
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#ifndef PCI_DEVICE_ID_INTEL_82975_0
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#define PCI_DEVICE_ID_INTEL_82975_0 0x277c
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#endif /* PCI_DEVICE_ID_INTEL_82975_0 */
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#define I82975X_NR_DIMMS 8
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#define I82975X_NR_CSROWS(nr_chans) (I82975X_NR_DIMMS / (nr_chans))
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/* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
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#define I82975X_EAP 0x58 /* Dram Error Address Pointer (32b)
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*
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* 31:7 128 byte cache-line address
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* 6:1 reserved
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* 0 0: CH0; 1: CH1
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*/
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#define I82975X_DERRSYN 0x5c /* Dram Error SYNdrome (8b)
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*
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* 7:0 DRAM ECC Syndrome
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*/
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#define I82975X_DES 0x5d /* Dram ERRor DeSTination (8b)
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* 0h: Processor Memory Reads
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* 1h:7h reserved
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* More - See Page 65 of Intel DocSheet.
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*/
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#define I82975X_ERRSTS 0xc8 /* Error Status Register (16b)
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*
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* 15:12 reserved
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* 11 Thermal Sensor Event
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* 10 reserved
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* 9 non-DRAM lock error (ndlock)
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* 8 Refresh Timeout
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* 7:2 reserved
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* 1 ECC UE (multibit DRAM error)
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* 0 ECC CE (singlebit DRAM error)
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*/
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/* Error Reporting is supported by 3 mechanisms:
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1. DMI SERR generation ( ERRCMD )
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2. SMI DMI generation ( SMICMD )
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3. SCI DMI generation ( SCICMD )
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NOTE: Only ONE of the three must be enabled
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*/
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#define I82975X_ERRCMD 0xca /* Error Command (16b)
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*
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* 15:12 reserved
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* 11 Thermal Sensor Event
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* 10 reserved
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* 9 non-DRAM lock error (ndlock)
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* 8 Refresh Timeout
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* 7:2 reserved
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* 1 ECC UE (multibit DRAM error)
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* 0 ECC CE (singlebit DRAM error)
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*/
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#define I82975X_SMICMD 0xcc /* Error Command (16b)
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*
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* 15:2 reserved
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* 1 ECC UE (multibit DRAM error)
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* 0 ECC CE (singlebit DRAM error)
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*/
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#define I82975X_SCICMD 0xce /* Error Command (16b)
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*
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* 15:2 reserved
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* 1 ECC UE (multibit DRAM error)
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* 0 ECC CE (singlebit DRAM error)
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*/
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#define I82975X_XEAP 0xfc /* Extended Dram Error Address Pointer (8b)
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*
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* 7:1 reserved
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* 0 Bit32 of the Dram Error Address
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*/
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#define I82975X_MCHBAR 0x44 /*
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*
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* 31:14 Base Addr of 16K memory-mapped
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* configuration space
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* 13:1 reserverd
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* 0 mem-mapped config space enable
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*/
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/* NOTE: Following addresses have to indexed using MCHBAR offset (44h, 32b) */
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/* Intel 82975x memory mapped register space */
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#define I82975X_DRB_SHIFT 25 /* fixed 32MiB grain */
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#define I82975X_DRB 0x100 /* DRAM Row Boundary (8b x 8)
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*
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* 7 set to 1 in highest DRB of
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* channel if 4GB in ch.
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* 6:2 upper boundary of rank in
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* 32MB grains
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* 1:0 set to 0
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*/
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#define I82975X_DRB_CH0R0 0x100
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#define I82975X_DRB_CH0R1 0x101
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#define I82975X_DRB_CH0R2 0x102
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#define I82975X_DRB_CH0R3 0x103
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#define I82975X_DRB_CH1R0 0x180
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#define I82975X_DRB_CH1R1 0x181
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#define I82975X_DRB_CH1R2 0x182
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#define I82975X_DRB_CH1R3 0x183
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#define I82975X_DRA 0x108 /* DRAM Row Attribute (4b x 8)
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* defines the PAGE SIZE to be used
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* for the rank
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* 7 reserved
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* 6:4 row attr of odd rank, i.e. 1
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* 3 reserved
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* 2:0 row attr of even rank, i.e. 0
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*
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* 000 = unpopulated
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* 001 = reserved
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* 010 = 4KiB
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* 011 = 8KiB
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* 100 = 16KiB
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* others = reserved
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*/
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#define I82975X_DRA_CH0R01 0x108
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#define I82975X_DRA_CH0R23 0x109
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#define I82975X_DRA_CH1R01 0x188
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#define I82975X_DRA_CH1R23 0x189
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#define I82975X_BNKARC 0x10e /* Type of device in each rank - Bank Arch (16b)
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*
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* 15:8 reserved
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* 7:6 Rank 3 architecture
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* 5:4 Rank 2 architecture
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* 3:2 Rank 1 architecture
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* 1:0 Rank 0 architecture
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*
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* 00 => 4 banks
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* 01 => 8 banks
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*/
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#define I82975X_C0BNKARC 0x10e
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#define I82975X_C1BNKARC 0x18e
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#define I82975X_DRC 0x120 /* DRAM Controller Mode0 (32b)
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*
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* 31:30 reserved
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* 29 init complete
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* 28:11 reserved, according to Intel
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* 22:21 number of channels
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* 00=1 01=2 in 82875
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* seems to be ECC mode
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* bits in 82975 in Asus
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* P5W
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* 19:18 Data Integ Mode
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* 00=none 01=ECC in 82875
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* 10:8 refresh mode
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* 7 reserved
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* 6:4 mode select
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* 3:2 reserved
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* 1:0 DRAM type 10=Second Revision
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* DDR2 SDRAM
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* 00, 01, 11 reserved
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*/
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#define I82975X_DRC_CH0M0 0x120
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#define I82975X_DRC_CH1M0 0x1A0
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#define I82975X_DRC_M1 0x124 /* DRAM Controller Mode1 (32b)
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* 31 0=Standard Address Map
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* 1=Enhanced Address Map
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* 30:0 reserved
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*/
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#define I82975X_DRC_CH0M1 0x124
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#define I82975X_DRC_CH1M1 0x1A4
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enum i82975x_chips {
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I82975X = 0,
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};
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struct i82975x_pvt {
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void __iomem *mch_window;
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};
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struct i82975x_dev_info {
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const char *ctl_name;
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};
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struct i82975x_error_info {
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u16 errsts;
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u32 eap;
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u8 des;
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u8 derrsyn;
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u16 errsts2;
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u8 chan; /* the channel is bit 0 of EAP */
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u8 xeap; /* extended eap bit */
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};
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static const struct i82975x_dev_info i82975x_devs[] = {
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[I82975X] = {
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.ctl_name = "i82975x"
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},
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};
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static struct pci_dev *mci_pdev; /* init dev: in case that AGP code has
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* already registered driver
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*/
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static int i82975x_registered = 1;
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static void i82975x_get_error_info(struct mem_ctl_info *mci,
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struct i82975x_error_info *info)
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{
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struct pci_dev *pdev;
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pdev = to_pci_dev(mci->pdev);
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/*
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* This is a mess because there is no atomic way to read all the
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* registers at once and the registers can transition from CE being
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* overwritten by UE.
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*/
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pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts);
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pci_read_config_dword(pdev, I82975X_EAP, &info->eap);
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pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap);
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pci_read_config_byte(pdev, I82975X_DES, &info->des);
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pci_read_config_byte(pdev, I82975X_DERRSYN, &info->derrsyn);
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pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts2);
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pci_write_bits16(pdev, I82975X_ERRSTS, 0x0003, 0x0003);
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/*
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* If the error is the same then we can for both reads then
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* the first set of reads is valid. If there is a change then
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* there is a CE no info and the second set of reads is valid
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* and should be UE info.
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*/
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if (!(info->errsts2 & 0x0003))
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return;
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if ((info->errsts ^ info->errsts2) & 0x0003) {
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pci_read_config_dword(pdev, I82975X_EAP, &info->eap);
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pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap);
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pci_read_config_byte(pdev, I82975X_DES, &info->des);
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pci_read_config_byte(pdev, I82975X_DERRSYN,
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&info->derrsyn);
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}
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}
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static int i82975x_process_error_info(struct mem_ctl_info *mci,
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struct i82975x_error_info *info, int handle_errors)
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{
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int row, chan;
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unsigned long offst, page;
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if (!(info->errsts2 & 0x0003))
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return 0;
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if (!handle_errors)
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return 1;
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if ((info->errsts ^ info->errsts2) & 0x0003) {
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
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-1, -1, -1, "UE overwrote CE", "");
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info->errsts = info->errsts2;
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}
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page = (unsigned long) info->eap;
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page >>= 1;
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if (info->xeap & 1)
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page |= 0x80000000;
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page >>= (PAGE_SHIFT - 1);
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row = edac_mc_find_csrow_by_page(mci, page);
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if (row == -1) {
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i82975x_mc_printk(mci, KERN_ERR, "error processing EAP:\n"
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"\tXEAP=%u\n"
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"\t EAP=0x%08x\n"
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"\tPAGE=0x%08x\n",
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(info->xeap & 1) ? 1 : 0, info->eap, (unsigned int) page);
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return 0;
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}
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chan = (mci->csrows[row]->nr_channels == 1) ? 0 : info->eap & 1;
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offst = info->eap
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& ((1 << PAGE_SHIFT) -
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(1 << mci->csrows[row]->channels[chan]->dimm->grain));
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if (info->errsts & 0x0002)
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
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page, offst, 0,
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row, -1, -1,
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"i82975x UE", "");
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else
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
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page, offst, info->derrsyn,
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row, chan ? chan : 0, -1,
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"i82975x CE", "");
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return 1;
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}
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static void i82975x_check(struct mem_ctl_info *mci)
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{
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struct i82975x_error_info info;
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edac_dbg(1, "MC%d\n", mci->mc_idx);
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i82975x_get_error_info(mci, &info);
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i82975x_process_error_info(mci, &info, 1);
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}
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/* Return 1 if dual channel mode is active. Else return 0. */
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static int dual_channel_active(void __iomem *mch_window)
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{
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/*
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* We treat interleaved-symmetric configuration as dual-channel - EAP's
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* bit-0 giving the channel of the error location.
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*
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* All other configurations are treated as single channel - the EAP's
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* bit-0 will resolve ok in symmetric area of mixed
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* (symmetric/asymmetric) configurations
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*/
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u8 drb[4][2];
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int row;
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int dualch;
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for (dualch = 1, row = 0; dualch && (row < 4); row++) {
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drb[row][0] = readb(mch_window + I82975X_DRB + row);
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drb[row][1] = readb(mch_window + I82975X_DRB + row + 0x80);
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dualch = dualch && (drb[row][0] == drb[row][1]);
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}
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return dualch;
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}
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static enum dev_type i82975x_dram_type(void __iomem *mch_window, int rank)
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{
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/*
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* ECC is possible on i92975x ONLY with DEV_X8
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*/
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return DEV_X8;
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}
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static void i82975x_init_csrows(struct mem_ctl_info *mci,
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struct pci_dev *pdev, void __iomem *mch_window)
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{
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struct csrow_info *csrow;
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unsigned long last_cumul_size;
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u8 value;
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u32 cumul_size, nr_pages;
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int index, chan;
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struct dimm_info *dimm;
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enum dev_type dtype;
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last_cumul_size = 0;
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/*
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* 82875 comment:
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* The dram row boundary (DRB) reg values are boundary address
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* for each DRAM row with a granularity of 32 or 64MB (single/dual
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* channel operation). DRB regs are cumulative; therefore DRB7 will
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* contain the total memory contained in all rows.
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*
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*/
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for (index = 0; index < mci->nr_csrows; index++) {
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csrow = mci->csrows[index];
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value = readb(mch_window + I82975X_DRB + index +
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((index >= 4) ? 0x80 : 0));
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cumul_size = value;
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cumul_size <<= (I82975X_DRB_SHIFT - PAGE_SHIFT);
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/*
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* Adjust cumul_size w.r.t number of channels
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*
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*/
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if (csrow->nr_channels > 1)
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cumul_size <<= 1;
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edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
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nr_pages = cumul_size - last_cumul_size;
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if (!nr_pages)
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continue;
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/*
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* Initialise dram labels
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* index values:
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* [0-7] for single-channel; i.e. csrow->nr_channels = 1
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* [0-3] for dual-channel; i.e. csrow->nr_channels = 2
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*/
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dtype = i82975x_dram_type(mch_window, index);
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for (chan = 0; chan < csrow->nr_channels; chan++) {
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dimm = mci->csrows[index]->channels[chan]->dimm;
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dimm->nr_pages = nr_pages / csrow->nr_channels;
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snprintf(csrow->channels[chan]->dimm->label, EDAC_MC_LABEL_LEN, "DIMM %c%d",
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(chan == 0) ? 'A' : 'B',
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index);
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dimm->grain = 1 << 7; /* 128Byte cache-line resolution */
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dimm->dtype = i82975x_dram_type(mch_window, index);
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dimm->mtype = MEM_DDR2; /* I82975x supports only DDR2 */
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dimm->edac_mode = EDAC_SECDED; /* only supported */
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}
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csrow->first_page = last_cumul_size;
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csrow->last_page = cumul_size - 1;
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last_cumul_size = cumul_size;
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}
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}
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/* #define i82975x_DEBUG_IOMEM */
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#ifdef i82975x_DEBUG_IOMEM
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static void i82975x_print_dram_timings(void __iomem *mch_window)
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{
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/*
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* The register meanings are from Intel specs;
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* (shows 13-5-5-5 for 800-DDR2)
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* Asus P5W Bios reports 15-5-4-4
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* What's your religion?
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*/
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static const int caslats[4] = { 5, 4, 3, 6 };
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u32 dtreg[2];
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dtreg[0] = readl(mch_window + 0x114);
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dtreg[1] = readl(mch_window + 0x194);
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i82975x_printk(KERN_INFO, "DRAM Timings : Ch0 Ch1\n"
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" RAS Active Min = %d %d\n"
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" CAS latency = %d %d\n"
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" RAS to CAS = %d %d\n"
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" RAS precharge = %d %d\n",
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(dtreg[0] >> 19 ) & 0x0f,
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(dtreg[1] >> 19) & 0x0f,
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caslats[(dtreg[0] >> 8) & 0x03],
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caslats[(dtreg[1] >> 8) & 0x03],
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((dtreg[0] >> 4) & 0x07) + 2,
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((dtreg[1] >> 4) & 0x07) + 2,
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(dtreg[0] & 0x07) + 2,
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(dtreg[1] & 0x07) + 2
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);
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}
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#endif
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static int i82975x_probe1(struct pci_dev *pdev, int dev_idx)
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{
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int rc = -ENODEV;
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struct mem_ctl_info *mci;
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struct edac_mc_layer layers[2];
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struct i82975x_pvt *pvt;
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void __iomem *mch_window;
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u32 mchbar;
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u32 drc[2];
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struct i82975x_error_info discard;
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int chans;
|
|
#ifdef i82975x_DEBUG_IOMEM
|
|
u8 c0drb[4];
|
|
u8 c1drb[4];
|
|
#endif
|
|
|
|
edac_dbg(0, "\n");
|
|
|
|
pci_read_config_dword(pdev, I82975X_MCHBAR, &mchbar);
|
|
if (!(mchbar & 1)) {
|
|
edac_dbg(3, "failed, MCHBAR disabled!\n");
|
|
goto fail0;
|
|
}
|
|
mchbar &= 0xffffc000; /* bits 31:14 used for 16K window */
|
|
mch_window = ioremap_nocache(mchbar, 0x1000);
|
|
if (!mch_window) {
|
|
edac_dbg(3, "error ioremapping MCHBAR!\n");
|
|
goto fail0;
|
|
}
|
|
|
|
#ifdef i82975x_DEBUG_IOMEM
|
|
i82975x_printk(KERN_INFO, "MCHBAR real = %0x, remapped = %p\n",
|
|
mchbar, mch_window);
|
|
|
|
c0drb[0] = readb(mch_window + I82975X_DRB_CH0R0);
|
|
c0drb[1] = readb(mch_window + I82975X_DRB_CH0R1);
|
|
c0drb[2] = readb(mch_window + I82975X_DRB_CH0R2);
|
|
c0drb[3] = readb(mch_window + I82975X_DRB_CH0R3);
|
|
c1drb[0] = readb(mch_window + I82975X_DRB_CH1R0);
|
|
c1drb[1] = readb(mch_window + I82975X_DRB_CH1R1);
|
|
c1drb[2] = readb(mch_window + I82975X_DRB_CH1R2);
|
|
c1drb[3] = readb(mch_window + I82975X_DRB_CH1R3);
|
|
i82975x_printk(KERN_INFO, "DRBCH0R0 = 0x%02x\n", c0drb[0]);
|
|
i82975x_printk(KERN_INFO, "DRBCH0R1 = 0x%02x\n", c0drb[1]);
|
|
i82975x_printk(KERN_INFO, "DRBCH0R2 = 0x%02x\n", c0drb[2]);
|
|
i82975x_printk(KERN_INFO, "DRBCH0R3 = 0x%02x\n", c0drb[3]);
|
|
i82975x_printk(KERN_INFO, "DRBCH1R0 = 0x%02x\n", c1drb[0]);
|
|
i82975x_printk(KERN_INFO, "DRBCH1R1 = 0x%02x\n", c1drb[1]);
|
|
i82975x_printk(KERN_INFO, "DRBCH1R2 = 0x%02x\n", c1drb[2]);
|
|
i82975x_printk(KERN_INFO, "DRBCH1R3 = 0x%02x\n", c1drb[3]);
|
|
#endif
|
|
|
|
drc[0] = readl(mch_window + I82975X_DRC_CH0M0);
|
|
drc[1] = readl(mch_window + I82975X_DRC_CH1M0);
|
|
#ifdef i82975x_DEBUG_IOMEM
|
|
i82975x_printk(KERN_INFO, "DRC_CH0 = %0x, %s\n", drc[0],
|
|
((drc[0] >> 21) & 3) == 1 ?
|
|
"ECC enabled" : "ECC disabled");
|
|
i82975x_printk(KERN_INFO, "DRC_CH1 = %0x, %s\n", drc[1],
|
|
((drc[1] >> 21) & 3) == 1 ?
|
|
"ECC enabled" : "ECC disabled");
|
|
|
|
i82975x_printk(KERN_INFO, "C0 BNKARC = %0x\n",
|
|
readw(mch_window + I82975X_C0BNKARC));
|
|
i82975x_printk(KERN_INFO, "C1 BNKARC = %0x\n",
|
|
readw(mch_window + I82975X_C1BNKARC));
|
|
i82975x_print_dram_timings(mch_window);
|
|
goto fail1;
|
|
#endif
|
|
if (!(((drc[0] >> 21) & 3) == 1 || ((drc[1] >> 21) & 3) == 1)) {
|
|
i82975x_printk(KERN_INFO, "ECC disabled on both channels.\n");
|
|
goto fail1;
|
|
}
|
|
|
|
chans = dual_channel_active(mch_window) + 1;
|
|
|
|
/* assuming only one controller, index thus is 0 */
|
|
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
|
|
layers[0].size = I82975X_NR_DIMMS;
|
|
layers[0].is_virt_csrow = true;
|
|
layers[1].type = EDAC_MC_LAYER_CHANNEL;
|
|
layers[1].size = I82975X_NR_CSROWS(chans);
|
|
layers[1].is_virt_csrow = false;
|
|
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
|
|
if (!mci) {
|
|
rc = -ENOMEM;
|
|
goto fail1;
|
|
}
|
|
|
|
edac_dbg(3, "init mci\n");
|
|
mci->pdev = &pdev->dev;
|
|
mci->mtype_cap = MEM_FLAG_DDR2;
|
|
mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
|
|
mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
|
|
mci->mod_name = EDAC_MOD_STR;
|
|
mci->mod_ver = I82975X_REVISION;
|
|
mci->ctl_name = i82975x_devs[dev_idx].ctl_name;
|
|
mci->dev_name = pci_name(pdev);
|
|
mci->edac_check = i82975x_check;
|
|
mci->ctl_page_to_phys = NULL;
|
|
edac_dbg(3, "init pvt\n");
|
|
pvt = (struct i82975x_pvt *) mci->pvt_info;
|
|
pvt->mch_window = mch_window;
|
|
i82975x_init_csrows(mci, pdev, mch_window);
|
|
mci->scrub_mode = SCRUB_HW_SRC;
|
|
i82975x_get_error_info(mci, &discard); /* clear counters */
|
|
|
|
/* finalize this instance of memory controller with edac core */
|
|
if (edac_mc_add_mc(mci)) {
|
|
edac_dbg(3, "failed edac_mc_add_mc()\n");
|
|
goto fail2;
|
|
}
|
|
|
|
/* get this far and it's successful */
|
|
edac_dbg(3, "success\n");
|
|
return 0;
|
|
|
|
fail2:
|
|
edac_mc_free(mci);
|
|
|
|
fail1:
|
|
iounmap(mch_window);
|
|
fail0:
|
|
return rc;
|
|
}
|
|
|
|
/* returns count (>= 0), or negative on error */
|
|
static int i82975x_init_one(struct pci_dev *pdev,
|
|
const struct pci_device_id *ent)
|
|
{
|
|
int rc;
|
|
|
|
edac_dbg(0, "\n");
|
|
|
|
if (pci_enable_device(pdev) < 0)
|
|
return -EIO;
|
|
|
|
rc = i82975x_probe1(pdev, ent->driver_data);
|
|
|
|
if (mci_pdev == NULL)
|
|
mci_pdev = pci_dev_get(pdev);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static void i82975x_remove_one(struct pci_dev *pdev)
|
|
{
|
|
struct mem_ctl_info *mci;
|
|
struct i82975x_pvt *pvt;
|
|
|
|
edac_dbg(0, "\n");
|
|
|
|
mci = edac_mc_del_mc(&pdev->dev);
|
|
if (mci == NULL)
|
|
return;
|
|
|
|
pvt = mci->pvt_info;
|
|
if (pvt->mch_window)
|
|
iounmap( pvt->mch_window );
|
|
|
|
edac_mc_free(mci);
|
|
}
|
|
|
|
static const struct pci_device_id i82975x_pci_tbl[] = {
|
|
{
|
|
PCI_VEND_DEV(INTEL, 82975_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
|
|
I82975X
|
|
},
|
|
{
|
|
0,
|
|
} /* 0 terminated list. */
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, i82975x_pci_tbl);
|
|
|
|
static struct pci_driver i82975x_driver = {
|
|
.name = EDAC_MOD_STR,
|
|
.probe = i82975x_init_one,
|
|
.remove = i82975x_remove_one,
|
|
.id_table = i82975x_pci_tbl,
|
|
};
|
|
|
|
static int __init i82975x_init(void)
|
|
{
|
|
int pci_rc;
|
|
|
|
edac_dbg(3, "\n");
|
|
|
|
/* Ensure that the OPSTATE is set correctly for POLL or NMI */
|
|
opstate_init();
|
|
|
|
pci_rc = pci_register_driver(&i82975x_driver);
|
|
if (pci_rc < 0)
|
|
goto fail0;
|
|
|
|
if (mci_pdev == NULL) {
|
|
mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
|
|
PCI_DEVICE_ID_INTEL_82975_0, NULL);
|
|
|
|
if (!mci_pdev) {
|
|
edac_dbg(0, "i82975x pci_get_device fail\n");
|
|
pci_rc = -ENODEV;
|
|
goto fail1;
|
|
}
|
|
|
|
pci_rc = i82975x_init_one(mci_pdev, i82975x_pci_tbl);
|
|
|
|
if (pci_rc < 0) {
|
|
edac_dbg(0, "i82975x init fail\n");
|
|
pci_rc = -ENODEV;
|
|
goto fail1;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
fail1:
|
|
pci_unregister_driver(&i82975x_driver);
|
|
|
|
fail0:
|
|
pci_dev_put(mci_pdev);
|
|
return pci_rc;
|
|
}
|
|
|
|
static void __exit i82975x_exit(void)
|
|
{
|
|
edac_dbg(3, "\n");
|
|
|
|
pci_unregister_driver(&i82975x_driver);
|
|
|
|
if (!i82975x_registered) {
|
|
i82975x_remove_one(mci_pdev);
|
|
pci_dev_put(mci_pdev);
|
|
}
|
|
}
|
|
|
|
module_init(i82975x_init);
|
|
module_exit(i82975x_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Arvind R. <arvino55@gmail.com>");
|
|
MODULE_DESCRIPTION("MC support for Intel 82975 memory hub controllers");
|
|
|
|
module_param(edac_op_state, int, 0444);
|
|
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
|