864 строки
21 KiB
C
864 строки
21 KiB
C
/*
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* Copyright (C) 2013 Broadcom Corporation
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* Copyright 2013 Linaro Limited
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include "clk-kona.h"
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/* These are used when a selector or trigger is found to be unneeded */
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#define selector_clear_exists(sel) ((sel)->width = 0)
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#define trigger_clear_exists(trig) FLAG_CLEAR(trig, TRIG, EXISTS)
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/* Validity checking */
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static bool ccu_data_offsets_valid(struct ccu_data *ccu)
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{
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struct ccu_policy *ccu_policy = &ccu->policy;
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u32 limit;
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limit = ccu->range - sizeof(u32);
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limit = round_down(limit, sizeof(u32));
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if (ccu_policy_exists(ccu_policy)) {
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if (ccu_policy->enable.offset > limit) {
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pr_err("%s: bad policy enable offset for %s "
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"(%u > %u)\n", __func__,
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ccu->name, ccu_policy->enable.offset, limit);
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return false;
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}
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if (ccu_policy->control.offset > limit) {
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pr_err("%s: bad policy control offset for %s "
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"(%u > %u)\n", __func__,
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ccu->name, ccu_policy->control.offset, limit);
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return false;
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}
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}
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return true;
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}
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static bool clk_requires_trigger(struct kona_clk *bcm_clk)
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{
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struct peri_clk_data *peri = bcm_clk->u.peri;
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struct bcm_clk_sel *sel;
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struct bcm_clk_div *div;
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if (bcm_clk->type != bcm_clk_peri)
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return false;
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sel = &peri->sel;
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if (sel->parent_count && selector_exists(sel))
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return true;
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div = &peri->div;
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if (!divider_exists(div))
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return false;
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/* Fixed dividers don't need triggers */
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if (!divider_is_fixed(div))
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return true;
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div = &peri->pre_div;
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return divider_exists(div) && !divider_is_fixed(div);
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}
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static bool peri_clk_data_offsets_valid(struct kona_clk *bcm_clk)
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{
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struct peri_clk_data *peri;
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struct bcm_clk_policy *policy;
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struct bcm_clk_gate *gate;
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struct bcm_clk_hyst *hyst;
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struct bcm_clk_div *div;
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struct bcm_clk_sel *sel;
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struct bcm_clk_trig *trig;
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const char *name;
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u32 range;
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u32 limit;
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BUG_ON(bcm_clk->type != bcm_clk_peri);
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peri = bcm_clk->u.peri;
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name = bcm_clk->init_data.name;
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range = bcm_clk->ccu->range;
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limit = range - sizeof(u32);
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limit = round_down(limit, sizeof(u32));
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policy = &peri->policy;
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if (policy_exists(policy)) {
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if (policy->offset > limit) {
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pr_err("%s: bad policy offset for %s (%u > %u)\n",
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__func__, name, policy->offset, limit);
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return false;
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}
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}
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gate = &peri->gate;
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hyst = &peri->hyst;
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if (gate_exists(gate)) {
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if (gate->offset > limit) {
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pr_err("%s: bad gate offset for %s (%u > %u)\n",
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__func__, name, gate->offset, limit);
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return false;
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}
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if (hyst_exists(hyst)) {
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if (hyst->offset > limit) {
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pr_err("%s: bad hysteresis offset for %s "
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"(%u > %u)\n", __func__,
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name, hyst->offset, limit);
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return false;
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}
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}
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} else if (hyst_exists(hyst)) {
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pr_err("%s: hysteresis but no gate for %s\n", __func__, name);
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return false;
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}
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div = &peri->div;
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if (divider_exists(div)) {
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if (div->u.s.offset > limit) {
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pr_err("%s: bad divider offset for %s (%u > %u)\n",
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__func__, name, div->u.s.offset, limit);
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return false;
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}
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}
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div = &peri->pre_div;
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if (divider_exists(div)) {
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if (div->u.s.offset > limit) {
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pr_err("%s: bad pre-divider offset for %s "
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"(%u > %u)\n",
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__func__, name, div->u.s.offset, limit);
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return false;
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}
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}
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sel = &peri->sel;
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if (selector_exists(sel)) {
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if (sel->offset > limit) {
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pr_err("%s: bad selector offset for %s (%u > %u)\n",
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__func__, name, sel->offset, limit);
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return false;
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}
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}
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trig = &peri->trig;
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if (trigger_exists(trig)) {
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if (trig->offset > limit) {
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pr_err("%s: bad trigger offset for %s (%u > %u)\n",
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__func__, name, trig->offset, limit);
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return false;
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}
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}
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trig = &peri->pre_trig;
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if (trigger_exists(trig)) {
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if (trig->offset > limit) {
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pr_err("%s: bad pre-trigger offset for %s (%u > %u)\n",
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__func__, name, trig->offset, limit);
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return false;
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}
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}
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return true;
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}
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/* A bit position must be less than the number of bits in a 32-bit register. */
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static bool bit_posn_valid(u32 bit_posn, const char *field_name,
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const char *clock_name)
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{
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u32 limit = BITS_PER_BYTE * sizeof(u32) - 1;
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if (bit_posn > limit) {
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pr_err("%s: bad %s bit for %s (%u > %u)\n", __func__,
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field_name, clock_name, bit_posn, limit);
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return false;
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}
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return true;
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}
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/*
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* A bitfield must be at least 1 bit wide. Both the low-order and
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* high-order bits must lie within a 32-bit register. We require
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* fields to be less than 32 bits wide, mainly because we use
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* shifting to produce field masks, and shifting a full word width
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* is not well-defined by the C standard.
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*/
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static bool bitfield_valid(u32 shift, u32 width, const char *field_name,
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const char *clock_name)
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{
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u32 limit = BITS_PER_BYTE * sizeof(u32);
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if (!width) {
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pr_err("%s: bad %s field width 0 for %s\n", __func__,
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field_name, clock_name);
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return false;
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}
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if (shift + width > limit) {
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pr_err("%s: bad %s for %s (%u + %u > %u)\n", __func__,
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field_name, clock_name, shift, width, limit);
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return false;
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}
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return true;
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}
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static bool
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ccu_policy_valid(struct ccu_policy *ccu_policy, const char *ccu_name)
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{
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struct bcm_lvm_en *enable = &ccu_policy->enable;
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struct bcm_policy_ctl *control;
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if (!bit_posn_valid(enable->bit, "policy enable", ccu_name))
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return false;
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control = &ccu_policy->control;
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if (!bit_posn_valid(control->go_bit, "policy control GO", ccu_name))
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return false;
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if (!bit_posn_valid(control->atl_bit, "policy control ATL", ccu_name))
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return false;
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if (!bit_posn_valid(control->ac_bit, "policy control AC", ccu_name))
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return false;
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return true;
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}
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static bool policy_valid(struct bcm_clk_policy *policy, const char *clock_name)
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{
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if (!bit_posn_valid(policy->bit, "policy", clock_name))
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return false;
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return true;
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}
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/*
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* All gates, if defined, have a status bit, and for hardware-only
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* gates, that's it. Gates that can be software controlled also
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* have an enable bit. And a gate that can be hardware or software
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* controlled will have a hardware/software select bit.
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*/
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static bool gate_valid(struct bcm_clk_gate *gate, const char *field_name,
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const char *clock_name)
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{
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if (!bit_posn_valid(gate->status_bit, "gate status", clock_name))
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return false;
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if (gate_is_sw_controllable(gate)) {
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if (!bit_posn_valid(gate->en_bit, "gate enable", clock_name))
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return false;
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if (gate_is_hw_controllable(gate)) {
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if (!bit_posn_valid(gate->hw_sw_sel_bit,
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"gate hw/sw select",
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clock_name))
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return false;
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}
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} else {
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BUG_ON(!gate_is_hw_controllable(gate));
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}
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return true;
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}
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static bool hyst_valid(struct bcm_clk_hyst *hyst, const char *clock_name)
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{
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if (!bit_posn_valid(hyst->en_bit, "hysteresis enable", clock_name))
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return false;
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if (!bit_posn_valid(hyst->val_bit, "hysteresis value", clock_name))
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return false;
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return true;
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}
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/*
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* A selector bitfield must be valid. Its parent_sel array must
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* also be reasonable for the field.
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*/
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static bool sel_valid(struct bcm_clk_sel *sel, const char *field_name,
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const char *clock_name)
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{
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if (!bitfield_valid(sel->shift, sel->width, field_name, clock_name))
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return false;
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if (sel->parent_count) {
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u32 max_sel;
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u32 limit;
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/*
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* Make sure the selector field can hold all the
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* selector values we expect to be able to use. A
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* clock only needs to have a selector defined if it
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* has more than one parent. And in that case the
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* highest selector value will be in the last entry
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* in the array.
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*/
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max_sel = sel->parent_sel[sel->parent_count - 1];
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limit = (1 << sel->width) - 1;
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if (max_sel > limit) {
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pr_err("%s: bad selector for %s "
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"(%u needs > %u bits)\n",
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__func__, clock_name, max_sel,
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sel->width);
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return false;
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}
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} else {
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pr_warn("%s: ignoring selector for %s (no parents)\n",
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__func__, clock_name);
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selector_clear_exists(sel);
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kfree(sel->parent_sel);
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sel->parent_sel = NULL;
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}
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return true;
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}
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/*
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* A fixed divider just needs to be non-zero. A variable divider
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* has to have a valid divider bitfield, and if it has a fraction,
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* the width of the fraction must not be no more than the width of
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* the divider as a whole.
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*/
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static bool div_valid(struct bcm_clk_div *div, const char *field_name,
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const char *clock_name)
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{
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if (divider_is_fixed(div)) {
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/* Any fixed divider value but 0 is OK */
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if (div->u.fixed == 0) {
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pr_err("%s: bad %s fixed value 0 for %s\n", __func__,
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field_name, clock_name);
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return false;
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}
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return true;
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}
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if (!bitfield_valid(div->u.s.shift, div->u.s.width,
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field_name, clock_name))
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return false;
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if (divider_has_fraction(div))
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if (div->u.s.frac_width > div->u.s.width) {
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pr_warn("%s: bad %s fraction width for %s (%u > %u)\n",
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__func__, field_name, clock_name,
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div->u.s.frac_width, div->u.s.width);
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return false;
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}
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return true;
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}
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/*
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* If a clock has two dividers, the combined number of fractional
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* bits must be representable in a 32-bit unsigned value. This
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* is because we scale up a dividend using both dividers before
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* dividing to improve accuracy, and we need to avoid overflow.
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*/
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static bool kona_dividers_valid(struct kona_clk *bcm_clk)
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{
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struct peri_clk_data *peri = bcm_clk->u.peri;
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struct bcm_clk_div *div;
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struct bcm_clk_div *pre_div;
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u32 limit;
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BUG_ON(bcm_clk->type != bcm_clk_peri);
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if (!divider_exists(&peri->div) || !divider_exists(&peri->pre_div))
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return true;
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div = &peri->div;
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pre_div = &peri->pre_div;
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if (divider_is_fixed(div) || divider_is_fixed(pre_div))
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return true;
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limit = BITS_PER_BYTE * sizeof(u32);
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return div->u.s.frac_width + pre_div->u.s.frac_width <= limit;
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}
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/* A trigger just needs to represent a valid bit position */
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static bool trig_valid(struct bcm_clk_trig *trig, const char *field_name,
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const char *clock_name)
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{
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return bit_posn_valid(trig->bit, field_name, clock_name);
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}
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/* Determine whether the set of peripheral clock registers are valid. */
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static bool
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peri_clk_data_valid(struct kona_clk *bcm_clk)
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{
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struct peri_clk_data *peri;
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struct bcm_clk_policy *policy;
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struct bcm_clk_gate *gate;
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struct bcm_clk_hyst *hyst;
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struct bcm_clk_sel *sel;
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struct bcm_clk_div *div;
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struct bcm_clk_div *pre_div;
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struct bcm_clk_trig *trig;
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const char *name;
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BUG_ON(bcm_clk->type != bcm_clk_peri);
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/*
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* First validate register offsets. This is the only place
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* where we need something from the ccu, so we do these
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* together.
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*/
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if (!peri_clk_data_offsets_valid(bcm_clk))
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return false;
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peri = bcm_clk->u.peri;
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name = bcm_clk->init_data.name;
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policy = &peri->policy;
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if (policy_exists(policy) && !policy_valid(policy, name))
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return false;
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gate = &peri->gate;
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if (gate_exists(gate) && !gate_valid(gate, "gate", name))
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return false;
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hyst = &peri->hyst;
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if (hyst_exists(hyst) && !hyst_valid(hyst, name))
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return false;
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sel = &peri->sel;
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if (selector_exists(sel)) {
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if (!sel_valid(sel, "selector", name))
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return false;
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} else if (sel->parent_count > 1) {
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pr_err("%s: multiple parents but no selector for %s\n",
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__func__, name);
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return false;
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}
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div = &peri->div;
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pre_div = &peri->pre_div;
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if (divider_exists(div)) {
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if (!div_valid(div, "divider", name))
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return false;
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if (divider_exists(pre_div))
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if (!div_valid(pre_div, "pre-divider", name))
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return false;
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} else if (divider_exists(pre_div)) {
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pr_err("%s: pre-divider but no divider for %s\n", __func__,
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name);
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return false;
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}
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trig = &peri->trig;
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if (trigger_exists(trig)) {
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if (!trig_valid(trig, "trigger", name))
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return false;
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if (trigger_exists(&peri->pre_trig)) {
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if (!trig_valid(trig, "pre-trigger", name)) {
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return false;
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}
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}
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if (!clk_requires_trigger(bcm_clk)) {
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pr_warn("%s: ignoring trigger for %s (not needed)\n",
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__func__, name);
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trigger_clear_exists(trig);
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}
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} else if (trigger_exists(&peri->pre_trig)) {
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pr_err("%s: pre-trigger but no trigger for %s\n", __func__,
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name);
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return false;
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} else if (clk_requires_trigger(bcm_clk)) {
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pr_err("%s: required trigger missing for %s\n", __func__,
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name);
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return false;
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}
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return kona_dividers_valid(bcm_clk);
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}
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static bool kona_clk_valid(struct kona_clk *bcm_clk)
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{
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switch (bcm_clk->type) {
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case bcm_clk_peri:
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if (!peri_clk_data_valid(bcm_clk))
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return false;
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break;
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default:
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pr_err("%s: unrecognized clock type (%d)\n", __func__,
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(int)bcm_clk->type);
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return false;
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}
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return true;
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}
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/*
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* Scan an array of parent clock names to determine whether there
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* are any entries containing BAD_CLK_NAME. Such entries are
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* placeholders for non-supported clocks. Keep track of the
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* position of each clock name in the original array.
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*
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* Allocates an array of pointers to to hold the names of all
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* non-null entries in the original array, and returns a pointer to
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* that array in *names. This will be used for registering the
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* clock with the common clock code. On successful return,
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* *count indicates how many entries are in that names array.
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*
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* If there is more than one entry in the resulting names array,
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* another array is allocated to record the parent selector value
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* for each (defined) parent clock. This is the value that
|
|
* represents this parent clock in the clock's source selector
|
|
* register. The position of the clock in the original parent array
|
|
* defines that selector value. The number of entries in this array
|
|
* is the same as the number of entries in the parent names array.
|
|
*
|
|
* The array of selector values is returned. If the clock has no
|
|
* parents, no selector is required and a null pointer is returned.
|
|
*
|
|
* Returns a null pointer if the clock names array supplied was
|
|
* null. (This is not an error.)
|
|
*
|
|
* Returns a pointer-coded error if an error occurs.
|
|
*/
|
|
static u32 *parent_process(const char *clocks[],
|
|
u32 *count, const char ***names)
|
|
{
|
|
static const char **parent_names;
|
|
static u32 *parent_sel;
|
|
const char **clock;
|
|
u32 parent_count;
|
|
u32 bad_count = 0;
|
|
u32 orig_count;
|
|
u32 i;
|
|
u32 j;
|
|
|
|
*count = 0; /* In case of early return */
|
|
*names = NULL;
|
|
if (!clocks)
|
|
return NULL;
|
|
|
|
/*
|
|
* Count the number of names in the null-terminated array,
|
|
* and find out how many of those are actually clock names.
|
|
*/
|
|
for (clock = clocks; *clock; clock++)
|
|
if (*clock == BAD_CLK_NAME)
|
|
bad_count++;
|
|
orig_count = (u32)(clock - clocks);
|
|
parent_count = orig_count - bad_count;
|
|
|
|
/* If all clocks are unsupported, we treat it as no clock */
|
|
if (!parent_count)
|
|
return NULL;
|
|
|
|
/* Avoid exceeding our parent clock limit */
|
|
if (parent_count > PARENT_COUNT_MAX) {
|
|
pr_err("%s: too many parents (%u > %u)\n", __func__,
|
|
parent_count, PARENT_COUNT_MAX);
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
|
|
/*
|
|
* There is one parent name for each defined parent clock.
|
|
* We also maintain an array containing the selector value
|
|
* for each defined clock. If there's only one clock, the
|
|
* selector is not required, but we allocate space for the
|
|
* array anyway to keep things simple.
|
|
*/
|
|
parent_names = kmalloc_array(parent_count, sizeof(*parent_names),
|
|
GFP_KERNEL);
|
|
if (!parent_names)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
/* There is at least one parent, so allocate a selector array */
|
|
parent_sel = kmalloc_array(parent_count, sizeof(*parent_sel),
|
|
GFP_KERNEL);
|
|
if (!parent_sel) {
|
|
kfree(parent_names);
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
}
|
|
|
|
/* Now fill in the parent names and selector arrays */
|
|
for (i = 0, j = 0; i < orig_count; i++) {
|
|
if (clocks[i] != BAD_CLK_NAME) {
|
|
parent_names[j] = clocks[i];
|
|
parent_sel[j] = i;
|
|
j++;
|
|
}
|
|
}
|
|
*names = parent_names;
|
|
*count = parent_count;
|
|
|
|
return parent_sel;
|
|
}
|
|
|
|
static int
|
|
clk_sel_setup(const char **clocks, struct bcm_clk_sel *sel,
|
|
struct clk_init_data *init_data)
|
|
{
|
|
const char **parent_names = NULL;
|
|
u32 parent_count = 0;
|
|
u32 *parent_sel;
|
|
|
|
/*
|
|
* If a peripheral clock has multiple parents, the value
|
|
* used by the hardware to select that parent is represented
|
|
* by the parent clock's position in the "clocks" list. Some
|
|
* values don't have defined or supported clocks; these will
|
|
* have BAD_CLK_NAME entries in the parents[] array. The
|
|
* list is terminated by a NULL entry.
|
|
*
|
|
* We need to supply (only) the names of defined parent
|
|
* clocks when registering a clock though, so we use an
|
|
* array of parent selector values to map between the
|
|
* indexes the common clock code uses and the selector
|
|
* values we need.
|
|
*/
|
|
parent_sel = parent_process(clocks, &parent_count, &parent_names);
|
|
if (IS_ERR(parent_sel)) {
|
|
int ret = PTR_ERR(parent_sel);
|
|
|
|
pr_err("%s: error processing parent clocks for %s (%d)\n",
|
|
__func__, init_data->name, ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
init_data->parent_names = parent_names;
|
|
init_data->num_parents = parent_count;
|
|
|
|
sel->parent_count = parent_count;
|
|
sel->parent_sel = parent_sel;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void clk_sel_teardown(struct bcm_clk_sel *sel,
|
|
struct clk_init_data *init_data)
|
|
{
|
|
kfree(sel->parent_sel);
|
|
sel->parent_sel = NULL;
|
|
sel->parent_count = 0;
|
|
|
|
init_data->num_parents = 0;
|
|
kfree(init_data->parent_names);
|
|
init_data->parent_names = NULL;
|
|
}
|
|
|
|
static void peri_clk_teardown(struct peri_clk_data *data,
|
|
struct clk_init_data *init_data)
|
|
{
|
|
clk_sel_teardown(&data->sel, init_data);
|
|
}
|
|
|
|
/*
|
|
* Caller is responsible for freeing the parent_names[] and
|
|
* parent_sel[] arrays in the peripheral clock's "data" structure
|
|
* that can be assigned if the clock has one or more parent clocks
|
|
* associated with it.
|
|
*/
|
|
static int
|
|
peri_clk_setup(struct peri_clk_data *data, struct clk_init_data *init_data)
|
|
{
|
|
init_data->flags = CLK_IGNORE_UNUSED;
|
|
|
|
return clk_sel_setup(data->clocks, &data->sel, init_data);
|
|
}
|
|
|
|
static void bcm_clk_teardown(struct kona_clk *bcm_clk)
|
|
{
|
|
switch (bcm_clk->type) {
|
|
case bcm_clk_peri:
|
|
peri_clk_teardown(bcm_clk->u.data, &bcm_clk->init_data);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
bcm_clk->u.data = NULL;
|
|
bcm_clk->type = bcm_clk_none;
|
|
}
|
|
|
|
static void kona_clk_teardown(struct clk_hw *hw)
|
|
{
|
|
struct kona_clk *bcm_clk;
|
|
|
|
if (!hw)
|
|
return;
|
|
|
|
clk_hw_unregister(hw);
|
|
|
|
bcm_clk = to_kona_clk(hw);
|
|
bcm_clk_teardown(bcm_clk);
|
|
}
|
|
|
|
static int kona_clk_setup(struct kona_clk *bcm_clk)
|
|
{
|
|
int ret;
|
|
struct clk_init_data *init_data = &bcm_clk->init_data;
|
|
|
|
switch (bcm_clk->type) {
|
|
case bcm_clk_peri:
|
|
ret = peri_clk_setup(bcm_clk->u.data, init_data);
|
|
if (ret)
|
|
return ret;
|
|
break;
|
|
default:
|
|
pr_err("%s: clock type %d invalid for %s\n", __func__,
|
|
(int)bcm_clk->type, init_data->name);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Make sure everything makes sense before we set it up */
|
|
if (!kona_clk_valid(bcm_clk)) {
|
|
pr_err("%s: clock data invalid for %s\n", __func__,
|
|
init_data->name);
|
|
ret = -EINVAL;
|
|
goto out_teardown;
|
|
}
|
|
|
|
bcm_clk->hw.init = init_data;
|
|
ret = clk_hw_register(NULL, &bcm_clk->hw);
|
|
if (ret) {
|
|
pr_err("%s: error registering clock %s (%d)\n", __func__,
|
|
init_data->name, ret);
|
|
goto out_teardown;
|
|
}
|
|
|
|
return 0;
|
|
out_teardown:
|
|
bcm_clk_teardown(bcm_clk);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void ccu_clks_teardown(struct ccu_data *ccu)
|
|
{
|
|
u32 i;
|
|
|
|
for (i = 0; i < ccu->clk_num; i++)
|
|
kona_clk_teardown(&ccu->kona_clks[i].hw);
|
|
}
|
|
|
|
static void kona_ccu_teardown(struct ccu_data *ccu)
|
|
{
|
|
if (!ccu->base)
|
|
return;
|
|
|
|
of_clk_del_provider(ccu->node); /* safe if never added */
|
|
ccu_clks_teardown(ccu);
|
|
of_node_put(ccu->node);
|
|
ccu->node = NULL;
|
|
iounmap(ccu->base);
|
|
ccu->base = NULL;
|
|
}
|
|
|
|
static bool ccu_data_valid(struct ccu_data *ccu)
|
|
{
|
|
struct ccu_policy *ccu_policy;
|
|
|
|
if (!ccu_data_offsets_valid(ccu))
|
|
return false;
|
|
|
|
ccu_policy = &ccu->policy;
|
|
if (ccu_policy_exists(ccu_policy))
|
|
if (!ccu_policy_valid(ccu_policy, ccu->name))
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
static struct clk_hw *
|
|
of_clk_kona_onecell_get(struct of_phandle_args *clkspec, void *data)
|
|
{
|
|
struct ccu_data *ccu = data;
|
|
unsigned int idx = clkspec->args[0];
|
|
|
|
if (idx >= ccu->clk_num) {
|
|
pr_err("%s: invalid index %u\n", __func__, idx);
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
|
|
return &ccu->kona_clks[idx].hw;
|
|
}
|
|
|
|
/*
|
|
* Set up a CCU. Call the provided ccu_clks_setup callback to
|
|
* initialize the array of clocks provided by the CCU.
|
|
*/
|
|
void __init kona_dt_ccu_setup(struct ccu_data *ccu,
|
|
struct device_node *node)
|
|
{
|
|
struct resource res = { 0 };
|
|
resource_size_t range;
|
|
unsigned int i;
|
|
int ret;
|
|
|
|
ret = of_address_to_resource(node, 0, &res);
|
|
if (ret) {
|
|
pr_err("%s: no valid CCU registers found for %s\n", __func__,
|
|
node->name);
|
|
goto out_err;
|
|
}
|
|
|
|
range = resource_size(&res);
|
|
if (range > (resource_size_t)U32_MAX) {
|
|
pr_err("%s: address range too large for %s\n", __func__,
|
|
node->name);
|
|
goto out_err;
|
|
}
|
|
|
|
ccu->range = (u32)range;
|
|
|
|
if (!ccu_data_valid(ccu)) {
|
|
pr_err("%s: ccu data not valid for %s\n", __func__, node->name);
|
|
goto out_err;
|
|
}
|
|
|
|
ccu->base = ioremap(res.start, ccu->range);
|
|
if (!ccu->base) {
|
|
pr_err("%s: unable to map CCU registers for %s\n", __func__,
|
|
node->name);
|
|
goto out_err;
|
|
}
|
|
ccu->node = of_node_get(node);
|
|
|
|
/*
|
|
* Set up each defined kona clock and save the result in
|
|
* the clock framework clock array (in ccu->data). Then
|
|
* register as a provider for these clocks.
|
|
*/
|
|
for (i = 0; i < ccu->clk_num; i++) {
|
|
if (!ccu->kona_clks[i].ccu)
|
|
continue;
|
|
kona_clk_setup(&ccu->kona_clks[i]);
|
|
}
|
|
|
|
ret = of_clk_add_hw_provider(node, of_clk_kona_onecell_get, ccu);
|
|
if (ret) {
|
|
pr_err("%s: error adding ccu %s as provider (%d)\n", __func__,
|
|
node->name, ret);
|
|
goto out_err;
|
|
}
|
|
|
|
if (!kona_ccu_init(ccu))
|
|
pr_err("Broadcom %s initialization had errors\n", node->name);
|
|
|
|
return;
|
|
out_err:
|
|
kona_ccu_teardown(ccu);
|
|
pr_err("Broadcom %s setup aborted\n", node->name);
|
|
}
|