788 строки
20 KiB
C
788 строки
20 KiB
C
/*
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* Ingenic SoC CGU driver
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*
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* Copyright (c) 2013-2015 Imagination Technologies
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* Author: Paul Burton <paul.burton@mips.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/delay.h>
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#include <linux/math64.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include "cgu.h"
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#define MHZ (1000 * 1000)
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/**
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* ingenic_cgu_gate_get() - get the value of clock gate register bit
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* @cgu: reference to the CGU whose registers should be read
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* @info: info struct describing the gate bit
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*
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* Retrieves the state of the clock gate bit described by info. The
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* caller must hold cgu->lock.
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*
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* Return: true if the gate bit is set, else false.
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*/
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static inline bool
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ingenic_cgu_gate_get(struct ingenic_cgu *cgu,
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const struct ingenic_cgu_gate_info *info)
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{
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return !!(readl(cgu->base + info->reg) & BIT(info->bit))
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^ info->clear_to_gate;
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}
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/**
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* ingenic_cgu_gate_set() - set the value of clock gate register bit
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* @cgu: reference to the CGU whose registers should be modified
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* @info: info struct describing the gate bit
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* @val: non-zero to gate a clock, otherwise zero
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*
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* Sets the given gate bit in order to gate or ungate a clock.
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*
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* The caller must hold cgu->lock.
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*/
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static inline void
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ingenic_cgu_gate_set(struct ingenic_cgu *cgu,
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const struct ingenic_cgu_gate_info *info, bool val)
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{
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u32 clkgr = readl(cgu->base + info->reg);
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if (val ^ info->clear_to_gate)
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clkgr |= BIT(info->bit);
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else
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clkgr &= ~BIT(info->bit);
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writel(clkgr, cgu->base + info->reg);
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}
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/*
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* PLL operations
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*/
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static unsigned long
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ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const struct ingenic_cgu_clk_info *clk_info;
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const struct ingenic_cgu_pll_info *pll_info;
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unsigned m, n, od_enc, od;
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bool bypass, enable;
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unsigned long flags;
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u32 ctl;
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clk_info = &cgu->clock_info[ingenic_clk->idx];
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BUG_ON(clk_info->type != CGU_CLK_PLL);
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pll_info = &clk_info->pll;
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spin_lock_irqsave(&cgu->lock, flags);
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ctl = readl(cgu->base + pll_info->reg);
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spin_unlock_irqrestore(&cgu->lock, flags);
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m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0);
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m += pll_info->m_offset;
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n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0);
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n += pll_info->n_offset;
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od_enc = ctl >> pll_info->od_shift;
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od_enc &= GENMASK(pll_info->od_bits - 1, 0);
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bypass = !pll_info->no_bypass_bit &&
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!!(ctl & BIT(pll_info->bypass_bit));
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enable = !!(ctl & BIT(pll_info->enable_bit));
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if (bypass)
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return parent_rate;
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for (od = 0; od < pll_info->od_max; od++) {
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if (pll_info->od_encoding[od] == od_enc)
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break;
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}
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BUG_ON(od == pll_info->od_max);
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od++;
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return div_u64((u64)parent_rate * m, n * od);
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}
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static unsigned long
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ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info,
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unsigned long rate, unsigned long parent_rate,
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unsigned *pm, unsigned *pn, unsigned *pod)
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{
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const struct ingenic_cgu_pll_info *pll_info;
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unsigned m, n, od;
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pll_info = &clk_info->pll;
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od = 1;
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/*
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* The frequency after the input divider must be between 10 and 50 MHz.
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* The highest divider yields the best resolution.
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*/
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n = parent_rate / (10 * MHZ);
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n = min_t(unsigned, n, 1 << clk_info->pll.n_bits);
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n = max_t(unsigned, n, pll_info->n_offset);
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m = (rate / MHZ) * od * n / (parent_rate / MHZ);
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m = min_t(unsigned, m, 1 << clk_info->pll.m_bits);
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m = max_t(unsigned, m, pll_info->m_offset);
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if (pm)
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*pm = m;
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if (pn)
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*pn = n;
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if (pod)
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*pod = od;
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return div_u64((u64)parent_rate * m, n * od);
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}
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static inline const struct ingenic_cgu_clk_info *to_clk_info(
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struct ingenic_clk *ingenic_clk)
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{
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const struct ingenic_cgu_clk_info *clk_info;
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clk_info = &cgu->clock_info[ingenic_clk->idx];
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BUG_ON(clk_info->type != CGU_CLK_PLL);
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return clk_info;
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}
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static long
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ingenic_pll_round_rate(struct clk_hw *hw, unsigned long req_rate,
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unsigned long *prate)
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{
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struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
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const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
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return ingenic_pll_calc(clk_info, req_rate, *prate, NULL, NULL, NULL);
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}
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static int
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ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate,
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unsigned long parent_rate)
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{
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struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
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const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
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unsigned long rate, flags;
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unsigned int m, n, od;
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u32 ctl;
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rate = ingenic_pll_calc(clk_info, req_rate, parent_rate,
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&m, &n, &od);
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if (rate != req_rate)
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pr_info("ingenic-cgu: request '%s' rate %luHz, actual %luHz\n",
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clk_info->name, req_rate, rate);
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spin_lock_irqsave(&cgu->lock, flags);
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ctl = readl(cgu->base + pll_info->reg);
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ctl &= ~(GENMASK(pll_info->m_bits - 1, 0) << pll_info->m_shift);
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ctl |= (m - pll_info->m_offset) << pll_info->m_shift;
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ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift);
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ctl |= (n - pll_info->n_offset) << pll_info->n_shift;
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ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift);
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ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift;
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writel(ctl, cgu->base + pll_info->reg);
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spin_unlock_irqrestore(&cgu->lock, flags);
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return 0;
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}
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static int ingenic_pll_enable(struct clk_hw *hw)
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{
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struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
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const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
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const unsigned int timeout = 100;
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unsigned long flags;
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unsigned int i;
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u32 ctl;
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spin_lock_irqsave(&cgu->lock, flags);
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ctl = readl(cgu->base + pll_info->reg);
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ctl &= ~BIT(pll_info->bypass_bit);
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ctl |= BIT(pll_info->enable_bit);
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writel(ctl, cgu->base + pll_info->reg);
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/* wait for the PLL to stabilise */
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for (i = 0; i < timeout; i++) {
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ctl = readl(cgu->base + pll_info->reg);
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if (ctl & BIT(pll_info->stable_bit))
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break;
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mdelay(1);
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}
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spin_unlock_irqrestore(&cgu->lock, flags);
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if (i == timeout)
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return -EBUSY;
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return 0;
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}
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static void ingenic_pll_disable(struct clk_hw *hw)
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{
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struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
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const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
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unsigned long flags;
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u32 ctl;
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spin_lock_irqsave(&cgu->lock, flags);
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ctl = readl(cgu->base + pll_info->reg);
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ctl &= ~BIT(pll_info->enable_bit);
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writel(ctl, cgu->base + pll_info->reg);
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spin_unlock_irqrestore(&cgu->lock, flags);
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}
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static int ingenic_pll_is_enabled(struct clk_hw *hw)
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{
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struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
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const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
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unsigned long flags;
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u32 ctl;
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spin_lock_irqsave(&cgu->lock, flags);
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ctl = readl(cgu->base + pll_info->reg);
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spin_unlock_irqrestore(&cgu->lock, flags);
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return !!(ctl & BIT(pll_info->enable_bit));
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}
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static const struct clk_ops ingenic_pll_ops = {
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.recalc_rate = ingenic_pll_recalc_rate,
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.round_rate = ingenic_pll_round_rate,
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.set_rate = ingenic_pll_set_rate,
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.enable = ingenic_pll_enable,
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.disable = ingenic_pll_disable,
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.is_enabled = ingenic_pll_is_enabled,
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};
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/*
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* Operations for all non-PLL clocks
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*/
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static u8 ingenic_clk_get_parent(struct clk_hw *hw)
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{
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struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const struct ingenic_cgu_clk_info *clk_info;
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u32 reg;
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u8 i, hw_idx, idx = 0;
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clk_info = &cgu->clock_info[ingenic_clk->idx];
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if (clk_info->type & CGU_CLK_MUX) {
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reg = readl(cgu->base + clk_info->mux.reg);
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hw_idx = (reg >> clk_info->mux.shift) &
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GENMASK(clk_info->mux.bits - 1, 0);
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/*
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* Convert the hardware index to the parent index by skipping
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* over any -1's in the parents array.
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*/
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for (i = 0; i < hw_idx; i++) {
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if (clk_info->parents[i] != -1)
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idx++;
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}
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}
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return idx;
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}
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static int ingenic_clk_set_parent(struct clk_hw *hw, u8 idx)
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{
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struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const struct ingenic_cgu_clk_info *clk_info;
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unsigned long flags;
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u8 curr_idx, hw_idx, num_poss;
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u32 reg, mask;
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clk_info = &cgu->clock_info[ingenic_clk->idx];
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if (clk_info->type & CGU_CLK_MUX) {
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/*
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* Convert the parent index to the hardware index by adding
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* 1 for any -1 in the parents array preceding the given
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* index. That is, we want the index of idx'th entry in
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* clk_info->parents which does not equal -1.
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*/
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hw_idx = curr_idx = 0;
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num_poss = 1 << clk_info->mux.bits;
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for (; hw_idx < num_poss; hw_idx++) {
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if (clk_info->parents[hw_idx] == -1)
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continue;
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if (curr_idx == idx)
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break;
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curr_idx++;
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}
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/* idx should always be a valid parent */
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BUG_ON(curr_idx != idx);
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mask = GENMASK(clk_info->mux.bits - 1, 0);
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mask <<= clk_info->mux.shift;
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spin_lock_irqsave(&cgu->lock, flags);
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/* write the register */
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reg = readl(cgu->base + clk_info->mux.reg);
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reg &= ~mask;
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reg |= hw_idx << clk_info->mux.shift;
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writel(reg, cgu->base + clk_info->mux.reg);
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spin_unlock_irqrestore(&cgu->lock, flags);
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return 0;
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}
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return idx ? -EINVAL : 0;
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}
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static unsigned long
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ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const struct ingenic_cgu_clk_info *clk_info;
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unsigned long rate = parent_rate;
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u32 div_reg, div;
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clk_info = &cgu->clock_info[ingenic_clk->idx];
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if (clk_info->type & CGU_CLK_DIV) {
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div_reg = readl(cgu->base + clk_info->div.reg);
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div = (div_reg >> clk_info->div.shift) &
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GENMASK(clk_info->div.bits - 1, 0);
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div += 1;
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div *= clk_info->div.div;
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rate /= div;
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} else if (clk_info->type & CGU_CLK_FIXDIV) {
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rate /= clk_info->fixdiv.div;
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}
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return rate;
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}
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static unsigned
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ingenic_clk_calc_div(const struct ingenic_cgu_clk_info *clk_info,
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unsigned long parent_rate, unsigned long req_rate)
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{
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unsigned div;
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/* calculate the divide */
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div = DIV_ROUND_UP(parent_rate, req_rate);
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/* and impose hardware constraints */
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div = min_t(unsigned, div, 1 << clk_info->div.bits);
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div = max_t(unsigned, div, 1);
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/*
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* If the divider value itself must be divided before being written to
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* the divider register, we must ensure we don't have any bits set that
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* would be lost as a result of doing so.
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*/
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div /= clk_info->div.div;
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div *= clk_info->div.div;
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return div;
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}
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static long
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ingenic_clk_round_rate(struct clk_hw *hw, unsigned long req_rate,
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unsigned long *parent_rate)
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{
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struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const struct ingenic_cgu_clk_info *clk_info;
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long rate = *parent_rate;
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clk_info = &cgu->clock_info[ingenic_clk->idx];
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if (clk_info->type & CGU_CLK_DIV)
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rate /= ingenic_clk_calc_div(clk_info, *parent_rate, req_rate);
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else if (clk_info->type & CGU_CLK_FIXDIV)
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rate /= clk_info->fixdiv.div;
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return rate;
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}
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static int
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ingenic_clk_set_rate(struct clk_hw *hw, unsigned long req_rate,
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unsigned long parent_rate)
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{
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struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const struct ingenic_cgu_clk_info *clk_info;
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const unsigned timeout = 100;
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unsigned long rate, flags;
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unsigned div, i;
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u32 reg, mask;
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int ret = 0;
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clk_info = &cgu->clock_info[ingenic_clk->idx];
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if (clk_info->type & CGU_CLK_DIV) {
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div = ingenic_clk_calc_div(clk_info, parent_rate, req_rate);
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rate = parent_rate / div;
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if (rate != req_rate)
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return -EINVAL;
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spin_lock_irqsave(&cgu->lock, flags);
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reg = readl(cgu->base + clk_info->div.reg);
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/* update the divide */
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mask = GENMASK(clk_info->div.bits - 1, 0);
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reg &= ~(mask << clk_info->div.shift);
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reg |= ((div / clk_info->div.div) - 1) << clk_info->div.shift;
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/* clear the stop bit */
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if (clk_info->div.stop_bit != -1)
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reg &= ~BIT(clk_info->div.stop_bit);
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/* set the change enable bit */
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if (clk_info->div.ce_bit != -1)
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reg |= BIT(clk_info->div.ce_bit);
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/* update the hardware */
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writel(reg, cgu->base + clk_info->div.reg);
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/* wait for the change to take effect */
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if (clk_info->div.busy_bit != -1) {
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for (i = 0; i < timeout; i++) {
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reg = readl(cgu->base + clk_info->div.reg);
|
|
if (!(reg & BIT(clk_info->div.busy_bit)))
|
|
break;
|
|
mdelay(1);
|
|
}
|
|
if (i == timeout)
|
|
ret = -EBUSY;
|
|
}
|
|
|
|
spin_unlock_irqrestore(&cgu->lock, flags);
|
|
return ret;
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int ingenic_clk_enable(struct clk_hw *hw)
|
|
{
|
|
struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
|
|
struct ingenic_cgu *cgu = ingenic_clk->cgu;
|
|
const struct ingenic_cgu_clk_info *clk_info;
|
|
unsigned long flags;
|
|
|
|
clk_info = &cgu->clock_info[ingenic_clk->idx];
|
|
|
|
if (clk_info->type & CGU_CLK_GATE) {
|
|
/* ungate the clock */
|
|
spin_lock_irqsave(&cgu->lock, flags);
|
|
ingenic_cgu_gate_set(cgu, &clk_info->gate, false);
|
|
spin_unlock_irqrestore(&cgu->lock, flags);
|
|
|
|
if (clk_info->gate.delay_us)
|
|
udelay(clk_info->gate.delay_us);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void ingenic_clk_disable(struct clk_hw *hw)
|
|
{
|
|
struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
|
|
struct ingenic_cgu *cgu = ingenic_clk->cgu;
|
|
const struct ingenic_cgu_clk_info *clk_info;
|
|
unsigned long flags;
|
|
|
|
clk_info = &cgu->clock_info[ingenic_clk->idx];
|
|
|
|
if (clk_info->type & CGU_CLK_GATE) {
|
|
/* gate the clock */
|
|
spin_lock_irqsave(&cgu->lock, flags);
|
|
ingenic_cgu_gate_set(cgu, &clk_info->gate, true);
|
|
spin_unlock_irqrestore(&cgu->lock, flags);
|
|
}
|
|
}
|
|
|
|
static int ingenic_clk_is_enabled(struct clk_hw *hw)
|
|
{
|
|
struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
|
|
struct ingenic_cgu *cgu = ingenic_clk->cgu;
|
|
const struct ingenic_cgu_clk_info *clk_info;
|
|
unsigned long flags;
|
|
int enabled = 1;
|
|
|
|
clk_info = &cgu->clock_info[ingenic_clk->idx];
|
|
|
|
if (clk_info->type & CGU_CLK_GATE) {
|
|
spin_lock_irqsave(&cgu->lock, flags);
|
|
enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate);
|
|
spin_unlock_irqrestore(&cgu->lock, flags);
|
|
}
|
|
|
|
return enabled;
|
|
}
|
|
|
|
static const struct clk_ops ingenic_clk_ops = {
|
|
.get_parent = ingenic_clk_get_parent,
|
|
.set_parent = ingenic_clk_set_parent,
|
|
|
|
.recalc_rate = ingenic_clk_recalc_rate,
|
|
.round_rate = ingenic_clk_round_rate,
|
|
.set_rate = ingenic_clk_set_rate,
|
|
|
|
.enable = ingenic_clk_enable,
|
|
.disable = ingenic_clk_disable,
|
|
.is_enabled = ingenic_clk_is_enabled,
|
|
};
|
|
|
|
/*
|
|
* Setup functions.
|
|
*/
|
|
|
|
static int ingenic_register_clock(struct ingenic_cgu *cgu, unsigned idx)
|
|
{
|
|
const struct ingenic_cgu_clk_info *clk_info = &cgu->clock_info[idx];
|
|
struct clk_init_data clk_init;
|
|
struct ingenic_clk *ingenic_clk = NULL;
|
|
struct clk *clk, *parent;
|
|
const char *parent_names[4];
|
|
unsigned caps, i, num_possible;
|
|
int err = -EINVAL;
|
|
|
|
BUILD_BUG_ON(ARRAY_SIZE(clk_info->parents) > ARRAY_SIZE(parent_names));
|
|
|
|
if (clk_info->type == CGU_CLK_EXT) {
|
|
clk = of_clk_get_by_name(cgu->np, clk_info->name);
|
|
if (IS_ERR(clk)) {
|
|
pr_err("%s: no external clock '%s' provided\n",
|
|
__func__, clk_info->name);
|
|
err = -ENODEV;
|
|
goto out;
|
|
}
|
|
err = clk_register_clkdev(clk, clk_info->name, NULL);
|
|
if (err) {
|
|
clk_put(clk);
|
|
goto out;
|
|
}
|
|
cgu->clocks.clks[idx] = clk;
|
|
return 0;
|
|
}
|
|
|
|
if (!clk_info->type) {
|
|
pr_err("%s: no clock type specified for '%s'\n", __func__,
|
|
clk_info->name);
|
|
goto out;
|
|
}
|
|
|
|
ingenic_clk = kzalloc(sizeof(*ingenic_clk), GFP_KERNEL);
|
|
if (!ingenic_clk) {
|
|
err = -ENOMEM;
|
|
goto out;
|
|
}
|
|
|
|
ingenic_clk->hw.init = &clk_init;
|
|
ingenic_clk->cgu = cgu;
|
|
ingenic_clk->idx = idx;
|
|
|
|
clk_init.name = clk_info->name;
|
|
clk_init.flags = 0;
|
|
clk_init.parent_names = parent_names;
|
|
|
|
caps = clk_info->type;
|
|
|
|
if (caps & (CGU_CLK_MUX | CGU_CLK_CUSTOM)) {
|
|
clk_init.num_parents = 0;
|
|
|
|
if (caps & CGU_CLK_MUX)
|
|
num_possible = 1 << clk_info->mux.bits;
|
|
else
|
|
num_possible = ARRAY_SIZE(clk_info->parents);
|
|
|
|
for (i = 0; i < num_possible; i++) {
|
|
if (clk_info->parents[i] == -1)
|
|
continue;
|
|
|
|
parent = cgu->clocks.clks[clk_info->parents[i]];
|
|
parent_names[clk_init.num_parents] =
|
|
__clk_get_name(parent);
|
|
clk_init.num_parents++;
|
|
}
|
|
|
|
BUG_ON(!clk_init.num_parents);
|
|
BUG_ON(clk_init.num_parents > ARRAY_SIZE(parent_names));
|
|
} else {
|
|
BUG_ON(clk_info->parents[0] == -1);
|
|
clk_init.num_parents = 1;
|
|
parent = cgu->clocks.clks[clk_info->parents[0]];
|
|
parent_names[0] = __clk_get_name(parent);
|
|
}
|
|
|
|
if (caps & CGU_CLK_CUSTOM) {
|
|
clk_init.ops = clk_info->custom.clk_ops;
|
|
|
|
caps &= ~CGU_CLK_CUSTOM;
|
|
|
|
if (caps) {
|
|
pr_err("%s: custom clock may not be combined with type 0x%x\n",
|
|
__func__, caps);
|
|
goto out;
|
|
}
|
|
} else if (caps & CGU_CLK_PLL) {
|
|
clk_init.ops = &ingenic_pll_ops;
|
|
clk_init.flags |= CLK_SET_RATE_GATE;
|
|
|
|
caps &= ~CGU_CLK_PLL;
|
|
|
|
if (caps) {
|
|
pr_err("%s: PLL may not be combined with type 0x%x\n",
|
|
__func__, caps);
|
|
goto out;
|
|
}
|
|
} else {
|
|
clk_init.ops = &ingenic_clk_ops;
|
|
}
|
|
|
|
/* nothing to do for gates or fixed dividers */
|
|
caps &= ~(CGU_CLK_GATE | CGU_CLK_FIXDIV);
|
|
|
|
if (caps & CGU_CLK_MUX) {
|
|
if (!(caps & CGU_CLK_MUX_GLITCHFREE))
|
|
clk_init.flags |= CLK_SET_PARENT_GATE;
|
|
|
|
caps &= ~(CGU_CLK_MUX | CGU_CLK_MUX_GLITCHFREE);
|
|
}
|
|
|
|
if (caps & CGU_CLK_DIV) {
|
|
caps &= ~CGU_CLK_DIV;
|
|
} else {
|
|
/* pass rate changes to the parent clock */
|
|
clk_init.flags |= CLK_SET_RATE_PARENT;
|
|
}
|
|
|
|
if (caps) {
|
|
pr_err("%s: unknown clock type 0x%x\n", __func__, caps);
|
|
goto out;
|
|
}
|
|
|
|
clk = clk_register(NULL, &ingenic_clk->hw);
|
|
if (IS_ERR(clk)) {
|
|
pr_err("%s: failed to register clock '%s'\n", __func__,
|
|
clk_info->name);
|
|
err = PTR_ERR(clk);
|
|
goto out;
|
|
}
|
|
|
|
err = clk_register_clkdev(clk, clk_info->name, NULL);
|
|
if (err)
|
|
goto out;
|
|
|
|
cgu->clocks.clks[idx] = clk;
|
|
out:
|
|
if (err)
|
|
kfree(ingenic_clk);
|
|
return err;
|
|
}
|
|
|
|
struct ingenic_cgu *
|
|
ingenic_cgu_new(const struct ingenic_cgu_clk_info *clock_info,
|
|
unsigned num_clocks, struct device_node *np)
|
|
{
|
|
struct ingenic_cgu *cgu;
|
|
|
|
cgu = kzalloc(sizeof(*cgu), GFP_KERNEL);
|
|
if (!cgu)
|
|
goto err_out;
|
|
|
|
cgu->base = of_iomap(np, 0);
|
|
if (!cgu->base) {
|
|
pr_err("%s: failed to map CGU registers\n", __func__);
|
|
goto err_out_free;
|
|
}
|
|
|
|
cgu->np = np;
|
|
cgu->clock_info = clock_info;
|
|
cgu->clocks.clk_num = num_clocks;
|
|
|
|
spin_lock_init(&cgu->lock);
|
|
|
|
return cgu;
|
|
|
|
err_out_free:
|
|
kfree(cgu);
|
|
err_out:
|
|
return NULL;
|
|
}
|
|
|
|
int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu)
|
|
{
|
|
unsigned i;
|
|
int err;
|
|
|
|
cgu->clocks.clks = kcalloc(cgu->clocks.clk_num, sizeof(struct clk *),
|
|
GFP_KERNEL);
|
|
if (!cgu->clocks.clks) {
|
|
err = -ENOMEM;
|
|
goto err_out;
|
|
}
|
|
|
|
for (i = 0; i < cgu->clocks.clk_num; i++) {
|
|
err = ingenic_register_clock(cgu, i);
|
|
if (err)
|
|
goto err_out_unregister;
|
|
}
|
|
|
|
err = of_clk_add_provider(cgu->np, of_clk_src_onecell_get,
|
|
&cgu->clocks);
|
|
if (err)
|
|
goto err_out_unregister;
|
|
|
|
return 0;
|
|
|
|
err_out_unregister:
|
|
for (i = 0; i < cgu->clocks.clk_num; i++) {
|
|
if (!cgu->clocks.clks[i])
|
|
continue;
|
|
if (cgu->clock_info[i].type & CGU_CLK_EXT)
|
|
clk_put(cgu->clocks.clks[i]);
|
|
else
|
|
clk_unregister(cgu->clocks.clks[i]);
|
|
}
|
|
kfree(cgu->clocks.clks);
|
|
err_out:
|
|
return err;
|
|
}
|