194 строки
5.2 KiB
C
194 строки
5.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2017 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/bitfield.h>
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#include <linux/regmap.h>
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#include "gxbb-aoclk.h"
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/*
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* The AO Domain embeds a dual/divider to generate a more precise
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* 32,768KHz clock for low-power suspend mode and CEC.
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* ______ ______
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* | | | |
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* ______ | Div1 |-| Cnt1 | ______
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* | | /|______| |______|\ | |
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* Xtal-->| Gate |---| ______ ______ X-X--| Gate |-->
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* |______| | \| | | |/ | |______|
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* | | Div2 |-| Cnt2 | |
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* | |______| |______| |
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* |_______________________|
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*
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* The dividing can be switched to single or dual, with a counter
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* for each divider to set when the switching is done.
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* The entire dividing mechanism can be also bypassed.
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*/
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#define CLK_CNTL0_N1_MASK GENMASK(11, 0)
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#define CLK_CNTL0_N2_MASK GENMASK(23, 12)
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#define CLK_CNTL0_DUALDIV_EN BIT(28)
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#define CLK_CNTL0_OUT_GATE_EN BIT(30)
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#define CLK_CNTL0_IN_GATE_EN BIT(31)
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#define CLK_CNTL1_M1_MASK GENMASK(11, 0)
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#define CLK_CNTL1_M2_MASK GENMASK(23, 12)
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#define CLK_CNTL1_BYPASS_EN BIT(24)
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#define CLK_CNTL1_SELECT_OSC BIT(27)
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#define PWR_CNTL_ALT_32K_SEL GENMASK(13, 10)
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struct cec_32k_freq_table {
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unsigned long parent_rate;
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unsigned long target_rate;
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bool dualdiv;
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unsigned int n1;
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unsigned int n2;
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unsigned int m1;
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unsigned int m2;
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};
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static const struct cec_32k_freq_table aoclk_cec_32k_table[] = {
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[0] = {
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.parent_rate = 24000000,
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.target_rate = 32768,
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.dualdiv = true,
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.n1 = 733,
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.n2 = 732,
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.m1 = 8,
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.m2 = 11,
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},
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};
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/*
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* If CLK_CNTL0_DUALDIV_EN == 0
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* - will use N1 divider only
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* If CLK_CNTL0_DUALDIV_EN == 1
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* - hold M1 cycles of N1 divider then changes to N2
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* - hold M2 cycles of N2 divider then changes to N1
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* Then we can get more accurate division.
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*/
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static unsigned long aoclk_cec_32k_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct aoclk_cec_32k *cec_32k = to_aoclk_cec_32k(hw);
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unsigned long n1;
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u32 reg0, reg1;
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regmap_read(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0, ®0);
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regmap_read(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL1, ®1);
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if (reg1 & CLK_CNTL1_BYPASS_EN)
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return parent_rate;
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if (reg0 & CLK_CNTL0_DUALDIV_EN) {
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unsigned long n2, m1, m2, f1, f2, p1, p2;
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n1 = FIELD_GET(CLK_CNTL0_N1_MASK, reg0) + 1;
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n2 = FIELD_GET(CLK_CNTL0_N2_MASK, reg0) + 1;
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m1 = FIELD_GET(CLK_CNTL1_M1_MASK, reg1) + 1;
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m2 = FIELD_GET(CLK_CNTL1_M2_MASK, reg1) + 1;
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f1 = DIV_ROUND_CLOSEST(parent_rate, n1);
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f2 = DIV_ROUND_CLOSEST(parent_rate, n2);
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p1 = DIV_ROUND_CLOSEST(100000000 * m1, f1 * (m1 + m2));
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p2 = DIV_ROUND_CLOSEST(100000000 * m2, f2 * (m1 + m2));
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return DIV_ROUND_UP(100000000, p1 + p2);
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}
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n1 = FIELD_GET(CLK_CNTL0_N1_MASK, reg0) + 1;
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return DIV_ROUND_CLOSEST(parent_rate, n1);
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}
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static const struct cec_32k_freq_table *find_cec_32k_freq(unsigned long rate,
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unsigned long prate)
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{
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int i;
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for (i = 0 ; i < ARRAY_SIZE(aoclk_cec_32k_table) ; ++i)
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if (aoclk_cec_32k_table[i].parent_rate == prate &&
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aoclk_cec_32k_table[i].target_rate == rate)
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return &aoclk_cec_32k_table[i];
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return NULL;
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}
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static long aoclk_cec_32k_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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const struct cec_32k_freq_table *freq = find_cec_32k_freq(rate,
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*prate);
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/* If invalid return first one */
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if (!freq)
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return aoclk_cec_32k_table[0].target_rate;
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return freq->target_rate;
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}
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/*
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* From the Amlogic init procedure, the IN and OUT gates needs to be handled
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* in the init procedure to avoid any glitches.
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*/
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static int aoclk_cec_32k_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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const struct cec_32k_freq_table *freq = find_cec_32k_freq(rate,
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parent_rate);
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struct aoclk_cec_32k *cec_32k = to_aoclk_cec_32k(hw);
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u32 reg = 0;
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if (!freq)
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return -EINVAL;
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/* Disable clock */
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regmap_update_bits(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0,
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CLK_CNTL0_IN_GATE_EN | CLK_CNTL0_OUT_GATE_EN, 0);
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reg = FIELD_PREP(CLK_CNTL0_N1_MASK, freq->n1 - 1);
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if (freq->dualdiv)
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reg |= CLK_CNTL0_DUALDIV_EN |
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FIELD_PREP(CLK_CNTL0_N2_MASK, freq->n2 - 1);
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regmap_write(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0, reg);
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reg = FIELD_PREP(CLK_CNTL1_M1_MASK, freq->m1 - 1);
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if (freq->dualdiv)
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reg |= FIELD_PREP(CLK_CNTL1_M2_MASK, freq->m2 - 1);
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regmap_write(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL1, reg);
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/* Enable clock */
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regmap_update_bits(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0,
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CLK_CNTL0_IN_GATE_EN, CLK_CNTL0_IN_GATE_EN);
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udelay(200);
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regmap_update_bits(cec_32k->regmap, AO_RTC_ALT_CLK_CNTL0,
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CLK_CNTL0_OUT_GATE_EN, CLK_CNTL0_OUT_GATE_EN);
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regmap_update_bits(cec_32k->regmap, AO_CRT_CLK_CNTL1,
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CLK_CNTL1_SELECT_OSC, CLK_CNTL1_SELECT_OSC);
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/* Select 32k from XTAL */
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regmap_update_bits(cec_32k->regmap,
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AO_RTI_PWR_CNTL_REG0,
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PWR_CNTL_ALT_32K_SEL,
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FIELD_PREP(PWR_CNTL_ALT_32K_SEL, 4));
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return 0;
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}
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const struct clk_ops meson_aoclk_cec_32k_ops = {
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.recalc_rate = aoclk_cec_32k_recalc_rate,
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.round_rate = aoclk_cec_32k_round_rate,
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.set_rate = aoclk_cec_32k_set_rate,
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};
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